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GET /api/patches/138031/?format=api
{ "id": 138031, "url": "http://patches.dpdk.org/api/patches/138031/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240306122445.4350-19-shaibran@amazon.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240306122445.4350-19-shaibran@amazon.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240306122445.4350-19-shaibran@amazon.com", "date": "2024-03-06T12:24:30", "name": "[v3,18/33] net/ena/hal: add unlikely to error checks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6253a3cc1383b08e4af9782aa57fb9567e94a606", "submitter": { "id": 2930, "url": "http://patches.dpdk.org/api/people/2930/?format=api", "name": "Brandes, Shai", "email": "shaibran@amazon.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240306122445.4350-19-shaibran@amazon.com/mbox/", "series": [ { "id": 31397, "url": "http://patches.dpdk.org/api/series/31397/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31397", "date": "2024-03-06T12:24:13", "name": "net/ena: v2.9.0 driver release", "version": 3, "mbox": "http://patches.dpdk.org/series/31397/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138031/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/138031/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C7C543C5B;\n\tWed, 6 Mar 2024 13:27:20 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4224342E7F;\n\tWed, 6 Mar 2024 13:25:33 +0100 (CET)", "from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com\n [207.171.184.29])\n by mails.dpdk.org (Postfix) with ESMTP id 69FF842E7F\n for <dev@dpdk.org>; Wed, 6 Mar 2024 13:25:30 +0100 (CET)", "from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO\n smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214])\n by smtp-border-fw-9102.sea19.amazon.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2024 12:25:29 +0000", "from EX19MTAEUA002.ant.amazon.com [10.0.43.254:20173]\n by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.11.111:2525]\n with esmtp (Farcaster)\n id 00490787-463f-439a-8fac-63527d1bfaed; Wed, 6 Mar 2024 12:25:28 +0000 (UTC)", "from EX19D007EUA001.ant.amazon.com (10.252.50.133) by\n EX19MTAEUA002.ant.amazon.com (10.252.50.124) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Wed, 6 Mar 2024 12:25:27 +0000", "from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by\n EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Wed, 6 Mar 2024 12:25:27 +0000", "from HFA15-CG15235BS.amazon.com (10.1.213.21) by\n mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id\n 15.2.1258.28 via Frontend Transport; Wed, 6 Mar 2024 12:25:25 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209;\n t=1709727930; x=1741263930;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version;\n bh=W/XY09LKHAfxeHeUsu35gK3VP2dCbMYwYzKcHfzr2sc=;\n b=NUBJvbdHbAroV4MUj4K/1A3DcEaw6SnsAfhLwSKfZljFVnoFu7Q5k5k9\n 0DOMqqFbEqGcHmaXaf8cxqBzHJA0alJOOSOBkek3707+YQgUfLuaYFEVo\n SMa4ACU4GJ/rmoWouumg1gY/cMNE3a71BPkVOzn/PN/C4lTRnwIBOhUzt I=;", "X-IronPort-AV": "E=Sophos;i=\"6.06,208,1705363200\"; d=\"scan'208\";a=\"401934692\"", "X-Farcaster-Flow-ID": "00490787-463f-439a-8fac-63527d1bfaed", "From": "<shaibran@amazon.com>", "To": "<ferruh.yigit@amd.com>", "CC": "<dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>", "Subject": "[PATCH v3 18/33] net/ena/hal: add unlikely to error checks", "Date": "Wed, 6 Mar 2024 14:24:30 +0200", "Message-ID": "<20240306122445.4350-19-shaibran@amazon.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240306122445.4350-1-shaibran@amazon.com>", "References": "<20240306122445.4350-1-shaibran@amazon.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shai Brandes <shaibran@amazon.com>\n\nThe unlikely mechanism is used to reduce pipe flush,\ncaused by a wrong branch prediction.\nMoreover, it increases readability by wrapping unexpected errors.\nThis commit adds unlikely to error checks that are unlikely to happen.\n\nSigned-off-by: Shai Brandes <shaibran@amazon.com>\nReviewed-by: Amit Bernstein <amitbern@amazon.com>\n---\n drivers/net/ena/hal/ena_com.c | 56 +++++++++++++++----------------\n drivers/net/ena/hal/ena_eth_com.c | 2 +-\n 2 files changed, 29 insertions(+), 29 deletions(-)", "diff": "diff --git a/drivers/net/ena/hal/ena_com.c b/drivers/net/ena/hal/ena_com.c\nindex a0c88b1a0e..d2de5e172d 100644\n--- a/drivers/net/ena/hal/ena_com.c\n+++ b/drivers/net/ena/hal/ena_com.c\n@@ -79,7 +79,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,\n \t\t\t\t struct ena_common_mem_addr *ena_addr,\n \t\t\t\t dma_addr_t addr)\n {\n-\tif ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {\n+\tif (unlikely((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr)) {\n \t\tena_trc_err(ena_dev, \"DMA address has more bits than the device supports\\n\");\n \t\treturn ENA_COM_INVAL;\n \t}\n@@ -99,7 +99,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)\n \tENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, sq->entries, sq->dma_addr,\n \t\t\t sq->mem_handle);\n \n-\tif (!sq->entries) {\n+\tif (unlikely(!sq->entries)) {\n \t\tena_trc_err(ena_dev, \"Memory allocation failed\\n\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n@@ -122,7 +122,7 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)\n \tENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, cq->entries, cq->dma_addr,\n \t\t\t cq->mem_handle);\n \n-\tif (!cq->entries) {\n+\tif (unlikely(!cq->entries)) {\n \t\tena_trc_err(ena_dev, \"Memory allocation failed\\n\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n@@ -147,7 +147,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,\n \t\t\taenq->dma_addr,\n \t\t\taenq->mem_handle);\n \n-\tif (!aenq->entries) {\n+\tif (unlikely(!aenq->entries)) {\n \t\tena_trc_err(ena_dev, \"Memory allocation failed\\n\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n@@ -233,7 +233,7 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu\n \n \t/* In case of queue FULL */\n \tcnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);\n-\tif (cnt >= admin_queue->q_depth) {\n+\tif (unlikely(cnt >= admin_queue->q_depth)) {\n \t\tena_trc_dbg(admin_queue->ena_dev, \"Admin queue is full.\\n\");\n \t\tadmin_queue->stats.out_of_space++;\n \t\treturn ERR_PTR(ENA_COM_NO_SPACE);\n@@ -357,7 +357,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,\n \t\t\t\t\t io_sq->desc_addr.mem_handle);\n \t\t}\n \n-\t\tif (!io_sq->desc_addr.virt_addr) {\n+\t\tif (unlikely(!io_sq->desc_addr.virt_addr)) {\n \t\t\tena_trc_err(ena_dev, \"Memory allocation failed\\n\");\n \t\t\treturn ENA_COM_NO_MEM;\n \t\t}\n@@ -382,7 +382,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,\n \t\tif (!io_sq->bounce_buf_ctrl.base_buffer)\n \t\t\tio_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);\n \n-\t\tif (!io_sq->bounce_buf_ctrl.base_buffer) {\n+\t\tif (unlikely(!io_sq->bounce_buf_ctrl.base_buffer)) {\n \t\t\tena_trc_err(ena_dev, \"Bounce buffer memory allocation failed\\n\");\n \t\t\treturn ENA_COM_NO_MEM;\n \t\t}\n@@ -447,7 +447,7 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,\n \t\t\t\t\t ENA_CDESC_RING_SIZE_ALIGNMENT);\n \t}\n \n-\tif (!io_cq->cdesc_addr.virt_addr) {\n+\tif (unlikely(!io_cq->cdesc_addr.virt_addr)) {\n \t\tena_trc_err(ena_dev, \"Memory allocation failed\\n\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n@@ -577,7 +577,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c\n \t\tif (comp_ctx->status != ENA_CMD_SUBMITTED)\n \t\t\tbreak;\n \n-\t\tif (ENA_TIME_EXPIRE(timeout)) {\n+\t\tif (unlikely(ENA_TIME_EXPIRE(timeout))) {\n \t\t\tena_trc_err(admin_queue->ena_dev,\n \t\t\t\t \"Wait for completion (polling) timeout\\n\");\n \t\t\t/* ENA didn't have any completion */\n@@ -776,7 +776,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,\n \t\t\tllq_default_cfg->llq_ring_entry_size_value;\n \n \trc = ena_com_set_llq(ena_dev);\n-\tif (rc)\n+\tif (unlikely(rc))\n \t\tena_trc_err(ena_dev, \"Cannot set LLQ configuration: %d\\n\", rc);\n \n \treturn rc;\n@@ -882,7 +882,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)\n \t\tgoto err;\n \t}\n \n-\tif (read_resp->reg_off != offset) {\n+\tif (unlikely(read_resp->reg_off != offset)) {\n \t\tena_trc_err(ena_dev, \"Read failure: wrong offset provided\\n\");\n \t\tret = ENA_MMIO_READ_TIMEOUT;\n \t} else {\n@@ -1006,7 +1006,7 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,\n \t\t\texp_state)\n \t\t\treturn 0;\n \n-\t\tif (ENA_TIME_EXPIRE(timeout_stamp))\n+\t\tif (unlikely(ENA_TIME_EXPIRE(timeout_stamp)))\n \t\t\treturn ENA_COM_TIMER_EXPIRED;\n \n \t\tena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);\n@@ -1467,7 +1467,7 @@ int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,\n \t\t\t struct ena_com_io_sq **io_sq,\n \t\t\t struct ena_com_io_cq **io_cq)\n {\n-\tif (qid >= ENA_TOTAL_NUM_QUEUES) {\n+\tif (unlikely(qid >= ENA_TOTAL_NUM_QUEUES)) {\n \t\tena_trc_err(ena_dev, \"Invalid queue number %d but the max is %d\\n\",\n \t\t\t qid, ENA_TOTAL_NUM_QUEUES);\n \t\treturn ENA_COM_INVAL;\n@@ -1575,7 +1575,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)\n \tint ret;\n \n \tret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);\n-\tif (ret) {\n+\tif (unlikely(ret)) {\n \t\tena_trc_info(ena_dev, \"Can't get aenq configuration\\n\");\n \t\treturn ret;\n \t}\n@@ -1622,7 +1622,7 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev)\n \n \tena_trc_dbg(ena_dev, \"ENA dma width: %d\\n\", width);\n \n-\tif ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {\n+\tif (unlikely(width < 32 || width > ENA_MAX_PHYS_ADDR_SIZE_BITS)) {\n \t\tena_trc_err(ena_dev, \"DMA width illegal value: %d\\n\", width);\n \t\treturn ENA_COM_INVAL;\n \t}\n@@ -2092,15 +2092,15 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,\n \tENA_SPINLOCK_INIT(admin_queue->q_lock);\n \n \tret = ena_com_init_comp_ctxt(admin_queue);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \n \tret = ena_com_admin_init_sq(admin_queue);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \n \tret = ena_com_admin_init_cq(admin_queue);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \n \tadmin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +\n@@ -2133,7 +2133,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,\n \tENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);\n \tENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);\n \tret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \n \tadmin_queue->ena_dev = ena_dev;\n@@ -2153,7 +2153,7 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev,\n \tstruct ena_com_io_cq *io_cq;\n \tint ret;\n \n-\tif (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {\n+\tif (unlikely(ctx->qid >= ENA_TOTAL_NUM_QUEUES)) {\n \t\tena_trc_err(ena_dev, \"Qid (%d) is bigger than max num of queues (%d)\\n\",\n \t\t\t ctx->qid, ENA_TOTAL_NUM_QUEUES);\n \t\treturn ENA_COM_INVAL;\n@@ -2184,18 +2184,18 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev,\n \t\t\tENA_MIN32(ena_dev->tx_max_header_size, SZ_256);\n \n \tret = ena_com_init_io_sq(ena_dev, ctx, io_sq);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \tret = ena_com_init_io_cq(ena_dev, ctx, io_cq);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \n \tret = ena_com_create_io_cq(ena_dev, io_cq);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto error;\n \n \tret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);\n-\tif (ret)\n+\tif (unlikely(ret))\n \t\tgoto destroy_io_cq;\n \n \treturn 0;\n@@ -2212,7 +2212,7 @@ void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)\n \tstruct ena_com_io_sq *io_sq;\n \tstruct ena_com_io_cq *io_cq;\n \n-\tif (qid >= ENA_TOTAL_NUM_QUEUES) {\n+\tif (unlikely(qid >= ENA_TOTAL_NUM_QUEUES)) {\n \t\tena_trc_err(ena_dev, \"Qid (%d) is bigger than max num of queues (%d)\\n\",\n \t\t\t qid, ENA_TOTAL_NUM_QUEUES);\n \t\treturn;\n@@ -2513,7 +2513,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n \n \trc = wait_for_reset_state(ena_dev, timeout,\n \t\t\t\t ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);\n-\tif (rc != 0) {\n+\tif (unlikely(rc)) {\n \t\tena_trc_err(ena_dev, \"Reset indication didn't turn on\\n\");\n \t\treturn rc;\n \t}\n@@ -2521,7 +2521,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n \t/* reset done */\n \tENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);\n \trc = wait_for_reset_state(ena_dev, timeout, 0);\n-\tif (rc != 0) {\n+\tif (unlikely(rc)) {\n \t\tena_trc_err(ena_dev, \"Reset indication didn't turn off\\n\");\n \t\treturn rc;\n \t}\n@@ -3383,7 +3383,7 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,\n \t}\n \n \trc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);\n-\tif (rc)\n+\tif (unlikely(rc))\n \t\treturn rc;\n \n \tena_dev->tx_max_header_size = llq_info->desc_list_entry_size -\ndiff --git a/drivers/net/ena/hal/ena_eth_com.c b/drivers/net/ena/hal/ena_eth_com.c\nindex 988fa013a7..b9123f84c3 100644\n--- a/drivers/net/ena/hal/ena_eth_com.c\n+++ b/drivers/net/ena/hal/ena_eth_com.c\n@@ -455,7 +455,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,\n \t/* If the caller doesn't want to send packets */\n \tif (unlikely(!num_bufs && !header_len)) {\n \t\trc = ena_com_close_bounce_buffer(io_sq);\n-\t\tif (rc)\n+\t\tif (unlikely(rc))\n \t\t\tena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),\n \t\t\t\t \"Failed to write buffers to LLQ\\n\");\n \t\t*nb_hw_desc = io_sq->tail - start_tail;\n", "prefixes": [ "v3", "18/33" ] }