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GET /api/patches/136853/?format=api
{ "id": 136853, "url": "http://patches.dpdk.org/api/patches/136853/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240216170704.55523-2-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240216170704.55523-2-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240216170704.55523-2-andrew.boyer@amd.com", "date": "2024-02-16T17:07:02", "name": "[1/3] common/ionic: create common code library for ionic", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c396649de56b6017c3c9c7503e9ea1b1e858ebe4", "submitter": { "id": 2861, "url": "http://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240216170704.55523-2-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31131, "url": "http://patches.dpdk.org/api/series/31131/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31131", "date": "2024-02-16T17:07:01", "name": "net/ionic, common/ionic: add vdev support", "version": 1, "mbox": "http://patches.dpdk.org/series/31131/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136853/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/136853/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=cyw+8CvwBVVbxTRuaNd0V62WcKlecKM4p86GMGRcXVHhbIwKS5eUVkb4YgbKr9gsoJEl3kdhviaFxB751xwmUfhwWqFJYdDlwICEXSHkOKrJKnJ+TEELGxNHGqsWbtlMGg2swRpeDbCyIDIeNwenTh5SpfR3xJOaG2mojk4ZKGQ=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH 1/3] common/ionic: create common code library for ionic", "Date": "Fri, 16 Feb 2024 09:07:02 -0800", "Message-ID": "<20240216170704.55523-2-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240216170704.55523-1-andrew.boyer@amd.com>", "References": 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SFS:(13230031)(4636009)(346002)(136003)(39860400002)(376002)(396003)(230922051799003)(36860700004)(451199024)(1800799012)(82310400011)(186009)(64100799003)(40470700004)(46966006)(82740400003)(86362001)(356005)(36756003)(81166007)(316002)(6666004)(41300700001)(478600001)(426003)(336012)(83380400001)(1076003)(2616005)(26005)(16526019)(2906002)(4326008)(6916009)(8936002)(30864003)(8676002)(44832011)(5660300002)(70206006)(70586007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Feb 2024 17:07:38.3596 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4cbebf35-023e-47b4-8387-08dc2f11c75a", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989EC.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4457", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Move definitions that will be shared by net/ionic and crypto/ionic.\nAdd the code used for discovering UIO vdevs.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n MAINTAINERS | 1 +\n drivers/common/ionic/ionic_common.h | 41 +++\n drivers/common/ionic/ionic_common_uio.c | 283 ++++++++++++++++++++\n drivers/{net => common}/ionic/ionic_osdep.h | 37 ++-\n drivers/{net => common}/ionic/ionic_regs.h | 49 +++-\n drivers/common/ionic/meson.build | 12 +\n drivers/common/ionic/version.map | 9 +\n drivers/common/meson.build | 1 +\n drivers/net/ionic/ionic.h | 3 +-\n drivers/net/ionic/ionic_dev.h | 26 +-\n drivers/net/ionic/ionic_dev_pci.c | 2 +-\n drivers/net/ionic/ionic_if.h | 125 ---------\n drivers/net/ionic/ionic_rx_filter.h | 1 -\n drivers/net/ionic/ionic_rxtx_sg.c | 3 +-\n drivers/net/ionic/ionic_rxtx_simple.c | 3 +-\n drivers/net/ionic/meson.build | 4 +\n 16 files changed, 419 insertions(+), 181 deletions(-)\n create mode 100644 drivers/common/ionic/ionic_common.h\n create mode 100644 drivers/common/ionic/ionic_common_uio.c\n rename drivers/{net => common}/ionic/ionic_osdep.h (53%)\n rename drivers/{net => common}/ionic/ionic_regs.h (74%)\n create mode 100644 drivers/common/ionic/meson.build\n create mode 100644 drivers/common/ionic/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 5fb3a73f84..8a8199a82d 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -654,6 +654,7 @@ F: doc/guides/nics/features/axgbe.ini\n \n AMD Pensando ionic\n M: Andrew Boyer <andrew.boyer@amd.com>\n+F: drivers/common/ionic/\n F: drivers/net/ionic/\n F: doc/guides/nics/ionic.rst\n F: doc/guides/nics/features/ionic.ini\ndiff --git a/drivers/common/ionic/ionic_common.h b/drivers/common/ionic/ionic_common.h\nnew file mode 100644\nindex 0000000000..eb4850e24c\n--- /dev/null\n+++ b/drivers/common/ionic/ionic_common.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2018-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef _IONIC_COMMON_H_\n+#define _IONIC_COMMON_H_\n+\n+#include <stdint.h>\n+#include <assert.h>\n+\n+#include <rte_common.h>\n+#include <rte_memory.h>\n+#include <rte_eal_paging.h>\n+\n+#include \"ionic_osdep.h\"\n+\n+#define IONIC_DEVCMD_TIMEOUT\t\t5\t/* devcmd_timeout */\n+#define IONIC_DEVCMD_CHECK_PERIOD_US\t10\t/* devcmd status chk period */\n+#define IONIC_DEVCMD_RETRY_WAIT_US\t20000\n+\n+#define IONIC_Q_WDOG_MS\t\t\t10\t/* 10ms */\n+#define IONIC_Q_WDOG_MAX_MS\t\t5000\t/* 5s */\n+#define IONIC_ADMINQ_WDOG_MS\t\t500\t/* 500ms */\n+\n+#define IONIC_ALIGN\t\t\t4096\n+\n+struct ionic_dev_bar {\n+\tvoid __iomem *vaddr;\n+\trte_iova_t bus_addr;\n+\tunsigned long len;\n+};\n+\n+__rte_internal\n+void ionic_uio_scan_mnet_devices(void);\n+\n+__rte_internal\n+void ionic_uio_get_rsrc(const char *name, int idx, struct ionic_dev_bar *bar);\n+__rte_internal\n+void ionic_uio_rel_rsrc(const char *name, int idx, struct ionic_dev_bar *bar);\n+\n+#endif /* _IONIC_COMMON_H_ */\ndiff --git a/drivers/common/ionic/ionic_common_uio.c b/drivers/common/ionic/ionic_common_uio.c\nnew file mode 100644\nindex 0000000000..a12131301e\n--- /dev/null\n+++ b/drivers/common/ionic/ionic_common_uio.c\n@@ -0,0 +1,283 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2018-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <string.h>\n+#include <unistd.h>\n+#include <stdarg.h>\n+#include <inttypes.h>\n+#include <sys/mman.h>\n+#include <sys/stat.h>\n+#include <dirent.h>\n+#include <stdlib.h>\n+#include <fcntl.h>\n+#include <stdbool.h>\n+\n+#include <rte_common.h>\n+#include <rte_eal.h>\n+#include <rte_string_fns.h>\n+\n+#include \"ionic_common.h\"\n+\n+#define IONIC_MDEV_UNK \"mdev_unknown\"\n+#define IONIC_MNIC \"cpu_mnic\"\n+\n+#define IONIC_MAX_NAME_LEN 20\n+#define IONIC_MAX_MNETS 5\n+#define IONIC_MAX_DEVICES (IONIC_MAX_MNETS)\n+#define IONIC_MAX_U16_IDX 0xFFFF\n+#define IONIC_UIO_MAX_TRIES 32\n+\n+/*\n+ * Note: the driver can assign any idx number\n+ * in the range [0-IONIC_MAX_MDEV_SCAN)\n+ */\n+#define IONIC_MAX_MDEV_SCAN 32\n+\n+struct ionic_map_tbl {\n+\tchar dev_name[IONIC_MAX_NAME_LEN];\n+\tuint16_t dev_idx;\n+\tuint16_t uio_idx;\n+\tchar mdev_name[IONIC_MAX_NAME_LEN];\n+};\n+\n+struct ionic_map_tbl ionic_mdev_map[IONIC_MAX_DEVICES] = {\n+\t{ \"net_ionic0\", 0, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n+\t{ \"net_ionic1\", 1, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n+\t{ \"net_ionic2\", 2, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n+\t{ \"net_ionic3\", 3, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n+\t{ \"net_ionic4\", 4, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n+};\n+\n+struct uio_name {\n+\tuint16_t idx;\n+\tchar name[IONIC_MAX_NAME_LEN];\n+};\n+\n+static void\n+uio_fill_name_cache(struct uio_name *name_cache, const char *pfx)\n+{\n+\tchar file[64];\n+\tFILE *fp;\n+\tchar *ret;\n+\tint name_idx = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < IONIC_UIO_MAX_TRIES &&\n+\t\t\tname_idx < IONIC_MAX_DEVICES; i++) {\n+\t\tsprintf(file, \"/sys/class/uio/uio%d/name\", i);\n+\n+\t\tfp = fopen(file, \"r\");\n+\t\tif (fp == NULL)\n+\t\t\tcontinue;\n+\n+\t\tret = fgets(name_cache[name_idx].name, IONIC_MAX_NAME_LEN, fp);\n+\t\tif (ret == NULL) {\n+\t\t\tfclose(fp);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tname_cache[name_idx].idx = i;\n+\n+\t\tfclose(fp);\n+\n+\t\tif (strncmp(name_cache[name_idx].name, pfx, strlen(pfx)) == 0)\n+\t\t\tname_idx++;\n+\t}\n+}\n+\n+static int\n+uio_get_idx_for_devname(struct uio_name *name_cache, char *devname)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < IONIC_MAX_DEVICES; i++)\n+\t\tif (strncmp(name_cache[i].name, devname, strlen(devname)) == 0)\n+\t\t\treturn name_cache[i].idx;\n+\n+\treturn -1;\n+}\n+\n+void\n+ionic_uio_scan_mnet_devices(void)\n+{\n+\tstruct ionic_map_tbl *map;\n+\tchar devname[IONIC_MAX_NAME_LEN];\n+\tstruct uio_name name_cache[IONIC_MAX_DEVICES];\n+\tbool done;\n+\tint mdev_idx = 0;\n+\tint uio_idx;\n+\tint i;\n+\n+\tuio_fill_name_cache(name_cache, IONIC_MNIC);\n+\n+\tfor (i = 0; i < IONIC_MAX_MNETS; i++) {\n+\t\tdone = false;\n+\n+\t\twhile (!done) {\n+\t\t\tif (mdev_idx > IONIC_MAX_MDEV_SCAN)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* Look for a matching mnic */\n+\t\t\tsnprintf(devname, IONIC_MAX_NAME_LEN,\n+\t\t\t\tIONIC_MNIC \"%d\", mdev_idx);\n+\t\t\tuio_idx = uio_get_idx_for_devname(name_cache, devname);\n+\t\t\tif (uio_idx >= 0) {\n+\t\t\t\tmap = &ionic_mdev_map[i];\n+\t\t\t\tmap->uio_idx = (uint16_t)uio_idx;\n+\t\t\t\tstrlcpy(map->mdev_name, devname,\n+\t\t\t\t\tIONIC_MAX_NAME_LEN);\n+\t\t\t\tdone = true;\n+\t\t\t}\n+\n+\t\t\tmdev_idx++;\n+\t\t}\n+\t}\n+}\n+\n+static int\n+uio_get_multi_dev_uionum(const char *name)\n+{\n+\tstruct ionic_map_tbl *map;\n+\tint i;\n+\n+\tfor (i = 0; i < IONIC_MAX_DEVICES; i++) {\n+\t\tmap = &ionic_mdev_map[i];\n+\t\tif (strncmp(map->dev_name, name, IONIC_MAX_NAME_LEN) == 0) {\n+\t\t\tif (map->uio_idx == IONIC_MAX_U16_IDX)\n+\t\t\t\treturn -1;\n+\t\t\telse\n+\t\t\t\treturn map->uio_idx;\n+\t\t}\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static unsigned long\n+uio_get_res_size(int uio_idx, int res_idx)\n+{\n+\tunsigned long size;\n+\tchar file[64];\n+\tFILE *fp;\n+\n+\tsprintf(file, \"/sys/class/uio/uio%d/maps/map%d/size\",\n+\t\tuio_idx, res_idx);\n+\n+\tfp = fopen(file, \"r\");\n+\tif (fp == NULL)\n+\t\treturn 0;\n+\n+\tif (fscanf(fp, \"0x%lx\", &size) != 1)\n+\t\tsize = 0;\n+\n+\tfclose(fp);\n+\n+\treturn size;\n+}\n+\n+static unsigned long\n+uio_get_res_phy_addr_offs(int uio_idx, int res_idx)\n+{\n+\tunsigned long offset;\n+\tchar file[64];\n+\tFILE *fp;\n+\n+\tsprintf(file, \"/sys/class/uio/uio%d/maps/map%d/offset\",\n+\t\tuio_idx, res_idx);\n+\n+\tfp = fopen(file, \"r\");\n+\tif (fp == NULL)\n+\t\treturn 0;\n+\n+\tif (fscanf(fp, \"0x%lx\", &offset) != 1)\n+\t\toffset = 0;\n+\n+\tfclose(fp);\n+\n+\treturn offset;\n+}\n+\n+static unsigned long\n+uio_get_res_phy_addr(int uio_idx, int res_idx)\n+{\n+\tunsigned long addr;\n+\tchar file[64];\n+\tFILE *fp;\n+\n+\tsprintf(file, \"/sys/class/uio/uio%d/maps/map%d/addr\",\n+\t\tuio_idx, res_idx);\n+\n+\tfp = fopen(file, \"r\");\n+\tif (fp == NULL)\n+\t\treturn 0;\n+\n+\tif (fscanf(fp, \"0x%lx\", &addr) != 1)\n+\t\taddr = 0;\n+\n+\tfclose(fp);\n+\n+\treturn addr;\n+}\n+\n+static void *\n+uio_get_map_res_addr(int uio_idx, int size, int res_idx)\n+{\n+\tchar name[64];\n+\tint fd;\n+\tvoid *addr;\n+\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\tsprintf(name, \"/dev/uio%d\", uio_idx);\n+\n+\tfd = open(name, O_RDWR);\n+\tif (fd < 0)\n+\t\treturn NULL;\n+\n+\tif (size < getpagesize())\n+\t\tsize = getpagesize();\n+\n+\taddr = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED,\n+\t\t\t\tfd, res_idx * getpagesize());\n+\n+\tclose(fd);\n+\n+\treturn addr;\n+}\n+\n+void\n+ionic_uio_get_rsrc(const char *name, int idx, struct ionic_dev_bar *bar)\n+{\n+\tint num;\n+\tint offs;\n+\n+\tnum = uio_get_multi_dev_uionum(name);\n+\tif (num < 0)\n+\t\treturn;\n+\n+\tbar->len = uio_get_res_size(num, idx);\n+\toffs = uio_get_res_phy_addr_offs(num, idx);\n+\tbar->bus_addr = uio_get_res_phy_addr(num, idx);\n+\tbar->bus_addr += offs;\n+\tbar->vaddr = uio_get_map_res_addr(num, bar->len, idx);\n+\tbar->vaddr = ((char *)bar->vaddr) + offs;\n+}\n+\n+void\n+ionic_uio_rel_rsrc(const char *name, int idx, struct ionic_dev_bar *bar)\n+{\n+\tint num, offs;\n+\n+\tnum = uio_get_multi_dev_uionum(name);\n+\tif (num < 0)\n+\t\treturn;\n+\tif (bar->vaddr == NULL)\n+\t\treturn;\n+\n+\toffs = uio_get_res_phy_addr_offs(num, idx);\n+\tmunmap(((char *)bar->vaddr) - offs, bar->len);\n+}\ndiff --git a/drivers/net/ionic/ionic_osdep.h b/drivers/common/ionic/ionic_osdep.h\nsimilarity index 53%\nrename from drivers/net/ionic/ionic_osdep.h\nrename to drivers/common/ionic/ionic_osdep.h\nindex 68f767b920..029bc5f4fb 100644\n--- a/drivers/net/ionic/ionic_osdep.h\n+++ b/drivers/common/ionic/ionic_osdep.h\n@@ -1,47 +1,40 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright 2018-2022 Advanced Micro Devices, Inc.\n+ * Copyright 2018-2024 Advanced Micro Devices, Inc.\n */\n \n #ifndef _IONIC_OSDEP_\n #define _IONIC_OSDEP_\n \n-#include <string.h>\n #include <stdint.h>\n-#include <stdio.h>\n #include <stdarg.h>\n \n #include <rte_common.h>\n-#include <rte_debug.h>\n-#include <rte_cycles.h>\n-#include <rte_log.h>\n-#include <rte_byteorder.h>\n #include <rte_io.h>\n-#include <rte_memory.h>\n-#include <rte_eal_paging.h>\n-\n-#include \"ionic_logs.h\"\n-\n-#define BIT(nr) (1UL << (nr))\n-#define BIT_ULL(nr) (1ULL << (nr))\n+#include <rte_byteorder.h>\n \n-#ifndef PAGE_SHIFT\n-#define PAGE_SHIFT 12\n-#endif\n+#define BIT(nr)\t\t(1UL << (nr))\n+#define BIT_ULL(nr)\t(1ULL << (nr))\n \n #define __iomem\n \n-typedef uint8_t\t u8;\n+typedef uint8_t u8;\n typedef uint16_t u16;\n typedef uint32_t u32;\n typedef uint64_t u64;\n \n-typedef uint16_t __le16;\n-typedef uint32_t __le32;\n-typedef uint64_t __le64;\n+#ifndef __le16\n+#define __le16 uint16_t\n+#endif\n+#ifndef __le32\n+#define __le32 uint32_t\n+#endif\n+#ifndef __le64\n+#define __le64 uint64_t\n+#endif\n \n #define ioread8(reg)\t\trte_read8(reg)\n #define ioread32(reg)\t\trte_read32(rte_le_to_cpu_32(reg))\n #define iowrite8(value, reg)\trte_write8(value, reg)\n #define iowrite32(value, reg)\trte_write32(rte_cpu_to_le_32(value), reg)\n \n-#endif\n+#endif /* _IONIC_OSDEP_ */\ndiff --git a/drivers/net/ionic/ionic_regs.h b/drivers/common/ionic/ionic_regs.h\nsimilarity index 74%\nrename from drivers/net/ionic/ionic_regs.h\nrename to drivers/common/ionic/ionic_regs.h\nindex b4c665a58d..bb97e9c6eb 100644\n--- a/drivers/net/ionic/ionic_regs.h\n+++ b/drivers/common/ionic/ionic_regs.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright 2018-2022 Advanced Micro Devices, Inc.\n+ * Copyright 2018-2024 Advanced Micro Devices, Inc.\n */\n \n #ifndef _IONIC_REGS_H_\n@@ -46,6 +46,19 @@ enum ionic_intr_credits_bits {\n \t\t\t\t\t IONIC_INTR_CRED_RESET_COALESCE),\n };\n \n+#define IONIC_INTR_NONE\t\t\t(-1)\n+#define IONIC_INTR_CTRL_REGS_MAX\t2048\n+\n+struct ionic_intr_info {\n+\tint index;\n+\tuint32_t vector;\n+\tstruct ionic_intr __iomem *ctrl;\n+};\n+\n+struct ionic_intr_status {\n+\tuint32_t status[2];\n+};\n+\n static inline void\n ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,\n \t\tint intr_idx, uint32_t coal)\n@@ -65,7 +78,6 @@ ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,\n \t\tint intr_idx, uint32_t cred, uint32_t flags)\n {\n \tif (cred > IONIC_INTR_CRED_COUNT) {\n-\t\tIONIC_WARN_ON(cred > IONIC_INTR_CRED_COUNT);\n \t\tcred = ioread32(&intr_ctrl[intr_idx].credits);\n \t\tcred &= IONIC_INTR_CRED_COUNT_SIGNED;\n \t}\n@@ -130,4 +142,37 @@ enum ionic_dbell_bits {\n \tIONIC_DBELL_INDEX_MASK\t\t= 0xffff,\n };\n \n+#define IONIC_BARS_MIN\t\t\t\t2\n+#define IONIC_BARS_MAX\t\t\t\t6\n+#define IONIC_PCI_BAR_DBELL\t\t\t1\n+\n+/* BAR0 */\n+#define IONIC_BAR0_SIZE\t\t\t\t0x8000\n+\n+#define IONIC_BAR0_DEV_INFO_REGS_OFFSET\t\t0x0000\n+#define IONIC_BAR0_DEV_CMD_REGS_OFFSET\t\t0x0800\n+#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET\t0x0c00\n+#define IONIC_BAR0_INTR_STATUS_OFFSET\t\t0x1000\n+#define IONIC_BAR0_INTR_CTRL_OFFSET\t\t0x2000\n+#define IONIC_DEV_CMD_DONE\t\t\t0x00000001\n+\n+/**\n+ * struct ionic_doorbell - Doorbell register layout\n+ * @p_index: Producer index\n+ * @ring: Selects the specific ring of the queue to update\n+ * Type-specific meaning:\n+ * ring=0: Default producer/consumer queue\n+ * ring=1: (CQ, EQ) Re-Arm queue. CQs send events to EQs\n+ * when armed. EQs send interrupts when armed.\n+ * @qid_lo: Queue destination for the producer index and flags (low bits)\n+ * @qid_hi: Queue destination for the producer index and flags (high bits)\n+ */\n+struct ionic_doorbell {\n+\t__le16 p_index;\n+\tu8 ring;\n+\tu8 qid_lo;\n+\t__le16 qid_hi;\n+\tu16 rsvd2;\n+};\n+\n #endif /* _IONIC_REGS_H_ */\ndiff --git a/drivers/common/ionic/meson.build b/drivers/common/ionic/meson.build\nnew file mode 100644\nindex 0000000000..51f6f3c7bd\n--- /dev/null\n+++ b/drivers/common/ionic/meson.build\n@@ -0,0 +1,12 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright 2018-2022 Advanced Micro Devices, Inc.\n+\n+if is_windows\n+ build = false\n+ reason = 'not supported on Windows'\n+ subdir_done()\n+endif\n+\n+sources = files(\n+ 'ionic_common_uio.c',\n+)\ndiff --git a/drivers/common/ionic/version.map b/drivers/common/ionic/version.map\nnew file mode 100644\nindex 0000000000..484330c437\n--- /dev/null\n+++ b/drivers/common/ionic/version.map\n@@ -0,0 +1,9 @@\n+INTERNAL {\n+\tglobal:\n+\n+\tionic_uio_scan_mnet_devices;\n+\tionic_uio_get_rsrc;\n+\tionic_uio_rel_rsrc;\n+\n+\tlocal: *;\n+};\ndiff --git a/drivers/common/meson.build b/drivers/common/meson.build\nindex b63d899d50..8734af36aa 100644\n--- a/drivers/common/meson.build\n+++ b/drivers/common/meson.build\n@@ -7,6 +7,7 @@ drivers = [\n 'dpaax',\n 'iavf',\n 'idpf',\n+ 'ionic',\n 'mvep',\n 'octeontx',\n ]\ndiff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h\nindex cb4ea450a9..a4a2e2756d 100644\n--- a/drivers/net/ionic/ionic.h\n+++ b/drivers/net/ionic/ionic.h\n@@ -8,9 +8,10 @@\n #include <stdint.h>\n #include <inttypes.h>\n \n+#include \"ionic_common.h\"\n #include \"ionic_dev.h\"\n #include \"ionic_if.h\"\n-#include \"ionic_osdep.h\"\n+#include \"ionic_logs.h\"\n \n #define IONIC_DRV_NAME\t\t\t\"ionic\"\n #define IONIC_DRV_DESCRIPTION\t\t\"AMD Pensando Ethernet NIC Driver\"\ndiff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex 3a366247f1..b8eebcd181 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -7,7 +7,7 @@\n \n #include <stdbool.h>\n \n-#include \"ionic_osdep.h\"\n+#include \"ionic_common.h\"\n #include \"ionic_if.h\"\n #include \"ionic_regs.h\"\n \n@@ -22,24 +22,8 @@\n #define IONIC_DEF_TXRX_DESC\t\t4096\n #define IONIC_DEF_TXRX_BURST\t\t32\n \n-#define IONIC_DEVCMD_TIMEOUT\t\t5\t/* devcmd_timeout */\n-#define IONIC_DEVCMD_CHECK_PERIOD_US\t10\t/* devcmd status chk period */\n-#define IONIC_DEVCMD_RETRY_WAIT_US\t20000\n-\n-#define IONIC_Q_WDOG_MS\t\t\t10\t/* 10ms */\n-#define IONIC_Q_WDOG_MAX_MS\t\t5000\t/* 5s */\n-#define IONIC_ADMINQ_WDOG_MS\t\t500\t/* 500ms */\n-\n-#define IONIC_ALIGN\t\t\t4096\n-\n struct ionic_adapter;\n \n-struct ionic_dev_bar {\n-\tvoid __iomem *vaddr;\n-\trte_iova_t bus_addr;\n-\tunsigned long len;\n-};\n-\n static inline void ionic_struct_size_checks(void)\n {\n \tRTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8);\n@@ -163,14 +147,6 @@ struct ionic_queue {\n \trte_iova_t cmb_base_pa;\n };\n \n-#define IONIC_INTR_NONE\t\t(-1)\n-\n-struct ionic_intr_info {\n-\tint index;\n-\tuint32_t vector;\n-\tstruct ionic_intr __iomem *ctrl;\n-};\n-\n struct ionic_cq {\n \tuint16_t tail_idx;\n \tuint16_t num_descs;\ndiff --git a/drivers/net/ionic/ionic_dev_pci.c b/drivers/net/ionic/ionic_dev_pci.c\nindex cbaac2c5bc..2d7b4f223e 100644\n--- a/drivers/net/ionic/ionic_dev_pci.c\n+++ b/drivers/net/ionic/ionic_dev_pci.c\n@@ -83,7 +83,7 @@ ionic_pci_setup(struct ionic_adapter *adapter)\n \n \t/* BAR1: doorbells */\n \tbar++;\n-\tif (num_bars < 2) {\n+\tif (num_bars < IONIC_BARS_MIN) {\n \t\tIONIC_PRINT(ERR, \"Doorbell bar missing, aborting\\n\");\n \t\treturn -EFAULT;\n \t}\ndiff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h\nindex 7ca604a7bb..e4ac79ac21 100644\n--- a/drivers/net/ionic/ionic_if.h\n+++ b/drivers/net/ionic/ionic_if.h\n@@ -2837,131 +2837,6 @@ union ionic_adminq_comp {\n \tstruct ionic_fw_control_comp fw_control;\n };\n \n-#define IONIC_BARS_MAX\t\t\t6\n-#define IONIC_PCI_BAR_DBELL\t\t1\n-\n-/* BAR0 */\n-#define IONIC_BAR0_SIZE\t\t\t\t0x8000\n-\n-#define IONIC_BAR0_DEV_INFO_REGS_OFFSET\t\t0x0000\n-#define IONIC_BAR0_DEV_CMD_REGS_OFFSET\t\t0x0800\n-#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET\t0x0c00\n-#define IONIC_BAR0_INTR_STATUS_OFFSET\t\t0x1000\n-#define IONIC_BAR0_INTR_CTRL_OFFSET\t\t0x2000\n-#define IONIC_DEV_CMD_DONE\t\t\t0x00000001\n-\n-#define IONIC_ASIC_TYPE_CAPRI\t\t\t0\n-\n-/**\n- * struct ionic_doorbell - Doorbell register layout\n- * @p_index: Producer index\n- * @ring: Selects the specific ring of the queue to update\n- * Type-specific meaning:\n- * ring=0: Default producer/consumer queue\n- * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs\n- * send events to EQs when armed. EQs send\n- * interrupts when armed.\n- * @qid_lo: Queue destination for the producer index and flags (low bits)\n- * @qid_hi: Queue destination for the producer index and flags (high bits)\n- */\n-struct ionic_doorbell {\n-\t__le16 p_index;\n-\tu8 ring;\n-\tu8 qid_lo;\n-\t__le16 qid_hi;\n-\tu16 rsvd2;\n-};\n-\n-/**\n- * struct ionic_intr_ctrl - Interrupt control register\n- * @coalescing_init: Coalescing timer initial value, in\n- * device units. Use @identity->intr_coal_mult\n- * and @identity->intr_coal_div to convert from\n- * usecs to device units:\n- *\n- * coal_init = coal_usecs * coal_mult / coal_div\n- *\n- * When an interrupt is sent the interrupt\n- * coalescing timer current value\n- * (@coalescing_curr) is initialized with this\n- * value and begins counting down. No more\n- * interrupts are sent until the coalescing\n- * timer reaches 0. When @coalescing_init=0\n- * interrupt coalescing is effectively disabled\n- * and every interrupt assert results in an\n- * interrupt. Reset value: 0\n- * @mask: Interrupt mask. When @mask=1 the interrupt\n- * resource will not send an interrupt. When\n- * @mask=0 the interrupt resource will send an\n- * interrupt if an interrupt event is pending\n- * or on the next interrupt assertion event.\n- * Reset value: 1\n- * @int_credits: Interrupt credits. This register indicates\n- * how many interrupt events the hardware has\n- * sent. When written by software this\n- * register atomically decrements @int_credits\n- * by the value written. When @int_credits\n- * becomes 0 then the \"pending interrupt\" bit\n- * in the Interrupt Status register is cleared\n- * by the hardware and any pending but unsent\n- * interrupts are cleared.\n- * !!!IMPORTANT!!! This is a signed register.\n- * @flags: Interrupt control flags\n- * @unmask -- When this bit is written with a 1\n- * the interrupt resource will set mask=0.\n- * @coal_timer_reset -- When this\n- * bit is written with a 1 the\n- * @coalescing_curr will be reloaded with\n- * @coalescing_init to reset the coalescing\n- * timer.\n- * @mask_on_assert: Automatically mask on assertion. When\n- * @mask_on_assert=1 the interrupt resource\n- * will set @mask=1 whenever an interrupt is\n- * sent. When using interrupts in Legacy\n- * Interrupt mode the driver must select\n- * @mask_on_assert=0 for proper interrupt\n- * operation.\n- * @coalescing_curr: Coalescing timer current value, in\n- * microseconds. When this value reaches 0\n- * the interrupt resource is again eligible to\n- * send an interrupt. If an interrupt event\n- * is already pending when @coalescing_curr\n- * reaches 0 the pending interrupt will be\n- * sent, otherwise an interrupt will be sent\n- * on the next interrupt assertion event.\n- */\n-struct ionic_intr_ctrl {\n-\tu8 coalescing_init;\n-\tu8 rsvd[3];\n-\tu8 mask;\n-\tu8 rsvd2[3];\n-\tu16 int_credits;\n-\tu16 flags;\n-#define INTR_F_UNMASK\t\t0x0001\n-#define INTR_F_TIMER_RESET\t0x0002\n-\tu8 mask_on_assert;\n-\tu8 rsvd3[3];\n-\tu8 coalescing_curr;\n-\tu8 rsvd4[3];\n-\tu32 rsvd6[3];\n-};\n-\n-#define IONIC_INTR_CTRL_REGS_MAX\t2048\n-#define IONIC_INTR_CTRL_COAL_MAX\t0x3F\n-\n-#define intr_to_coal(intr_ctrl)\t\t\\\n-\t\t((void __iomem *)&(intr_ctrl)->coalescing_init)\n-#define intr_to_mask(intr_ctrl)\t\t\\\n-\t\t((void __iomem *)&(intr_ctrl)->mask)\n-#define intr_to_credits(intr_ctrl)\t\\\n-\t\t((void __iomem *)&(intr_ctrl)->int_credits)\n-#define intr_to_mask_on_assert(intr_ctrl)\\\n-\t\t((void __iomem *)&(intr_ctrl)->mask_on_assert)\n-\n-struct ionic_intr_status {\n-\tu32 status[2];\n-};\n-\n struct ionic_notifyq_cmd {\n \t__le32 data;\t/* Not used but needed for qcq structure */\n };\ndiff --git a/drivers/net/ionic/ionic_rx_filter.h b/drivers/net/ionic/ionic_rx_filter.h\nindex 5500c7d70b..80dc5d806c 100644\n--- a/drivers/net/ionic/ionic_rx_filter.h\n+++ b/drivers/net/ionic/ionic_rx_filter.h\n@@ -7,7 +7,6 @@\n \n #include <rte_spinlock.h>\n \n-#include \"ionic_osdep.h\"\n #include \"ionic_if.h\"\n \n #define IONIC_RXQ_INDEX_ANY\t\t(0xFFFF)\ndiff --git a/drivers/net/ionic/ionic_rxtx_sg.c b/drivers/net/ionic/ionic_rxtx_sg.c\nindex 92e1d6e259..e8dec99c04 100644\n--- a/drivers/net/ionic/ionic_rxtx_sg.c\n+++ b/drivers/net/ionic/ionic_rxtx_sg.c\n@@ -16,8 +16,7 @@\n #include <rte_prefetch.h>\n \n #include \"ionic.h\"\n-#include \"ionic_if.h\"\n-#include \"ionic_dev.h\"\n+#include \"ionic_ethdev.h\"\n #include \"ionic_lif.h\"\n #include \"ionic_rxtx.h\"\n \ndiff --git a/drivers/net/ionic/ionic_rxtx_simple.c b/drivers/net/ionic/ionic_rxtx_simple.c\nindex f12f66f40c..9674b4d1df 100644\n--- a/drivers/net/ionic/ionic_rxtx_simple.c\n+++ b/drivers/net/ionic/ionic_rxtx_simple.c\n@@ -16,8 +16,7 @@\n #include <rte_prefetch.h>\n \n #include \"ionic.h\"\n-#include \"ionic_if.h\"\n-#include \"ionic_dev.h\"\n+#include \"ionic_ethdev.h\"\n #include \"ionic_lif.h\"\n #include \"ionic_rxtx.h\"\n \ndiff --git a/drivers/net/ionic/meson.build b/drivers/net/ionic/meson.build\nindex 71c7f2311a..9f735e353e 100644\n--- a/drivers/net/ionic/meson.build\n+++ b/drivers/net/ionic/meson.build\n@@ -7,6 +7,8 @@ if is_windows\n subdir_done()\n endif\n \n+deps += ['common_ionic']\n+\n sources = files(\n 'ionic_dev.c',\n 'ionic_dev_pci.c',\n@@ -19,3 +21,5 @@ sources = files(\n 'ionic_rxtx_simple.c',\n 'ionic_rxtx_sg.c',\n )\n+\n+includes += include_directories('../../common/ionic')\n", "prefixes": [ "1/3" ] }