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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2024 17:07:38.3596 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cbebf35-023e-47b4-8387-08dc2f11c75a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4457 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move definitions that will be shared by net/ionic and crypto/ionic. Add the code used for discovering UIO vdevs. Signed-off-by: Andrew Boyer --- MAINTAINERS | 1 + drivers/common/ionic/ionic_common.h | 41 +++ drivers/common/ionic/ionic_common_uio.c | 283 ++++++++++++++++++++ drivers/{net => common}/ionic/ionic_osdep.h | 37 ++- drivers/{net => common}/ionic/ionic_regs.h | 49 +++- drivers/common/ionic/meson.build | 12 + drivers/common/ionic/version.map | 9 + drivers/common/meson.build | 1 + drivers/net/ionic/ionic.h | 3 +- drivers/net/ionic/ionic_dev.h | 26 +- drivers/net/ionic/ionic_dev_pci.c | 2 +- drivers/net/ionic/ionic_if.h | 125 --------- drivers/net/ionic/ionic_rx_filter.h | 1 - drivers/net/ionic/ionic_rxtx_sg.c | 3 +- drivers/net/ionic/ionic_rxtx_simple.c | 3 +- drivers/net/ionic/meson.build | 4 + 16 files changed, 419 insertions(+), 181 deletions(-) create mode 100644 drivers/common/ionic/ionic_common.h create mode 100644 drivers/common/ionic/ionic_common_uio.c rename drivers/{net => common}/ionic/ionic_osdep.h (53%) rename drivers/{net => common}/ionic/ionic_regs.h (74%) create mode 100644 drivers/common/ionic/meson.build create mode 100644 drivers/common/ionic/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 5fb3a73f84..8a8199a82d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -654,6 +654,7 @@ F: doc/guides/nics/features/axgbe.ini AMD Pensando ionic M: Andrew Boyer +F: drivers/common/ionic/ F: drivers/net/ionic/ F: doc/guides/nics/ionic.rst F: doc/guides/nics/features/ionic.ini diff --git a/drivers/common/ionic/ionic_common.h b/drivers/common/ionic/ionic_common.h new file mode 100644 index 0000000000..eb4850e24c --- /dev/null +++ b/drivers/common/ionic/ionic_common.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018-2024 Advanced Micro Devices, Inc. + */ + +#ifndef _IONIC_COMMON_H_ +#define _IONIC_COMMON_H_ + +#include +#include + +#include +#include +#include + +#include "ionic_osdep.h" + +#define IONIC_DEVCMD_TIMEOUT 5 /* devcmd_timeout */ +#define IONIC_DEVCMD_CHECK_PERIOD_US 10 /* devcmd status chk period */ +#define IONIC_DEVCMD_RETRY_WAIT_US 20000 + +#define IONIC_Q_WDOG_MS 10 /* 10ms */ +#define IONIC_Q_WDOG_MAX_MS 5000 /* 5s */ +#define IONIC_ADMINQ_WDOG_MS 500 /* 500ms */ + +#define IONIC_ALIGN 4096 + +struct ionic_dev_bar { + void __iomem *vaddr; + rte_iova_t bus_addr; + unsigned long len; +}; + +__rte_internal +void ionic_uio_scan_mnet_devices(void); + +__rte_internal +void ionic_uio_get_rsrc(const char *name, int idx, struct ionic_dev_bar *bar); +__rte_internal +void ionic_uio_rel_rsrc(const char *name, int idx, struct ionic_dev_bar *bar); + +#endif /* _IONIC_COMMON_H_ */ diff --git a/drivers/common/ionic/ionic_common_uio.c b/drivers/common/ionic/ionic_common_uio.c new file mode 100644 index 0000000000..a12131301e --- /dev/null +++ b/drivers/common/ionic/ionic_common_uio.c @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018-2024 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ionic_common.h" + +#define IONIC_MDEV_UNK "mdev_unknown" +#define IONIC_MNIC "cpu_mnic" + +#define IONIC_MAX_NAME_LEN 20 +#define IONIC_MAX_MNETS 5 +#define IONIC_MAX_DEVICES (IONIC_MAX_MNETS) +#define IONIC_MAX_U16_IDX 0xFFFF +#define IONIC_UIO_MAX_TRIES 32 + +/* + * Note: the driver can assign any idx number + * in the range [0-IONIC_MAX_MDEV_SCAN) + */ +#define IONIC_MAX_MDEV_SCAN 32 + +struct ionic_map_tbl { + char dev_name[IONIC_MAX_NAME_LEN]; + uint16_t dev_idx; + uint16_t uio_idx; + char mdev_name[IONIC_MAX_NAME_LEN]; +}; + +struct ionic_map_tbl ionic_mdev_map[IONIC_MAX_DEVICES] = { + { "net_ionic0", 0, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, + { "net_ionic1", 1, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, + { "net_ionic2", 2, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, + { "net_ionic3", 3, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, + { "net_ionic4", 4, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK }, +}; + +struct uio_name { + uint16_t idx; + char name[IONIC_MAX_NAME_LEN]; +}; + +static void +uio_fill_name_cache(struct uio_name *name_cache, const char *pfx) +{ + char file[64]; + FILE *fp; + char *ret; + int name_idx = 0; + int i; + + for (i = 0; i < IONIC_UIO_MAX_TRIES && + name_idx < IONIC_MAX_DEVICES; i++) { + sprintf(file, "/sys/class/uio/uio%d/name", i); + + fp = fopen(file, "r"); + if (fp == NULL) + continue; + + ret = fgets(name_cache[name_idx].name, IONIC_MAX_NAME_LEN, fp); + if (ret == NULL) { + fclose(fp); + continue; + } + + name_cache[name_idx].idx = i; + + fclose(fp); + + if (strncmp(name_cache[name_idx].name, pfx, strlen(pfx)) == 0) + name_idx++; + } +} + +static int +uio_get_idx_for_devname(struct uio_name *name_cache, char *devname) +{ + int i; + + for (i = 0; i < IONIC_MAX_DEVICES; i++) + if (strncmp(name_cache[i].name, devname, strlen(devname)) == 0) + return name_cache[i].idx; + + return -1; +} + +void +ionic_uio_scan_mnet_devices(void) +{ + struct ionic_map_tbl *map; + char devname[IONIC_MAX_NAME_LEN]; + struct uio_name name_cache[IONIC_MAX_DEVICES]; + bool done; + int mdev_idx = 0; + int uio_idx; + int i; + + uio_fill_name_cache(name_cache, IONIC_MNIC); + + for (i = 0; i < IONIC_MAX_MNETS; i++) { + done = false; + + while (!done) { + if (mdev_idx > IONIC_MAX_MDEV_SCAN) + break; + + /* Look for a matching mnic */ + snprintf(devname, IONIC_MAX_NAME_LEN, + IONIC_MNIC "%d", mdev_idx); + uio_idx = uio_get_idx_for_devname(name_cache, devname); + if (uio_idx >= 0) { + map = &ionic_mdev_map[i]; + map->uio_idx = (uint16_t)uio_idx; + strlcpy(map->mdev_name, devname, + IONIC_MAX_NAME_LEN); + done = true; + } + + mdev_idx++; + } + } +} + +static int +uio_get_multi_dev_uionum(const char *name) +{ + struct ionic_map_tbl *map; + int i; + + for (i = 0; i < IONIC_MAX_DEVICES; i++) { + map = &ionic_mdev_map[i]; + if (strncmp(map->dev_name, name, IONIC_MAX_NAME_LEN) == 0) { + if (map->uio_idx == IONIC_MAX_U16_IDX) + return -1; + else + return map->uio_idx; + } + } + + return -1; +} + +static unsigned long +uio_get_res_size(int uio_idx, int res_idx) +{ + unsigned long size; + char file[64]; + FILE *fp; + + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", + uio_idx, res_idx); + + fp = fopen(file, "r"); + if (fp == NULL) + return 0; + + if (fscanf(fp, "0x%lx", &size) != 1) + size = 0; + + fclose(fp); + + return size; +} + +static unsigned long +uio_get_res_phy_addr_offs(int uio_idx, int res_idx) +{ + unsigned long offset; + char file[64]; + FILE *fp; + + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/offset", + uio_idx, res_idx); + + fp = fopen(file, "r"); + if (fp == NULL) + return 0; + + if (fscanf(fp, "0x%lx", &offset) != 1) + offset = 0; + + fclose(fp); + + return offset; +} + +static unsigned long +uio_get_res_phy_addr(int uio_idx, int res_idx) +{ + unsigned long addr; + char file[64]; + FILE *fp; + + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", + uio_idx, res_idx); + + fp = fopen(file, "r"); + if (fp == NULL) + return 0; + + if (fscanf(fp, "0x%lx", &addr) != 1) + addr = 0; + + fclose(fp); + + return addr; +} + +static void * +uio_get_map_res_addr(int uio_idx, int size, int res_idx) +{ + char name[64]; + int fd; + void *addr; + + if (size == 0) + return NULL; + + sprintf(name, "/dev/uio%d", uio_idx); + + fd = open(name, O_RDWR); + if (fd < 0) + return NULL; + + if (size < getpagesize()) + size = getpagesize(); + + addr = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, + fd, res_idx * getpagesize()); + + close(fd); + + return addr; +} + +void +ionic_uio_get_rsrc(const char *name, int idx, struct ionic_dev_bar *bar) +{ + int num; + int offs; + + num = uio_get_multi_dev_uionum(name); + if (num < 0) + return; + + bar->len = uio_get_res_size(num, idx); + offs = uio_get_res_phy_addr_offs(num, idx); + bar->bus_addr = uio_get_res_phy_addr(num, idx); + bar->bus_addr += offs; + bar->vaddr = uio_get_map_res_addr(num, bar->len, idx); + bar->vaddr = ((char *)bar->vaddr) + offs; +} + +void +ionic_uio_rel_rsrc(const char *name, int idx, struct ionic_dev_bar *bar) +{ + int num, offs; + + num = uio_get_multi_dev_uionum(name); + if (num < 0) + return; + if (bar->vaddr == NULL) + return; + + offs = uio_get_res_phy_addr_offs(num, idx); + munmap(((char *)bar->vaddr) - offs, bar->len); +} diff --git a/drivers/net/ionic/ionic_osdep.h b/drivers/common/ionic/ionic_osdep.h similarity index 53% rename from drivers/net/ionic/ionic_osdep.h rename to drivers/common/ionic/ionic_osdep.h index 68f767b920..029bc5f4fb 100644 --- a/drivers/net/ionic/ionic_osdep.h +++ b/drivers/common/ionic/ionic_osdep.h @@ -1,47 +1,40 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2018-2022 Advanced Micro Devices, Inc. + * Copyright 2018-2024 Advanced Micro Devices, Inc. */ #ifndef _IONIC_OSDEP_ #define _IONIC_OSDEP_ -#include #include -#include #include #include -#include -#include -#include -#include #include -#include -#include - -#include "ionic_logs.h" - -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) +#include -#ifndef PAGE_SHIFT -#define PAGE_SHIFT 12 -#endif +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) #define __iomem -typedef uint8_t u8; +typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; -typedef uint16_t __le16; -typedef uint32_t __le32; -typedef uint64_t __le64; +#ifndef __le16 +#define __le16 uint16_t +#endif +#ifndef __le32 +#define __le32 uint32_t +#endif +#ifndef __le64 +#define __le64 uint64_t +#endif #define ioread8(reg) rte_read8(reg) #define ioread32(reg) rte_read32(rte_le_to_cpu_32(reg)) #define iowrite8(value, reg) rte_write8(value, reg) #define iowrite32(value, reg) rte_write32(rte_cpu_to_le_32(value), reg) -#endif +#endif /* _IONIC_OSDEP_ */ diff --git a/drivers/net/ionic/ionic_regs.h b/drivers/common/ionic/ionic_regs.h similarity index 74% rename from drivers/net/ionic/ionic_regs.h rename to drivers/common/ionic/ionic_regs.h index b4c665a58d..bb97e9c6eb 100644 --- a/drivers/net/ionic/ionic_regs.h +++ b/drivers/common/ionic/ionic_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2018-2022 Advanced Micro Devices, Inc. + * Copyright 2018-2024 Advanced Micro Devices, Inc. */ #ifndef _IONIC_REGS_H_ @@ -46,6 +46,19 @@ enum ionic_intr_credits_bits { IONIC_INTR_CRED_RESET_COALESCE), }; +#define IONIC_INTR_NONE (-1) +#define IONIC_INTR_CTRL_REGS_MAX 2048 + +struct ionic_intr_info { + int index; + uint32_t vector; + struct ionic_intr __iomem *ctrl; +}; + +struct ionic_intr_status { + uint32_t status[2]; +}; + static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl, int intr_idx, uint32_t coal) @@ -65,7 +78,6 @@ ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl, int intr_idx, uint32_t cred, uint32_t flags) { if (cred > IONIC_INTR_CRED_COUNT) { - IONIC_WARN_ON(cred > IONIC_INTR_CRED_COUNT); cred = ioread32(&intr_ctrl[intr_idx].credits); cred &= IONIC_INTR_CRED_COUNT_SIGNED; } @@ -130,4 +142,37 @@ enum ionic_dbell_bits { IONIC_DBELL_INDEX_MASK = 0xffff, }; +#define IONIC_BARS_MIN 2 +#define IONIC_BARS_MAX 6 +#define IONIC_PCI_BAR_DBELL 1 + +/* BAR0 */ +#define IONIC_BAR0_SIZE 0x8000 + +#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 +#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 +#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 +#define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 +#define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 +#define IONIC_DEV_CMD_DONE 0x00000001 + +/** + * struct ionic_doorbell - Doorbell register layout + * @p_index: Producer index + * @ring: Selects the specific ring of the queue to update + * Type-specific meaning: + * ring=0: Default producer/consumer queue + * ring=1: (CQ, EQ) Re-Arm queue. CQs send events to EQs + * when armed. EQs send interrupts when armed. + * @qid_lo: Queue destination for the producer index and flags (low bits) + * @qid_hi: Queue destination for the producer index and flags (high bits) + */ +struct ionic_doorbell { + __le16 p_index; + u8 ring; + u8 qid_lo; + __le16 qid_hi; + u16 rsvd2; +}; + #endif /* _IONIC_REGS_H_ */ diff --git a/drivers/common/ionic/meson.build b/drivers/common/ionic/meson.build new file mode 100644 index 0000000000..51f6f3c7bd --- /dev/null +++ b/drivers/common/ionic/meson.build @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018-2022 Advanced Micro Devices, Inc. + +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + +sources = files( + 'ionic_common_uio.c', +) diff --git a/drivers/common/ionic/version.map b/drivers/common/ionic/version.map new file mode 100644 index 0000000000..484330c437 --- /dev/null +++ b/drivers/common/ionic/version.map @@ -0,0 +1,9 @@ +INTERNAL { + global: + + ionic_uio_scan_mnet_devices; + ionic_uio_get_rsrc; + ionic_uio_rel_rsrc; + + local: *; +}; diff --git a/drivers/common/meson.build b/drivers/common/meson.build index b63d899d50..8734af36aa 100644 --- a/drivers/common/meson.build +++ b/drivers/common/meson.build @@ -7,6 +7,7 @@ drivers = [ 'dpaax', 'iavf', 'idpf', + 'ionic', 'mvep', 'octeontx', ] diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h index cb4ea450a9..a4a2e2756d 100644 --- a/drivers/net/ionic/ionic.h +++ b/drivers/net/ionic/ionic.h @@ -8,9 +8,10 @@ #include #include +#include "ionic_common.h" #include "ionic_dev.h" #include "ionic_if.h" -#include "ionic_osdep.h" +#include "ionic_logs.h" #define IONIC_DRV_NAME "ionic" #define IONIC_DRV_DESCRIPTION "AMD Pensando Ethernet NIC Driver" diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 3a366247f1..b8eebcd181 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -7,7 +7,7 @@ #include -#include "ionic_osdep.h" +#include "ionic_common.h" #include "ionic_if.h" #include "ionic_regs.h" @@ -22,24 +22,8 @@ #define IONIC_DEF_TXRX_DESC 4096 #define IONIC_DEF_TXRX_BURST 32 -#define IONIC_DEVCMD_TIMEOUT 5 /* devcmd_timeout */ -#define IONIC_DEVCMD_CHECK_PERIOD_US 10 /* devcmd status chk period */ -#define IONIC_DEVCMD_RETRY_WAIT_US 20000 - -#define IONIC_Q_WDOG_MS 10 /* 10ms */ -#define IONIC_Q_WDOG_MAX_MS 5000 /* 5s */ -#define IONIC_ADMINQ_WDOG_MS 500 /* 500ms */ - -#define IONIC_ALIGN 4096 - struct ionic_adapter; -struct ionic_dev_bar { - void __iomem *vaddr; - rte_iova_t bus_addr; - unsigned long len; -}; - static inline void ionic_struct_size_checks(void) { RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8); @@ -163,14 +147,6 @@ struct ionic_queue { rte_iova_t cmb_base_pa; }; -#define IONIC_INTR_NONE (-1) - -struct ionic_intr_info { - int index; - uint32_t vector; - struct ionic_intr __iomem *ctrl; -}; - struct ionic_cq { uint16_t tail_idx; uint16_t num_descs; diff --git a/drivers/net/ionic/ionic_dev_pci.c b/drivers/net/ionic/ionic_dev_pci.c index cbaac2c5bc..2d7b4f223e 100644 --- a/drivers/net/ionic/ionic_dev_pci.c +++ b/drivers/net/ionic/ionic_dev_pci.c @@ -83,7 +83,7 @@ ionic_pci_setup(struct ionic_adapter *adapter) /* BAR1: doorbells */ bar++; - if (num_bars < 2) { + if (num_bars < IONIC_BARS_MIN) { IONIC_PRINT(ERR, "Doorbell bar missing, aborting\n"); return -EFAULT; } diff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h index 7ca604a7bb..e4ac79ac21 100644 --- a/drivers/net/ionic/ionic_if.h +++ b/drivers/net/ionic/ionic_if.h @@ -2837,131 +2837,6 @@ union ionic_adminq_comp { struct ionic_fw_control_comp fw_control; }; -#define IONIC_BARS_MAX 6 -#define IONIC_PCI_BAR_DBELL 1 - -/* BAR0 */ -#define IONIC_BAR0_SIZE 0x8000 - -#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 -#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 -#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 -#define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 -#define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 -#define IONIC_DEV_CMD_DONE 0x00000001 - -#define IONIC_ASIC_TYPE_CAPRI 0 - -/** - * struct ionic_doorbell - Doorbell register layout - * @p_index: Producer index - * @ring: Selects the specific ring of the queue to update - * Type-specific meaning: - * ring=0: Default producer/consumer queue - * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs - * send events to EQs when armed. EQs send - * interrupts when armed. - * @qid_lo: Queue destination for the producer index and flags (low bits) - * @qid_hi: Queue destination for the producer index and flags (high bits) - */ -struct ionic_doorbell { - __le16 p_index; - u8 ring; - u8 qid_lo; - __le16 qid_hi; - u16 rsvd2; -}; - -/** - * struct ionic_intr_ctrl - Interrupt control register - * @coalescing_init: Coalescing timer initial value, in - * device units. Use @identity->intr_coal_mult - * and @identity->intr_coal_div to convert from - * usecs to device units: - * - * coal_init = coal_usecs * coal_mult / coal_div - * - * When an interrupt is sent the interrupt - * coalescing timer current value - * (@coalescing_curr) is initialized with this - * value and begins counting down. No more - * interrupts are sent until the coalescing - * timer reaches 0. When @coalescing_init=0 - * interrupt coalescing is effectively disabled - * and every interrupt assert results in an - * interrupt. Reset value: 0 - * @mask: Interrupt mask. When @mask=1 the interrupt - * resource will not send an interrupt. When - * @mask=0 the interrupt resource will send an - * interrupt if an interrupt event is pending - * or on the next interrupt assertion event. - * Reset value: 1 - * @int_credits: Interrupt credits. This register indicates - * how many interrupt events the hardware has - * sent. When written by software this - * register atomically decrements @int_credits - * by the value written. When @int_credits - * becomes 0 then the "pending interrupt" bit - * in the Interrupt Status register is cleared - * by the hardware and any pending but unsent - * interrupts are cleared. - * !!!IMPORTANT!!! This is a signed register. - * @flags: Interrupt control flags - * @unmask -- When this bit is written with a 1 - * the interrupt resource will set mask=0. - * @coal_timer_reset -- When this - * bit is written with a 1 the - * @coalescing_curr will be reloaded with - * @coalescing_init to reset the coalescing - * timer. - * @mask_on_assert: Automatically mask on assertion. When - * @mask_on_assert=1 the interrupt resource - * will set @mask=1 whenever an interrupt is - * sent. When using interrupts in Legacy - * Interrupt mode the driver must select - * @mask_on_assert=0 for proper interrupt - * operation. - * @coalescing_curr: Coalescing timer current value, in - * microseconds. When this value reaches 0 - * the interrupt resource is again eligible to - * send an interrupt. If an interrupt event - * is already pending when @coalescing_curr - * reaches 0 the pending interrupt will be - * sent, otherwise an interrupt will be sent - * on the next interrupt assertion event. - */ -struct ionic_intr_ctrl { - u8 coalescing_init; - u8 rsvd[3]; - u8 mask; - u8 rsvd2[3]; - u16 int_credits; - u16 flags; -#define INTR_F_UNMASK 0x0001 -#define INTR_F_TIMER_RESET 0x0002 - u8 mask_on_assert; - u8 rsvd3[3]; - u8 coalescing_curr; - u8 rsvd4[3]; - u32 rsvd6[3]; -}; - -#define IONIC_INTR_CTRL_REGS_MAX 2048 -#define IONIC_INTR_CTRL_COAL_MAX 0x3F - -#define intr_to_coal(intr_ctrl) \ - ((void __iomem *)&(intr_ctrl)->coalescing_init) -#define intr_to_mask(intr_ctrl) \ - ((void __iomem *)&(intr_ctrl)->mask) -#define intr_to_credits(intr_ctrl) \ - ((void __iomem *)&(intr_ctrl)->int_credits) -#define intr_to_mask_on_assert(intr_ctrl)\ - ((void __iomem *)&(intr_ctrl)->mask_on_assert) - -struct ionic_intr_status { - u32 status[2]; -}; - struct ionic_notifyq_cmd { __le32 data; /* Not used but needed for qcq structure */ }; diff --git a/drivers/net/ionic/ionic_rx_filter.h b/drivers/net/ionic/ionic_rx_filter.h index 5500c7d70b..80dc5d806c 100644 --- a/drivers/net/ionic/ionic_rx_filter.h +++ b/drivers/net/ionic/ionic_rx_filter.h @@ -7,7 +7,6 @@ #include -#include "ionic_osdep.h" #include "ionic_if.h" #define IONIC_RXQ_INDEX_ANY (0xFFFF) diff --git a/drivers/net/ionic/ionic_rxtx_sg.c b/drivers/net/ionic/ionic_rxtx_sg.c index 92e1d6e259..e8dec99c04 100644 --- a/drivers/net/ionic/ionic_rxtx_sg.c +++ b/drivers/net/ionic/ionic_rxtx_sg.c @@ -16,8 +16,7 @@ #include #include "ionic.h" -#include "ionic_if.h" -#include "ionic_dev.h" +#include "ionic_ethdev.h" #include "ionic_lif.h" #include "ionic_rxtx.h" diff --git a/drivers/net/ionic/ionic_rxtx_simple.c b/drivers/net/ionic/ionic_rxtx_simple.c index f12f66f40c..9674b4d1df 100644 --- a/drivers/net/ionic/ionic_rxtx_simple.c +++ b/drivers/net/ionic/ionic_rxtx_simple.c @@ -16,8 +16,7 @@ #include #include "ionic.h" -#include "ionic_if.h" -#include "ionic_dev.h" +#include "ionic_ethdev.h" #include "ionic_lif.h" #include "ionic_rxtx.h" diff --git a/drivers/net/ionic/meson.build b/drivers/net/ionic/meson.build index 71c7f2311a..9f735e353e 100644 --- a/drivers/net/ionic/meson.build +++ b/drivers/net/ionic/meson.build @@ -7,6 +7,8 @@ if is_windows subdir_done() endif +deps += ['common_ionic'] + sources = files( 'ionic_dev.c', 'ionic_dev_pci.c', @@ -19,3 +21,5 @@ sources = files( 'ionic_rxtx_simple.c', 'ionic_rxtx_sg.c', ) + +includes += include_directories('../../common/ionic')