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GET /api/patches/133477/?format=api
{ "id": 133477, "url": "http://patches.dpdk.org/api/patches/133477/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231027060947.3183983-8-haijie1@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231027060947.3183983-8-haijie1@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231027060947.3183983-8-haijie1@huawei.com", "date": "2023-10-27T06:09:45", "name": "[7/8] net/hns3: fix the imp/global reset interrupted possibly", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1de8ff2c1badb3a6512a306dd845698418b26112", "submitter": { "id": 2935, "url": "http://patches.dpdk.org/api/people/2935/?format=api", "name": "Jie Hai", "email": "haijie1@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231027060947.3183983-8-haijie1@huawei.com/mbox/", "series": [ { "id": 30018, "url": "http://patches.dpdk.org/api/series/30018/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30018", "date": "2023-10-27T06:09:41", "name": "net/hns3: add some bugfix for hns3", "version": 1, "mbox": "http://patches.dpdk.org/series/30018/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133477/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/133477/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7D17643212;\n\tFri, 27 Oct 2023 08:14:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A144242DB2;\n\tFri, 27 Oct 2023 08:14:01 +0200 (CEST)", "from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188])\n by mails.dpdk.org (Postfix) with ESMTP id D23C64064A\n for <dev@dpdk.org>; Fri, 27 Oct 2023 08:13:53 +0200 (CEST)", "from kwepemi500020.china.huawei.com (unknown [172.30.72.57])\n by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshD69mqzPnjK\n for <dev@dpdk.org>; Fri, 27 Oct 2023 14:09:48 +0800 (CST)", "from localhost.localdomain (10.67.165.2) by\n kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2507.31; Fri, 27 Oct 2023 14:13:51 +0800" ], "From": "Jie Hai <haijie1@huawei.com>", "To": "<dev@dpdk.org>, Yisen Zhuang <yisen.zhuang@huawei.com>, \"Min Hu (Connor)\"\n <humin29@huawei.com>, Ferruh Yigit <ferruh.yigit@intel.com>, Huisong Li\n <lihuisong@huawei.com>, Chunsong Feng <fengchunsong@huawei.com>, \"Wei Hu\n (Xavier)\" <xavier.huwei@huawei.com>", "CC": "<fengchengwen@huawei.com>, <liudongdong3@huawei.com>,\n <huangdengdui@huawei.com>", "Subject": "[PATCH 7/8] net/hns3: fix the imp/global reset interrupted possibly", "Date": "Fri, 27 Oct 2023 14:09:45 +0800", "Message-ID": "<20231027060947.3183983-8-haijie1@huawei.com>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20231027060947.3183983-1-haijie1@huawei.com>", "References": "<20231027060947.3183983-1-haijie1@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.2]", "X-ClientProxiedBy": "dggems703-chm.china.huawei.com (10.3.19.180) To\n kwepemi500020.china.huawei.com (7.221.188.8)", "X-CFilter-Loop": "Reflected", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dengdui Huang <huangdengdui@huawei.com>\n\nCurrently, when the IMP or Global reset detected, the vector0\ninterrupt is enabled before the reset process is completed.\nAt this moment, if the initialization of IMP is not completed,\nand the vector0 interrupt may continue to be reported. In this\nscenario, the IMP/global reset being performed by the driver\ndoes not need to be interrupted. Therefore, for IMP and global\nresets, the driver has to enable the interrupt after the end\nof reset.\n\nThe RAS interrupt is also shared with the vector0 interrupt.\nWhen the interrupt is disabled, the RAS interrupt can still be\nreported to the driver and the driver interrupt processing\nfunction is also called. In this case, the interrupt status of\nthe IMP/global may still exist. Therefore, this patch also has\nto the check of the new reset level based on the priority of\nreset level in the interrupt hnader.\n\nFixes: 2790c6464725 (\"net/hns3: support device reset\")\nFixes: 3988ab0eee52 (\"net/hns3: add abnormal interrupt process\")\nCc: stable@dpdk.org\n\nSigned-off-by: Dengdui Huang <huangdengdui@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev.c | 88 ++++++++++++++++++++++++++++------\n drivers/net/hns3/hns3_ethdev.h | 1 +\n drivers/net/hns3/hns3_intr.c | 2 +\n 3 files changed, 77 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 18afc0fa0a12..bb9dde9c5bc3 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -215,6 +215,30 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \treturn ret;\n }\n \n+void\n+hns3_clear_reset_event(struct hns3_hw *hw)\n+{\n+\tuint32_t clearval = 0;\n+\n+\tswitch (hw->reset.level) {\n+\tcase HNS3_IMP_RESET:\n+\t\tclearval = BIT(HNS3_VECTOR0_IMPRESET_INT_B);\n+\t\tbreak;\n+\tcase HNS3_GLOBAL_RESET:\n+\t\tclearval = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (clearval == 0)\n+\t\treturn;\n+\n+\thns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, clearval);\n+\n+\thns3_pf_enable_irq0(hw);\n+}\n+\n static void\n hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)\n {\n@@ -287,6 +311,34 @@ hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uin\n \t}\n }\n \n+static bool\n+hns3_reset_event_valid(struct hns3_hw *hw)\n+{\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\tenum hns3_reset_level new_req = HNS3_NONE_RESET;\n+\tenum hns3_reset_level last_req;\n+\tuint32_t vector0_int;\n+\n+\tvector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n+\tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int)\n+\t\tnew_req = HNS3_IMP_RESET;\n+\telse if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int)\n+\t\tnew_req = HNS3_GLOBAL_RESET;\n+\tif (new_req == HNS3_NONE_RESET)\n+\t\treturn true;\n+\n+\tlast_req = hns3_get_reset_level(hns, &hw->reset.pending);\n+\tif (last_req == HNS3_NONE_RESET)\n+\t\treturn true;\n+\n+\tif (new_req > last_req)\n+\t\treturn true;\n+\n+\thns3_warn(hw, \"last_req (%u) less than or equal to new_req (%u) ignore\",\n+\t\t last_req, new_req);\n+\treturn false;\n+}\n+\n static void\n hns3_interrupt_handler(void *param)\n {\n@@ -299,6 +351,9 @@ hns3_interrupt_handler(void *param)\n \tuint32_t ras_int;\n \tuint32_t cmdq_int;\n \n+\tif (!hns3_reset_event_valid(hw))\n+\t\treturn;\n+\n \t/* Disable interrupt */\n \thns3_pf_disable_irq0(hw);\n \n@@ -327,7 +382,11 @@ hns3_interrupt_handler(void *param)\n \t}\n \n \t/* Enable interrupt if it is not cause by reset */\n-\thns3_pf_enable_irq0(hw);\n+\tif (event_cause == HNS3_VECTOR0_EVENT_ERR ||\n+\t event_cause == HNS3_VECTOR0_EVENT_MBX ||\n+\t event_cause == HNS3_VECTOR0_EVENT_PTP ||\n+\t event_cause == HNS3_VECTOR0_EVENT_OTHER)\n+\t\thns3_pf_enable_irq0(hw);\n }\n \n static int\n@@ -5489,7 +5548,7 @@ is_pf_reset_done(struct hns3_hw *hw)\n \t\treturn true;\n }\n \n-static void\n+static enum hns3_reset_level\n hns3_detect_reset_event(struct hns3_hw *hw)\n {\n \tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n@@ -5501,11 +5560,9 @@ hns3_detect_reset_event(struct hns3_hw *hw)\n \tvector0_intr_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n \tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_intr_state) {\n \t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n-\t\thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t\tnew_req = HNS3_IMP_RESET;\n \t} else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_intr_state) {\n \t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n-\t\thns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);\n \t\tnew_req = HNS3_GLOBAL_RESET;\n \t}\n \n@@ -5513,13 +5570,16 @@ hns3_detect_reset_event(struct hns3_hw *hw)\n \t\thns3_schedule_delayed_reset(hns);\n \t\thns3_warn(hw, \"High level reset detected, delay do reset\");\n \t}\n+\n+\treturn new_req;\n }\n \n bool\n hns3_is_reset_pending(struct hns3_adapter *hns)\n {\n+\tenum hns3_reset_level new_req;\n \tstruct hns3_hw *hw = &hns->hw;\n-\tenum hns3_reset_level reset;\n+\tenum hns3_reset_level last_req;\n \n \t/*\n \t * Only primary can process can process the reset event,\n@@ -5528,17 +5588,17 @@ hns3_is_reset_pending(struct hns3_adapter *hns)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn false;\n \n-\thns3_detect_reset_event(hw);\n-\treset = hns3_get_reset_level(hns, &hw->reset.pending);\n-\tif (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&\n-\t hw->reset.level < reset) {\n-\t\thns3_warn(hw, \"High level reset %d is pending\", reset);\n+\tnew_req = hns3_detect_reset_event(hw);\n+\tlast_req = hns3_get_reset_level(hns, &hw->reset.pending);\n+\tif (last_req != HNS3_NONE_RESET && new_req != HNS3_NONE_RESET &&\n+\t new_req < last_req) {\n+\t\thns3_warn(hw, \"High level reset %d is pending\", last_req);\n \t\treturn true;\n \t}\n-\treset = hns3_get_reset_level(hns, &hw->reset.request);\n-\tif (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&\n-\t hw->reset.level < reset) {\n-\t\thns3_warn(hw, \"High level reset %d is request\", reset);\n+\tlast_req = hns3_get_reset_level(hns, &hw->reset.request);\n+\tif (last_req != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&\n+\t hw->reset.level < last_req) {\n+\t\thns3_warn(hw, \"High level reset %d is request\", last_req);\n \t\treturn true;\n \t}\n \treturn false;\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex c85a6912ada4..0e8d043704e3 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -1033,6 +1033,7 @@ void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);\n void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,\n \t\t\t uint32_t link_speed, uint8_t link_duplex);\n void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);\n+void hns3_clear_reset_event(struct hns3_hw *hw);\n \n const char *hns3_get_media_type_name(uint8_t media_type);\n \ndiff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nindex baf5f58e9e2b..c5a3e3797cbd 100644\n--- a/drivers/net/hns3/hns3_intr.c\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -2749,6 +2749,7 @@ hns3_reset_post(struct hns3_adapter *hns)\n \t\t/* IMP will wait ready flag before reset */\n \t\thns3_notify_reset_ready(hw, false);\n \t\thns3_clear_reset_level(hw, &hw->reset.pending);\n+\t\thns3_clear_reset_event(hw);\n \t\t__atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);\n \t\thw->reset.attempts = 0;\n \t\thw->reset.stats.success_cnt++;\n@@ -2798,6 +2799,7 @@ hns3_reset_fail_handle(struct hns3_adapter *hns)\n \tstruct timeval tv;\n \n \thns3_clear_reset_level(hw, &hw->reset.pending);\n+\thns3_clear_reset_event(hw);\n \tif (hns3_reset_err_handle(hns)) {\n \t\thw->reset.stage = RESET_STAGE_PREWAIT;\n \t\thns3_schedule_reset(hns);\n", "prefixes": [ "7/8" ] }