From patchwork Fri Oct 27 06:09:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133474 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8842F43212; Fri, 27 Oct 2023 08:14:20 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 350D540EE2; Fri, 27 Oct 2023 08:13:58 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 225C74029A for ; Fri, 27 Oct 2023 08:13:53 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshL6m6szVm02 for ; Fri, 27 Oct 2023 14:09:54 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:48 +0800 From: Jie Hai To: , Yisen Zhuang , Lijun Ou , Chengwen Feng CC: , , Subject: [PATCH 1/8] net/hns3: fix a typo Date: Fri, 27 Oct 2023 14:09:39 +0800 Message-ID: <20231027060947.3183983-2-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch fixes a typo. Fixes: c09c7847d892 ("net/hns3: support traffic management") Cc: stable@dpdk.org Signed-off-by: Jie Hai Acked-by: Huisong Li Acked-by: Chengwen Feng --- drivers/net/hns3/hns3_tm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_tm.c b/drivers/net/hns3/hns3_tm.c index 67402a700f46..d9691640140b 100644 --- a/drivers/net/hns3/hns3_tm.c +++ b/drivers/net/hns3/hns3_tm.c @@ -739,7 +739,7 @@ hns3_tm_node_type_get(struct rte_eth_dev *dev, uint32_t node_id, } static void -hns3_tm_nonleaf_level_capsbilities_get(struct rte_eth_dev *dev, +hns3_tm_nonleaf_level_capabilities_get(struct rte_eth_dev *dev, uint32_t level_id, struct rte_tm_level_capabilities *cap) { @@ -818,7 +818,7 @@ hns3_tm_level_capabilities_get(struct rte_eth_dev *dev, memset(cap, 0, sizeof(struct rte_tm_level_capabilities)); if (level_id != HNS3_TM_NODE_LEVEL_QUEUE) - hns3_tm_nonleaf_level_capsbilities_get(dev, level_id, cap); + hns3_tm_nonleaf_level_capabilities_get(dev, level_id, cap); else hns3_tm_leaf_level_capabilities_get(dev, cap); From patchwork Fri Oct 27 06:09:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133472 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A3D8543212; Fri, 27 Oct 2023 08:13:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A186B40A6C; Fri, 27 Oct 2023 08:13:54 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 8303C4029A for ; Fri, 27 Oct 2023 08:13:51 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SGsjV12bBzrTXj; Fri, 27 Oct 2023 14:10:54 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:48 +0800 From: Jie Hai To: , Yisen Zhuang , "Wei Hu (Xavier)" , Hao Chen , Chunsong Feng , Ferruh Yigit , "Min Hu (Connor)" CC: , , , Subject: [PATCH 2/8] net/hns3: fix unchecked Rx free threshold Date: Fri, 27 Oct 2023 14:09:40 +0800 Message-ID: <20231027060947.3183983-3-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang To reduce the frequency of updating the head pointer of Rx queue, driver just updates this pointer when the number of processed descriptors is greater than the Rx free threshold. If the Rx free threshold is set to a value greater than or equal to the number of descriptors in Rx queue, the driver does not update this pointer. As a result, the hardware cannot receive more packets. This patch fix it by adding Rx free threshold check. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_rxtx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index f3c3b38c55d1..13214d02d536 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -1785,6 +1785,12 @@ hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf, return -EINVAL; } + if (conf->rx_free_thresh >= nb_desc) { + hns3_err(hw, "rx_free_thresh (%u) must be less than %u", + conf->rx_free_thresh, nb_desc); + return -EINVAL; + } + if (conf->rx_drop_en == 0) hns3_warn(hw, "if no descriptors available, packets are always " "dropped and rx_drop_en (1) is fixed on"); From patchwork Fri Oct 27 06:09:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133471 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC0E243212; Fri, 27 Oct 2023 08:13:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7C94C402D4; Fri, 27 Oct 2023 08:13:53 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 7D8D140272 for ; Fri, 27 Oct 2023 08:13:51 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SGsgC4w4dzpWZF for ; Fri, 27 Oct 2023 14:08:55 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:49 +0800 From: Jie Hai To: , Yisen Zhuang , "Wei Hu (Xavier)" , Huisong Li , Chengwen Feng , Dongdong Liu CC: Subject: [PATCH 3/8] net/hns3: fix segmentfault for NEON and SVE Date: Fri, 27 Oct 2023 14:09:41 +0800 Message-ID: <20231027060947.3183983-4-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li Driver may fail to allocate bulk mbufs for Neon and SVE when rearm mbuf. Currently, driver keeps going to handle packets even if there isn't available descriptors to receive packets at this moment. As a result, driver probably fills the mbufs with invalid data to application and accesses to illegal address because of the VLD bit of the descriptor at the "rx_rearm_start" position still being set. So driver has to clear VLD bit for this descriptor in this scenario in case of receiving packets later. In addition, it is possible that the sum of the "rx_rearm_nb" and "rx_rearm_start" is greater than total descriptor number of Rx queue in the above scenario. So the index of rxq->sw_ring[] to set mbuf pointer to NULL should also be fixed to avoid out-of-bounds memory access. Fixes: a3d4f4d291d7 ("net/hns3: support NEON Rx") Fixes: f81a18f49152 ("net/hns3: fix mbuf leakage when RxQ started after reset") Cc: stable@dpdk.org Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_rxtx.c | 2 +- drivers/net/hns3/hns3_rxtx_vec.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 13214d02d536..f28ca040be41 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -51,7 +51,7 @@ hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq) } } for (i = 0; i < rxq->rx_rearm_nb; i++) - rxq->sw_ring[rxq->rx_rearm_start + i].mbuf = NULL; + rxq->sw_ring[(rxq->rx_rearm_start + i) % rxq->nb_rx_desc].mbuf = NULL; } for (i = 0; i < rxq->bulk_mbuf_num; i++) diff --git a/drivers/net/hns3/hns3_rxtx_vec.h b/drivers/net/hns3/hns3_rxtx_vec.h index a9a6774294ef..9018e79c2f92 100644 --- a/drivers/net/hns3/hns3_rxtx_vec.h +++ b/drivers/net/hns3/hns3_rxtx_vec.h @@ -106,6 +106,11 @@ hns3_rxq_rearm_mbuf(struct hns3_rx_queue *rxq) if (unlikely(rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep, HNS3_DEFAULT_RXQ_REARM_THRESH) < 0)) { + /* + * Clear VLD bit for the first descriptor rearmed in case + * of going to receive packets later. + */ + rxdp[0].rx.bd_base_info = 0; rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++; return; } From patchwork Fri Oct 27 06:09:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133473 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D69743212; Fri, 27 Oct 2023 08:14:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D869A40A72; Fri, 27 Oct 2023 08:13:55 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id AF67D402AA for ; Fri, 27 Oct 2023 08:13:51 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SGsjW3GL9zrSn8; Fri, 27 Oct 2023 14:10:55 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:50 +0800 From: Jie Hai To: , Yisen Zhuang , Chunsong Feng , Hao Chen , Huisong Li , Ferruh Yigit , "Min Hu (Connor)" CC: , , Subject: [PATCH 4/8] net/hns3: fix double stats for IMP and global reset Date: Fri, 27 Oct 2023 14:09:42 +0800 Message-ID: <20231027060947.3183983-5-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang There is a stats counter for IMP and global reset in PF driver. hns3 driver has two following task to detect reset event: (1) interrupte handled task(A): triggered by interrupt and detect which reset level. And the reset service will be executed after 10us. (2) polling task(B): scan reset source register to detect if driver has to do reset. And the reset service will be executed after deferred 3s. They'll both count the number of one reset plus 1. Task(A) adds it before doing the reset service. And in the reset service, task(B) adds it if hw->reset.schedule is 'SCHEDULE_REQUESTED'. Normally, this reset counter is just added by 1 once. Unfortunately, this counter is added by 2 in the following case: 1. Task(B) detect the reset event, like IMP. hw->reset.schedule is set to 'SCHEDULE_REQUESTED'. 2. Task(A) is just triggered before running the reset service of task(B). Note: the reset counter is added by 1 at this moment before running the reset service of task(A). Additionally, the reset service of task(B) is canceled in task(A) because of schedule status being 'SCHEDULE_REQUESTED'. 3. Then the reset service of task(A) is executed at last. Note: The reset counter is added by 1 again in this step because of schedule status still being 'SCHEDULE_REQUESTED'. So this patch fix it by setting the scheduling status to 'SCHEDULE_REQUESTED' in step 2. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_intr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 44a11194155a..baf5f58e9e2b 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -2434,8 +2434,8 @@ hns3_schedule_reset(struct hns3_adapter *hns) if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == SCHEDULE_DEFERRED) rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns); - else - __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, + + __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, __ATOMIC_RELAXED); rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns); From patchwork Fri Oct 27 06:09:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133475 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7A5E43212; Fri, 27 Oct 2023 08:14:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F41B42670; Fri, 27 Oct 2023 08:13:59 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id BB0664029A for ; Fri, 27 Oct 2023 08:13:52 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshC47LJzPngv for ; Fri, 27 Oct 2023 14:09:47 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:50 +0800 From: Jie Hai To: , Yisen Zhuang , Anatoly Burakov , Chengwen Feng , Dongdong Liu CC: , Subject: [PATCH 5/8] net/hns3: remove reset log in secondary Date: Fri, 27 Oct 2023 14:09:43 +0800 Message-ID: <20231027060947.3183983-6-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang The reset event is checked and done in primary. And the secondary doesn't check and display reset log. There is a patch to remove the check code for secondary. please see commit a8f1f7cf1b42 ("net/hns3: fix crash when secondary process access FW") This patch removes the redundant log print of reset. Fixes: a8f1f7cf1b42 ("net/hns3: fix crash when secondary process access FW") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 11 +++++------ drivers/net/hns3/hns3_ethdev_vf.c | 11 +++++------ 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 964f47f1641e..3bdce1fa4b48 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5512,14 +5512,13 @@ hns3_is_reset_pending(struct hns3_adapter *hns) enum hns3_reset_level reset; /* - * Check the registers to confirm whether there is reset pending. - * Note: This check may lead to schedule reset task, but only primary - * process can process the reset event. Therefore, limit the - * checking under only primary process. + * Only primary can process can process the reset event, + * so don't check reset event in secondary. */ - if (rte_eal_process_type() == RTE_PROC_PRIMARY) - hns3_check_event_cause(hns, NULL); + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return false; + hns3_check_event_cause(hns, NULL); reset = hns3_get_reset_level(hns, &hw->reset.pending); if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 007f5d619fbf..5f3422d14e8a 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1715,14 +1715,13 @@ hns3vf_is_reset_pending(struct hns3_adapter *hns) return false; /* - * Check the registers to confirm whether there is reset pending. - * Note: This check may lead to schedule reset task, but only primary - * process can process the reset event. Therefore, limit the - * checking under only primary process. + * Only primary can process can process the reset event, + * so don't check reset event in secondary. */ - if (rte_eal_process_type() == RTE_PROC_PRIMARY) - hns3vf_check_event_cause(hns, NULL); + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return false; + hns3vf_check_event_cause(hns, NULL); reset = hns3vf_get_reset_level(hw, &hw->reset.pending); if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET && hw->reset.level < reset) { From patchwork Fri Oct 27 06:09:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133476 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5CEE43212; Fri, 27 Oct 2023 08:14:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7ED1B427DF; Fri, 27 Oct 2023 08:14:00 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id CD6DB40649 for ; Fri, 27 Oct 2023 08:13:52 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshQ0tGJzVlys for ; Fri, 27 Oct 2023 14:09:58 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:51 +0800 From: Jie Hai To: , Yisen Zhuang , Chunsong Feng , "Wei Hu (Xavier)" , "Min Hu (Connor)" , Ferruh Yigit , Huisong Li CC: , , Subject: [PATCH 6/8] net/hns3: fix multiple reset detected log Date: Fri, 27 Oct 2023 14:09:44 +0800 Message-ID: <20231027060947.3183983-7-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang Currently, the driver proactively checks whether interrupt exist (by checking reset registers), related reset delay task is scheduled. When a reset whose level is equal to or lower than the current level is detected, there is unnecessary to add delay task and print logs. This patch fix it. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 64 ++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3bdce1fa4b48..18afc0fa0a12 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -124,42 +124,29 @@ hns3_pf_enable_irq0(struct hns3_hw *hw) } static enum hns3_evt_cause -hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, - uint32_t *vec_val) +hns3_proc_imp_reset_event(struct hns3_adapter *hns, uint32_t *vec_val) { struct hns3_hw *hw = &hns->hw; __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); - if (!is_delay) { - hw->reset.stats.imp_cnt++; - hns3_warn(hw, "IMP reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, "IMP reset detected, don't clear reset status"); - } + hw->reset.stats.imp_cnt++; + hns3_warn(hw, "IMP reset detected, clear reset status"); return HNS3_VECTOR0_EVENT_RST; } static enum hns3_evt_cause -hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, - uint32_t *vec_val) +hns3_proc_global_reset_event(struct hns3_adapter *hns, uint32_t *vec_val) { struct hns3_hw *hw = &hns->hw; __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); - if (!is_delay) { - hw->reset.stats.global_cnt++; - hns3_warn(hw, "Global reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, - "Global reset detected, don't clear reset status"); - } + hw->reset.stats.global_cnt++; + hns3_warn(hw, "Global reset detected, clear reset status"); return HNS3_VECTOR0_EVENT_RST; } @@ -173,14 +160,12 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) uint32_t hw_err_src_reg; uint32_t val; enum hns3_evt_cause ret; - bool is_delay; /* fetch the events from their corresponding regs */ vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); - is_delay = clearval == NULL ? true : false; /* * Assumption: If by any chance reset and mailbox events are reported * together then we will only process reset event and defer the @@ -189,13 +174,13 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) * from H/W just for the mailbox. */ if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ - ret = hns3_proc_imp_reset_event(hns, is_delay, &val); + ret = hns3_proc_imp_reset_event(hns, &val); goto out; } /* Global reset */ if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { - ret = hns3_proc_global_reset_event(hns, is_delay, &val); + ret = hns3_proc_global_reset_event(hns, &val); goto out; } @@ -224,10 +209,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) val = vector0_int_stats; ret = HNS3_VECTOR0_EVENT_OTHER; -out: - if (clearval) - *clearval = val; +out: + *clearval = val; return ret; } @@ -5505,6 +5489,32 @@ is_pf_reset_done(struct hns3_hw *hw) return true; } +static void +hns3_detect_reset_event(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + enum hns3_reset_level new_req = HNS3_NONE_RESET; + enum hns3_reset_level last_req; + uint32_t vector0_intr_state; + + last_req = hns3_get_reset_level(hns, &hw->reset.pending); + vector0_intr_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_intr_state) { + __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); + hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); + new_req = HNS3_IMP_RESET; + } else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_intr_state) { + __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); + hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); + new_req = HNS3_GLOBAL_RESET; + } + + if (new_req != HNS3_NONE_RESET && last_req < new_req) { + hns3_schedule_delayed_reset(hns); + hns3_warn(hw, "High level reset detected, delay do reset"); + } +} + bool hns3_is_reset_pending(struct hns3_adapter *hns) { @@ -5518,7 +5528,7 @@ hns3_is_reset_pending(struct hns3_adapter *hns) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return false; - hns3_check_event_cause(hns, NULL); + hns3_detect_reset_event(hw); reset = hns3_get_reset_level(hns, &hw->reset.pending); if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { From patchwork Fri Oct 27 06:09:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133477 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D17643212; Fri, 27 Oct 2023 08:14:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A144242DB2; Fri, 27 Oct 2023 08:14:01 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id D23C64064A for ; Fri, 27 Oct 2023 08:13:53 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshD69mqzPnjK for ; Fri, 27 Oct 2023 14:09:48 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:51 +0800 From: Jie Hai To: , Yisen Zhuang , "Min Hu (Connor)" , Ferruh Yigit , Huisong Li , Chunsong Feng , "Wei Hu (Xavier)" CC: , , Subject: [PATCH 7/8] net/hns3: fix the imp/global reset interrupted possibly Date: Fri, 27 Oct 2023 14:09:45 +0800 Message-ID: <20231027060947.3183983-8-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang Currently, when the IMP or Global reset detected, the vector0 interrupt is enabled before the reset process is completed. At this moment, if the initialization of IMP is not completed, and the vector0 interrupt may continue to be reported. In this scenario, the IMP/global reset being performed by the driver does not need to be interrupted. Therefore, for IMP and global resets, the driver has to enable the interrupt after the end of reset. The RAS interrupt is also shared with the vector0 interrupt. When the interrupt is disabled, the RAS interrupt can still be reported to the driver and the driver interrupt processing function is also called. In this case, the interrupt status of the IMP/global may still exist. Therefore, this patch also has to the check of the new reset level based on the priority of reset level in the interrupt hnader. Fixes: 2790c6464725 ("net/hns3: support device reset") Fixes: 3988ab0eee52 ("net/hns3: add abnormal interrupt process") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 88 ++++++++++++++++++++++++++++------ drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_intr.c | 2 + 3 files changed, 77 insertions(+), 14 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 18afc0fa0a12..bb9dde9c5bc3 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -215,6 +215,30 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) return ret; } +void +hns3_clear_reset_event(struct hns3_hw *hw) +{ + uint32_t clearval = 0; + + switch (hw->reset.level) { + case HNS3_IMP_RESET: + clearval = BIT(HNS3_VECTOR0_IMPRESET_INT_B); + break; + case HNS3_GLOBAL_RESET: + clearval = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); + break; + default: + break; + } + + if (clearval == 0) + return; + + hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, clearval); + + hns3_pf_enable_irq0(hw); +} + static void hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) { @@ -287,6 +311,34 @@ hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uin } } +static bool +hns3_reset_event_valid(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + enum hns3_reset_level new_req = HNS3_NONE_RESET; + enum hns3_reset_level last_req; + uint32_t vector0_int; + + vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int) + new_req = HNS3_IMP_RESET; + else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int) + new_req = HNS3_GLOBAL_RESET; + if (new_req == HNS3_NONE_RESET) + return true; + + last_req = hns3_get_reset_level(hns, &hw->reset.pending); + if (last_req == HNS3_NONE_RESET) + return true; + + if (new_req > last_req) + return true; + + hns3_warn(hw, "last_req (%u) less than or equal to new_req (%u) ignore", + last_req, new_req); + return false; +} + static void hns3_interrupt_handler(void *param) { @@ -299,6 +351,9 @@ hns3_interrupt_handler(void *param) uint32_t ras_int; uint32_t cmdq_int; + if (!hns3_reset_event_valid(hw)) + return; + /* Disable interrupt */ hns3_pf_disable_irq0(hw); @@ -327,7 +382,11 @@ hns3_interrupt_handler(void *param) } /* Enable interrupt if it is not cause by reset */ - hns3_pf_enable_irq0(hw); + if (event_cause == HNS3_VECTOR0_EVENT_ERR || + event_cause == HNS3_VECTOR0_EVENT_MBX || + event_cause == HNS3_VECTOR0_EVENT_PTP || + event_cause == HNS3_VECTOR0_EVENT_OTHER) + hns3_pf_enable_irq0(hw); } static int @@ -5489,7 +5548,7 @@ is_pf_reset_done(struct hns3_hw *hw) return true; } -static void +static enum hns3_reset_level hns3_detect_reset_event(struct hns3_hw *hw) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); @@ -5501,11 +5560,9 @@ hns3_detect_reset_event(struct hns3_hw *hw) vector0_intr_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_intr_state) { __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); - hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); new_req = HNS3_IMP_RESET; } else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_intr_state) { __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); - hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); new_req = HNS3_GLOBAL_RESET; } @@ -5513,13 +5570,16 @@ hns3_detect_reset_event(struct hns3_hw *hw) hns3_schedule_delayed_reset(hns); hns3_warn(hw, "High level reset detected, delay do reset"); } + + return new_req; } bool hns3_is_reset_pending(struct hns3_adapter *hns) { + enum hns3_reset_level new_req; struct hns3_hw *hw = &hns->hw; - enum hns3_reset_level reset; + enum hns3_reset_level last_req; /* * Only primary can process can process the reset event, @@ -5528,17 +5588,17 @@ hns3_is_reset_pending(struct hns3_adapter *hns) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return false; - hns3_detect_reset_event(hw); - reset = hns3_get_reset_level(hns, &hw->reset.pending); - if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && - hw->reset.level < reset) { - hns3_warn(hw, "High level reset %d is pending", reset); + new_req = hns3_detect_reset_event(hw); + last_req = hns3_get_reset_level(hns, &hw->reset.pending); + if (last_req != HNS3_NONE_RESET && new_req != HNS3_NONE_RESET && + new_req < last_req) { + hns3_warn(hw, "High level reset %d is pending", last_req); return true; } - reset = hns3_get_reset_level(hns, &hw->reset.request); - if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && - hw->reset.level < reset) { - hns3_warn(hw, "High level reset %d is request", reset); + last_req = hns3_get_reset_level(hns, &hw->reset.request); + if (last_req != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && + hw->reset.level < last_req) { + hns3_warn(hw, "High level reset %d is request", last_req); return true; } return false; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index c85a6912ada4..0e8d043704e3 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -1033,6 +1033,7 @@ void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); +void hns3_clear_reset_event(struct hns3_hw *hw); const char *hns3_get_media_type_name(uint8_t media_type); diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index baf5f58e9e2b..c5a3e3797cbd 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -2749,6 +2749,7 @@ hns3_reset_post(struct hns3_adapter *hns) /* IMP will wait ready flag before reset */ hns3_notify_reset_ready(hw, false); hns3_clear_reset_level(hw, &hw->reset.pending); + hns3_clear_reset_event(hw); __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); hw->reset.attempts = 0; hw->reset.stats.success_cnt++; @@ -2798,6 +2799,7 @@ hns3_reset_fail_handle(struct hns3_adapter *hns) struct timeval tv; hns3_clear_reset_level(hw, &hw->reset.pending); + hns3_clear_reset_event(hw); if (hns3_reset_err_handle(hns)) { hw->reset.stage = RESET_STAGE_PREWAIT; hns3_schedule_reset(hns); From patchwork Fri Oct 27 06:09:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133478 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE60343212; Fri, 27 Oct 2023 08:14:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D23C842DCB; Fri, 27 Oct 2023 08:14:02 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 85FF0406BA for ; Fri, 27 Oct 2023 08:13:54 +0200 (CEST) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshF62xjzPnln; Fri, 27 Oct 2023 14:09:49 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Fri, 27 Oct 2023 14:13:52 +0800 From: Jie Hai To: , Yisen Zhuang , "Wei Hu (Xavier)" , Hongbo Zheng , Hao Chen , Ferruh Yigit , "Min Hu (Connor)" , Chunsong Feng , Huisong Li CC: , , Subject: [PATCH 8/8] net/hns3: refactor interrupt state query Date: Fri, 27 Oct 2023 14:09:46 +0800 Message-ID: <20231027060947.3183983-9-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231027060947.3183983-1-haijie1@huawei.com> References: <20231027060947.3183983-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang PF driver get all interrupt states by reading three registers. This logic code block is distributed in many places. So this patch extracts a common function to do this to improve the maintaince. Fixes: f53a793bb7c2 ("net/hns3: add more hardware error types") Fixes: 3988ab0eee52 ("net/hns3: add abnormal interrupt process") Cc: stable@dpdk.org Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 57 +++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index bb9dde9c5bc3..0feea52542f6 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -57,6 +57,12 @@ enum hns3_evt_cause { HNS3_VECTOR0_EVENT_OTHER, }; +struct hns3_intr_state { + uint32_t vector0_state; + uint32_t cmdq_state; + uint32_t hw_err_state; +}; + #define HNS3_SPEEDS_SUPP_FEC (RTE_ETH_LINK_SPEED_10G | \ RTE_ETH_LINK_SPEED_25G | \ RTE_ETH_LINK_SPEED_40G | \ @@ -151,20 +157,23 @@ hns3_proc_global_reset_event(struct hns3_adapter *hns, uint32_t *vec_val) return HNS3_VECTOR0_EVENT_RST; } +static void +hns3_query_intr_state(struct hns3_hw *hw, struct hns3_intr_state *state) +{ + state->vector0_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + state->cmdq_state = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + state->hw_err_state = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); +} + static enum hns3_evt_cause hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) { struct hns3_hw *hw = &hns->hw; - uint32_t vector0_int_stats; - uint32_t cmdq_src_val; - uint32_t hw_err_src_reg; + struct hns3_intr_state state; uint32_t val; enum hns3_evt_cause ret; - /* fetch the events from their corresponding regs */ - vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); - cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); - hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); + hns3_query_intr_state(hw, &state); /* * Assumption: If by any chance reset and mailbox events are reported @@ -173,41 +182,41 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) * RX CMDQ event this time we would receive again another interrupt * from H/W just for the mailbox. */ - if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & state.vector0_state) { /* IMP */ ret = hns3_proc_imp_reset_event(hns, &val); goto out; } /* Global reset */ - if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { + if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & state.vector0_state) { ret = hns3_proc_global_reset_event(hns, &val); goto out; } /* Check for vector0 1588 event source */ - if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { + if (BIT(HNS3_VECTOR0_1588_INT_B) & state.vector0_state) { val = BIT(HNS3_VECTOR0_1588_INT_B); ret = HNS3_VECTOR0_EVENT_PTP; goto out; } /* check for vector0 msix event source */ - if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || - hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { - val = vector0_int_stats | hw_err_src_reg; + if (state.vector0_state & HNS3_VECTOR0_REG_MSIX_MASK || + state.hw_err_state & HNS3_RAS_REG_NFE_MASK) { + val = state.vector0_state | state.hw_err_state; ret = HNS3_VECTOR0_EVENT_ERR; goto out; } /* check for vector0 mailbox(=CMDQ RX) event source */ - if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { - cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); - val = cmdq_src_val; + if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & state.cmdq_state) { + state.cmdq_state &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); + val = state.cmdq_state; ret = HNS3_VECTOR0_EVENT_MBX; goto out; } - val = vector0_int_stats; + val = state.vector0_state; ret = HNS3_VECTOR0_EVENT_OTHER; out: @@ -346,10 +355,8 @@ hns3_interrupt_handler(void *param) struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; enum hns3_evt_cause event_cause; + struct hns3_intr_state state; uint32_t clearval = 0; - uint32_t vector0_int; - uint32_t ras_int; - uint32_t cmdq_int; if (!hns3_reset_event_valid(hw)) return; @@ -358,16 +365,15 @@ hns3_interrupt_handler(void *param) hns3_pf_disable_irq0(hw); event_cause = hns3_check_event_cause(hns, &clearval); - vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); - ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); - cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + hns3_query_intr_state(hw, &state); hns3_delay_before_clear_event_cause(hw, event_cause, clearval); hns3_clear_event_cause(hw, event_cause, clearval); /* vector 0 interrupt is shared with reset and mailbox source events. */ if (event_cause == HNS3_VECTOR0_EVENT_ERR) { hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " "ras_int_stat:0x%x cmdq_int_stat:0x%x", - vector0_int, ras_int, cmdq_int); + state.vector0_state, state.hw_err_state, + state.cmdq_state); hns3_handle_mac_tnl(hw); hns3_handle_error(hns); } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { @@ -378,7 +384,8 @@ hns3_interrupt_handler(void *param) } else if (event_cause != HNS3_VECTOR0_EVENT_PTP) { hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " "ras_int_stat:0x%x cmdq_int_stat:0x%x", - vector0_int, ras_int, cmdq_int); + state.vector0_state, state.hw_err_state, + state.cmdq_state); } /* Enable interrupt if it is not cause by reset */