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GET /api/patches/133476/?format=api
{ "id": 133476, "url": "http://patches.dpdk.org/api/patches/133476/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231027060947.3183983-7-haijie1@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231027060947.3183983-7-haijie1@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231027060947.3183983-7-haijie1@huawei.com", "date": "2023-10-27T06:09:44", "name": "[6/8] net/hns3: fix multiple reset detected log", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "89ebd21b20378f933167fe0c589583be397c2fa6", "submitter": { "id": 2935, "url": "http://patches.dpdk.org/api/people/2935/?format=api", "name": "Jie Hai", "email": "haijie1@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231027060947.3183983-7-haijie1@huawei.com/mbox/", "series": [ { "id": 30018, "url": "http://patches.dpdk.org/api/series/30018/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30018", "date": "2023-10-27T06:09:41", "name": "net/hns3: add some bugfix for hns3", "version": 1, "mbox": "http://patches.dpdk.org/series/30018/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/133476/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/133476/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C5CEE43212;\n\tFri, 27 Oct 2023 08:14:34 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7ED1B427DF;\n\tFri, 27 Oct 2023 08:14:00 +0200 (CEST)", "from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188])\n by mails.dpdk.org (Postfix) with ESMTP id CD6DB40649\n for <dev@dpdk.org>; Fri, 27 Oct 2023 08:13:52 +0200 (CEST)", "from kwepemi500020.china.huawei.com (unknown [172.30.72.53])\n by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SGshQ0tGJzVlys\n for <dev@dpdk.org>; Fri, 27 Oct 2023 14:09:58 +0800 (CST)", "from localhost.localdomain (10.67.165.2) by\n kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2507.31; Fri, 27 Oct 2023 14:13:51 +0800" ], "From": "Jie Hai <haijie1@huawei.com>", "To": "<dev@dpdk.org>, Yisen Zhuang <yisen.zhuang@huawei.com>, Chunsong Feng\n <fengchunsong@huawei.com>, \"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>, \"Min\n Hu (Connor)\" <humin29@huawei.com>, Ferruh Yigit <ferruh.yigit@intel.com>,\n Huisong Li <lihuisong@huawei.com>", "CC": "<fengchengwen@huawei.com>, <liudongdong3@huawei.com>,\n <huangdengdui@huawei.com>", "Subject": "[PATCH 6/8] net/hns3: fix multiple reset detected log", "Date": "Fri, 27 Oct 2023 14:09:44 +0800", "Message-ID": "<20231027060947.3183983-7-haijie1@huawei.com>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20231027060947.3183983-1-haijie1@huawei.com>", "References": "<20231027060947.3183983-1-haijie1@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.2]", "X-ClientProxiedBy": "dggems703-chm.china.huawei.com (10.3.19.180) To\n kwepemi500020.china.huawei.com (7.221.188.8)", "X-CFilter-Loop": "Reflected", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dengdui Huang <huangdengdui@huawei.com>\n\nCurrently, the driver proactively checks whether interrupt exist\n(by checking reset registers), related reset delay task is scheduled.\n\nWhen a reset whose level is equal to or lower than the current level\nis detected, there is unnecessary to add delay task and print logs.\n\nThis patch fix it.\n\nFixes: 2790c6464725 (\"net/hns3: support device reset\")\nCc: stable@dpdk.org\n\nSigned-off-by: Dengdui Huang <huangdengdui@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev.c | 64 ++++++++++++++++++++--------------\n 1 file changed, 37 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 3bdce1fa4b48..18afc0fa0a12 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -124,42 +124,29 @@ hns3_pf_enable_irq0(struct hns3_hw *hw)\n }\n \n static enum hns3_evt_cause\n-hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,\n-\t\t\t uint32_t *vec_val)\n+hns3_proc_imp_reset_event(struct hns3_adapter *hns, uint32_t *vec_val)\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \n \t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t*vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);\n-\tif (!is_delay) {\n-\t\thw->reset.stats.imp_cnt++;\n-\t\thns3_warn(hw, \"IMP reset detected, clear reset status\");\n-\t} else {\n-\t\thns3_schedule_delayed_reset(hns);\n-\t\thns3_warn(hw, \"IMP reset detected, don't clear reset status\");\n-\t}\n+\thw->reset.stats.imp_cnt++;\n+\thns3_warn(hw, \"IMP reset detected, clear reset status\");\n \n \treturn HNS3_VECTOR0_EVENT_RST;\n }\n \n static enum hns3_evt_cause\n-hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,\n-\t\t\t uint32_t *vec_val)\n+hns3_proc_global_reset_event(struct hns3_adapter *hns, uint32_t *vec_val)\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \n \t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \thns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);\n \t*vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);\n-\tif (!is_delay) {\n-\t\thw->reset.stats.global_cnt++;\n-\t\thns3_warn(hw, \"Global reset detected, clear reset status\");\n-\t} else {\n-\t\thns3_schedule_delayed_reset(hns);\n-\t\thns3_warn(hw,\n-\t\t\t \"Global reset detected, don't clear reset status\");\n-\t}\n+\thw->reset.stats.global_cnt++;\n+\thns3_warn(hw, \"Global reset detected, clear reset status\");\n \n \treturn HNS3_VECTOR0_EVENT_RST;\n }\n@@ -173,14 +160,12 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \tuint32_t hw_err_src_reg;\n \tuint32_t val;\n \tenum hns3_evt_cause ret;\n-\tbool is_delay;\n \n \t/* fetch the events from their corresponding regs */\n \tvector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n \tcmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);\n \thw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);\n \n-\tis_delay = clearval == NULL ? true : false;\n \t/*\n \t * Assumption: If by any chance reset and mailbox events are reported\n \t * together then we will only process reset event and defer the\n@@ -189,13 +174,13 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \t * from H/W just for the mailbox.\n \t */\n \tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */\n-\t\tret = hns3_proc_imp_reset_event(hns, is_delay, &val);\n+\t\tret = hns3_proc_imp_reset_event(hns, &val);\n \t\tgoto out;\n \t}\n \n \t/* Global reset */\n \tif (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {\n-\t\tret = hns3_proc_global_reset_event(hns, is_delay, &val);\n+\t\tret = hns3_proc_global_reset_event(hns, &val);\n \t\tgoto out;\n \t}\n \n@@ -224,10 +209,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \n \tval = vector0_int_stats;\n \tret = HNS3_VECTOR0_EVENT_OTHER;\n-out:\n \n-\tif (clearval)\n-\t\t*clearval = val;\n+out:\n+\t*clearval = val;\n \treturn ret;\n }\n \n@@ -5505,6 +5489,32 @@ is_pf_reset_done(struct hns3_hw *hw)\n \t\treturn true;\n }\n \n+static void\n+hns3_detect_reset_event(struct hns3_hw *hw)\n+{\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\tenum hns3_reset_level new_req = HNS3_NONE_RESET;\n+\tenum hns3_reset_level last_req;\n+\tuint32_t vector0_intr_state;\n+\n+\tlast_req = hns3_get_reset_level(hns, &hw->reset.pending);\n+\tvector0_intr_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n+\tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_intr_state) {\n+\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\t\thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n+\t\tnew_req = HNS3_IMP_RESET;\n+\t} else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_intr_state) {\n+\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\t\thns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);\n+\t\tnew_req = HNS3_GLOBAL_RESET;\n+\t}\n+\n+\tif (new_req != HNS3_NONE_RESET && last_req < new_req) {\n+\t\thns3_schedule_delayed_reset(hns);\n+\t\thns3_warn(hw, \"High level reset detected, delay do reset\");\n+\t}\n+}\n+\n bool\n hns3_is_reset_pending(struct hns3_adapter *hns)\n {\n@@ -5518,7 +5528,7 @@ hns3_is_reset_pending(struct hns3_adapter *hns)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn false;\n \n-\thns3_check_event_cause(hns, NULL);\n+\thns3_detect_reset_event(hw);\n \treset = hns3_get_reset_level(hns, &hw->reset.pending);\n \tif (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&\n \t hw->reset.level < reset) {\n", "prefixes": [ "6/8" ] }