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GET /api/patches/130072/?format=api
{ "id": 130072, "url": "http://patches.dpdk.org/api/patches/130072/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230810100908.1756-1-gmuthukrishn@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230810100908.1756-1-gmuthukrishn@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230810100908.1756-1-gmuthukrishn@marvell.com", "date": "2023-08-10T10:09:08", "name": "app/dma-perf: add SG copy support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d2a88e2bed28b91f3565d2c14009154693ff8c84", "submitter": { "id": 2301, "url": "http://patches.dpdk.org/api/people/2301/?format=api", "name": "Gowrishankar Muthukrishnan", "email": "gmuthukrishn@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230810100908.1756-1-gmuthukrishn@marvell.com/mbox/", "series": [ { "id": 29151, "url": "http://patches.dpdk.org/api/series/29151/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29151", "date": "2023-08-10T10:09:08", "name": "app/dma-perf: add SG copy support", "version": 1, "mbox": "http://patches.dpdk.org/series/29151/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/130072/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/130072/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5449D4301C;\n\tThu, 10 Aug 2023 12:09:34 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4014E42D12;\n\tThu, 10 Aug 2023 12:09:34 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 9D21240691\n for <dev@dpdk.org>; Thu, 10 Aug 2023 12:09:32 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 37A57Pw1014697; Thu, 10 Aug 2023 03:09:31 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sc57snu99-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 10 Aug 2023 03:09:31 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 10 Aug 2023 03:09:29 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 10 Aug 2023 03:09:29 -0700", "from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34])\n by maili.marvell.com (Postfix) with ESMTP id E90D03F705B;\n Thu, 10 Aug 2023 03:09:27 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=JwRbIaCCSDsMUKqkY+INsvMZpRJu0NcEfledYo/jT/E=;\n b=CDxTeGny7PfKowguasNuyOZM3xDfuAzs9dsV8Txk5vLWflIh/Dhig/oWuViMOtQlvFcT\n x1z8kwMIW+V4ZNSIXhW/32fpT1EONhxeEDE9ifBCFvN+YVbdZs7DaeoC0a6W18xY/Z18\n gu3U/n3waBAShEVys38ObKtDjPE/1wQhRCMXywAP/zmil4lARg82CfF0BfzXbAum5I04\n JgNxxwkCOk1T9dv3qxc9DJK1ighTztwa9B7tbwP73hTfQu9rveheC0cvqVkbld08O/A7\n SFVzGDtHhRBhh5lFVHHgVBUVflN8qLeNaHHwE4iNGjLdXcIHuULK85sg2PeisG3J9hTy NQ==", "From": "Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<anoobj@marvell.com>, Cheng Jiang <cheng1.jiang@intel.com>, \"Gowrishankar\n Muthukrishnan\" <gmuthukrishn@marvell.com>", "Subject": "[PATCH] app/dma-perf: add SG copy support", "Date": "Thu, 10 Aug 2023 15:39:08 +0530", "Message-ID": "<20230810100908.1756-1-gmuthukrishn@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "AO4usnTg8m0Ye-7fJAwWPafOxn_kdNT-", "X-Proofpoint-ORIG-GUID": "AO4usnTg8m0Ye-7fJAwWPafOxn_kdNT-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-08-10_09,2023-08-09_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add SG copy support.\n\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nChange-Id: I17c736bec5c8309b4c9cbe9fb1eafa5b5a00a3fe\n---\n app/test-dma-perf/benchmark.c | 204 +++++++++++++++++++++++++++++-----\n app/test-dma-perf/config.ini | 17 +++\n app/test-dma-perf/main.c | 35 +++++-\n app/test-dma-perf/main.h | 5 +-\n 4 files changed, 231 insertions(+), 30 deletions(-)", "diff": "diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c\nindex 9e5b5dc770..5f03f99b7b 100644\n--- a/app/test-dma-perf/benchmark.c\n+++ b/app/test-dma-perf/benchmark.c\n@@ -46,6 +46,10 @@ struct lcore_params {\n \tuint16_t test_secs;\n \tstruct rte_mbuf **srcs;\n \tstruct rte_mbuf **dsts;\n+\tstruct rte_dma_sge **src_sges;\n+\tstruct rte_dma_sge **dst_sges;\n+\tuint8_t src_ptrs;\n+\tuint8_t dst_ptrs;\n \tvolatile struct worker_info worker_info;\n };\n \n@@ -86,21 +90,31 @@ calc_result(uint32_t buf_size, uint32_t nr_buf, uint16_t nb_workers, uint16_t te\n }\n \n static void\n-output_result(uint8_t scenario_id, uint32_t lcore_id, char *dma_name, uint16_t ring_size,\n-\t\t\tuint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size, uint32_t nr_buf,\n-\t\t\tfloat memory, float bandwidth, float mops, bool is_dma)\n+output_result(struct test_configure *cfg, struct lcore_params *para,\n+\t\t\tuint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size,\n+\t\t\tuint32_t nr_buf, float memory, float bandwidth, float mops)\n {\n-\tif (is_dma)\n-\t\tprintf(\"lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u.\\n\",\n-\t\t\t\tlcore_id, dma_name, ring_size, kick_batch);\n-\telse\n+\tuint16_t ring_size = cfg->ring_size.cur;\n+\tuint8_t scenario_id = cfg->scenario_id;\n+\tuint32_t lcore_id = para->lcore_id;\n+\tchar *dma_name = para->dma_name;\n+\n+\tif (cfg->is_dma) {\n+\t\tprintf(\"lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u\", lcore_id,\n+\t\t dma_name, ring_size, kick_batch);\n+\t\tif (cfg->is_sg)\n+\t\t\tprintf(\" DMA src ptrs: %u, dst ptrs: %u\",\n+\t\t\t para->src_ptrs, para->dst_ptrs);\n+\t\tprintf(\".\\n\");\n+\t} else {\n \t\tprintf(\"lcore %u\\n\", lcore_id);\n+\t}\n \n \tprintf(\"Average Cycles/op: %\" PRIu64 \", Buffer Size: %u B, Buffer Number: %u, Memory: %.2lf MB, Frequency: %.3lf Ghz.\\n\",\n \t\t\tave_cycle, buf_size, nr_buf, memory, rte_get_timer_hz()/1000000000.0);\n \tprintf(\"Average Bandwidth: %.3lf Gbps, MOps: %.3lf\\n\", bandwidth, mops);\n \n-\tif (is_dma)\n+\tif (cfg->is_dma)\n \t\tsnprintf(output_str[lcore_id], MAX_OUTPUT_STR_LEN, CSV_LINE_DMA_FMT,\n \t\t\tscenario_id, lcore_id, dma_name, ring_size, kick_batch, buf_size,\n \t\t\tnr_buf, memory, ave_cycle, bandwidth, mops);\n@@ -130,7 +144,7 @@ cache_flush_buf(__rte_unused struct rte_mbuf **array,\n \n /* Configuration of device. */\n static void\n-configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size)\n+configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size, uint8_t ptrs_max)\n {\n \tuint16_t vchan = 0;\n \tstruct rte_dma_info info;\n@@ -153,6 +167,10 @@ configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size)\n \t\trte_exit(EXIT_FAILURE, \"Error, no configured queues reported on device id. %u\\n\",\n \t\t\t\tdev_id);\n \n+\tif (info.max_sges < ptrs_max)\n+\t\trte_exit(EXIT_FAILURE, \"Error, DMA ptrs more than supported by device id %u.\\n\",\n+\t\t\t\tdev_id);\n+\n \tif (rte_dma_start(dev_id) != 0)\n \t\trte_exit(EXIT_FAILURE, \"Error with dma start.\\n\");\n }\n@@ -166,8 +184,12 @@ config_dmadevs(struct test_configure *cfg)\n \tuint32_t i;\n \tint dev_id;\n \tuint16_t nb_dmadevs = 0;\n+\tuint8_t ptrs_max = 0;\n \tchar *dma_name;\n \n+\tif (cfg->is_sg)\n+\t\tptrs_max = RTE_MAX(cfg->src_ptrs, cfg->dst_ptrs);\n+\n \tfor (i = 0; i < ldm->cnt; i++) {\n \t\tdma_name = ldm->dma_names[i];\n \t\tdev_id = rte_dma_get_dev_id_by_name(dma_name);\n@@ -177,7 +199,7 @@ config_dmadevs(struct test_configure *cfg)\n \t\t}\n \n \t\tldm->dma_ids[i] = dev_id;\n-\t\tconfigure_dmadev_queue(dev_id, ring_size);\n+\t\tconfigure_dmadev_queue(dev_id, ring_size, ptrs_max);\n \t\t++nb_dmadevs;\n \t}\n \n@@ -217,7 +239,7 @@ do_dma_submit_and_poll(uint16_t dev_id, uint64_t *async_cnt,\n }\n \n static inline int\n-do_dma_mem_copy(void *p)\n+do_dma_plain_mem_copy(void *p)\n {\n \tstruct lcore_params *para = (struct lcore_params *)p;\n \tvolatile struct worker_info *worker_info = &(para->worker_info);\n@@ -270,6 +292,61 @@ do_dma_mem_copy(void *p)\n \treturn 0;\n }\n \n+static inline int\n+do_dma_sg_mem_copy(void *p)\n+{\n+\tstruct lcore_params *para = (struct lcore_params *)p;\n+\tvolatile struct worker_info *worker_info = &(para->worker_info);\n+\tstruct rte_dma_sge **src_sges = para->src_sges;\n+\tstruct rte_dma_sge **dst_sges = para->dst_sges;\n+\tconst uint16_t dev_id = para->dev_id;\n+\tconst uint32_t nr_buf = para->nr_buf;\n+\tconst uint16_t kick_batch = para->kick_batch;\n+\tconst uint8_t src_ptrs = para->src_ptrs;\n+\tconst uint8_t dst_ptrs = para->dst_ptrs;\n+\tuint16_t nr_cpl;\n+\tuint64_t async_cnt = 0;\n+\tuint32_t i;\n+\tuint32_t poll_cnt = 0;\n+\tint ret;\n+\n+\tworker_info->stop_flag = false;\n+\tworker_info->ready_flag = true;\n+\n+\twhile (!worker_info->start_flag)\n+\t\t;\n+\n+\twhile (1) {\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+dma_copy:\n+\t\t\tret = rte_dma_copy_sg(dev_id, 0, src_sges[i], dst_sges[i],\n+\t\t\t\t\t\t\t\t src_ptrs, dst_ptrs, 0);\n+\t\t\tif (unlikely(ret < 0)) {\n+\t\t\t\tif (ret == -ENOSPC) {\n+\t\t\t\t\tdo_dma_submit_and_poll(dev_id, &async_cnt, worker_info);\n+\t\t\t\t\tgoto dma_copy;\n+\t\t\t\t} else\n+\t\t\t\t\terror_exit(dev_id);\n+\t\t\t}\n+\t\t\tasync_cnt++;\n+\n+\t\t\tif ((async_cnt % kick_batch) == 0)\n+\t\t\t\tdo_dma_submit_and_poll(dev_id, &async_cnt, worker_info);\n+\t\t}\n+\n+\t\tif (worker_info->stop_flag)\n+\t\t\tbreak;\n+\t}\n+\n+\trte_dma_submit(dev_id, 0);\n+\twhile ((async_cnt > 0) && (poll_cnt++ < POLL_MAX)) {\n+\t\tnr_cpl = rte_dma_completed(dev_id, 0, MAX_DMA_CPL_NB, NULL, NULL);\n+\t\tasync_cnt -= nr_cpl;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static inline int\n do_cpu_mem_copy(void *p)\n {\n@@ -303,8 +380,9 @@ do_cpu_mem_copy(void *p)\n }\n \n static int\n-setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n-\t\t\tstruct rte_mbuf ***dsts)\n+setup_memory_env(struct test_configure *cfg,\n+\t\t\t struct rte_mbuf ***srcs, struct rte_mbuf ***dsts,\n+\t\t\t struct rte_dma_sge ***src_sges, struct rte_dma_sge ***dst_sges)\n {\n \tunsigned int buf_size = cfg->buf_size.cur;\n \tunsigned int nr_sockets, i;\n@@ -366,15 +444,69 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\tmemset(rte_pktmbuf_mtod((*dsts)[i], void *), 0, buf_size);\n \t}\n \n+\tif (cfg->is_sg) {\n+\t\tuint8_t src_ptrs = cfg->src_ptrs;\n+\t\tuint8_t dst_ptrs = cfg->dst_ptrs;\n+\t\tuint32_t sglen_src, sglen_dst;\n+\t\tuint32_t nr_buf = cfg->nr_buf;\n+\t\tuint8_t j;\n+\n+\t\t*src_sges = rte_malloc(NULL, nr_buf * sizeof(struct rte_dma_sge **), 0);\n+\t\tif (*src_sges == NULL) {\n+\t\t\tprintf(\"Error: src_sges array malloc failed.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t(*src_sges)[i] = rte_malloc(NULL, src_ptrs * sizeof(struct rte_dma_sge), 0);\n+\t\t\tif ((*src_sges)[i] == NULL) {\n+\t\t\t\tprintf(\"Error: src_sges malloc failed.\\n\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\n+\t\t*dst_sges = rte_malloc(NULL, nr_buf * sizeof(struct rte_dma_sge **), 0);\n+\t\tif (*dst_sges == NULL) {\n+\t\t\tprintf(\"Error: dst_sges array malloc failed.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t(*dst_sges)[i] = rte_malloc(NULL, dst_ptrs * sizeof(struct rte_dma_sge), 0);\n+\t\t\tif ((*dst_sges)[i] == NULL) {\n+\t\t\t\tprintf(\"Error: dst_sges malloc failed.\\n\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\n+\t\tsglen_src = buf_size / src_ptrs;\n+\t\tsglen_dst = buf_size / dst_ptrs;\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\tfor (j = 0; j < src_ptrs; j++) {\n+\t\t\t\t(*src_sges)[i][j].addr = rte_pktmbuf_iova((*srcs)[i]) +\n+\t\t\t\t\t\t\t\t\t\tsglen_src * j;\n+\t\t\t\t(*src_sges)[i][j].length = sglen_src;\n+\t\t\t}\n+\t\t\t(*src_sges)[i][j-1].length += buf_size % src_ptrs;\n+\n+\t\t\tfor (j = 0; j < dst_ptrs; j++) {\n+\t\t\t\t(*dst_sges)[i][j].addr = rte_pktmbuf_iova((*dsts)[i]) +\n+\t\t\t\t\t\t\t\t\t\tsglen_dst * j;\n+\t\t\t\t(*dst_sges)[i][j].length = sglen_dst;\n+\t\t\t}\n+\t\t\t(*dst_sges)[i][j-1].length += buf_size % dst_ptrs;\n+\t\t}\n+\t}\n \treturn 0;\n }\n \n int\n-mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n+mem_copy_benchmark(struct test_configure *cfg)\n {\n \tuint16_t i;\n \tuint32_t offset;\n \tunsigned int lcore_id = 0;\n+\tstruct rte_dma_sge **src_sges = NULL, **dst_sges = NULL;\n \tstruct rte_mbuf **srcs = NULL, **dsts = NULL;\n \tstruct lcore_dma_map_t *ldm = &cfg->lcore_dma_map;\n \tunsigned int buf_size = cfg->buf_size.cur;\n@@ -389,10 +521,10 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \tfloat bandwidth, bandwidth_total;\n \tint ret = 0;\n \n-\tif (setup_memory_env(cfg, &srcs, &dsts) < 0)\n+\tif (setup_memory_env(cfg, &srcs, &dsts, &src_sges, &dst_sges) < 0)\n \t\tgoto out;\n \n-\tif (is_dma)\n+\tif (cfg->is_dma)\n \t\tif (config_dmadevs(cfg) < 0)\n \t\t\tgoto out;\n \n@@ -412,7 +544,7 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\t\tprintf(\"lcore parameters malloc failure for lcore %d\\n\", lcore_id);\n \t\t\tbreak;\n \t\t}\n-\t\tif (is_dma) {\n+\t\tif (cfg->is_dma) {\n \t\t\tlcores[i]->dma_name = ldm->dma_names[i];\n \t\t\tlcores[i]->dev_id = ldm->dma_ids[i];\n \t\t\tlcores[i]->kick_batch = kick_batch;\n@@ -426,10 +558,23 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\tlcores[i]->scenario_id = cfg->scenario_id;\n \t\tlcores[i]->lcore_id = lcore_id;\n \n-\t\tif (is_dma)\n-\t\t\trte_eal_remote_launch(do_dma_mem_copy, (void *)(lcores[i]), lcore_id);\n-\t\telse\n+\t\tif (cfg->is_sg) {\n+\t\t\tlcores[i]->src_ptrs = cfg->src_ptrs;\n+\t\t\tlcores[i]->dst_ptrs = cfg->dst_ptrs;\n+\t\t\tlcores[i]->src_sges = src_sges + offset * cfg->src_ptrs;\n+\t\t\tlcores[i]->dst_sges = dst_sges + offset * cfg->dst_ptrs;\n+\t\t}\n+\n+\t\tif (cfg->is_dma) {\n+\t\t\tif (!cfg->is_sg)\n+\t\t\t\trte_eal_remote_launch(do_dma_plain_mem_copy, (void *)(lcores[i]),\n+\t\t\t\t\tlcore_id);\n+\t\t\telse\n+\t\t\t\trte_eal_remote_launch(do_dma_sg_mem_copy, (void *)(lcores[i]),\n+\t\t\t\t\tlcore_id);\n+\t\t} else {\n \t\t\trte_eal_remote_launch(do_cpu_mem_copy, (void *)(lcores[i]), lcore_id);\n+\t\t}\n \t}\n \n \twhile (1) {\n@@ -478,10 +623,8 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\tcalc_result(buf_size, nr_buf, nb_workers, test_secs,\n \t\t\tlcores[i]->worker_info.test_cpl,\n \t\t\t&memory, &avg_cycles, &bandwidth, &mops);\n-\t\toutput_result(cfg->scenario_id, lcores[i]->lcore_id,\n-\t\t\t\t\tlcores[i]->dma_name, cfg->ring_size.cur, kick_batch,\n-\t\t\t\t\tavg_cycles, buf_size, nr_buf / nb_workers, memory,\n-\t\t\t\t\tbandwidth, mops, is_dma);\n+\t\toutput_result(cfg, lcores[i], kick_batch, avg_cycles, buf_size,\n+\t\t\tnr_buf / nb_workers, memory, bandwidth, mops);\n \t\tmops_total += mops;\n \t\tbandwidth_total += bandwidth;\n \t\tavg_cycles_total += avg_cycles;\n@@ -510,13 +653,24 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \trte_mempool_free(dst_pool);\n \tdst_pool = NULL;\n \n+\t/* free sges for mbufs */\n+\tfor (i = 0; i < nr_buf; i++) {\n+\t\trte_free(src_sges[i]);\n+\t\trte_free(dst_sges[i]);\n+\t}\n+\n+\trte_free(src_sges);\n+\tsrc_sges = NULL;\n+\n+\trte_free(dst_sges);\n+\tdst_sges = NULL;\n \t/* free the worker parameters */\n \tfor (i = 0; i < nb_workers; i++) {\n \t\trte_free(lcores[i]);\n \t\tlcores[i] = NULL;\n \t}\n \n-\tif (is_dma) {\n+\tif (cfg->is_dma) {\n \t\tfor (i = 0; i < nb_workers; i++) {\n \t\t\tprintf(\"Stopping dmadev %d\\n\", ldm->dma_ids[i]);\n \t\t\trte_dma_stop(ldm->dma_ids[i]);\ndiff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini\nindex b550f4b23f..f1b268a384 100644\n--- a/app/test-dma-perf/config.ini\n+++ b/app/test-dma-perf/config.ini\n@@ -9,6 +9,8 @@\n ; \"buf_size\" denotes the memory size of a single operation.\n ; \"dma_ring_size\" denotes the dma ring buffer size. It should be must be a power of two, and between\n ; 64 and 4096.\n+; \"dma_ptrs_src\" denotes number of source segments.\n+; \"dma_ptrs_dst\" denotes number of destination segments.\n ; \"kick_batch\" denotes the dma operation batch size, and should be greater than 1 normally.\n \n ; The format for variables is variable=first,last,increment,ADD|MUL.\n@@ -50,6 +52,21 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n eal_args=--in-memory --file-prefix=test\n \n [case2]\n+type=DMA_MEM_COPY\n+mem_size=10\n+buf_size=64,8192,2,MUL\n+dma_ring_size=1024\n+dma_ptrs_src=4\n+dma_ptrs_dst=1\n+kick_batch=32\n+src_numa_node=0\n+dst_numa_node=0\n+cache_flush=0\n+test_seconds=2\n+lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n+eal_args=--in-memory --file-prefix=test\n+\n+[case3]\n type=CPU_MEM_COPY\n mem_size=10\n buf_size=64,8192,2,MUL\ndiff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c\nindex bbba06ec1b..a4958d7a0f 100644\n--- a/app/test-dma-perf/main.c\n+++ b/app/test-dma-perf/main.c\n@@ -93,10 +93,8 @@ run_test_case(struct test_configure *case_cfg)\n \n \tswitch (case_cfg->test_type) {\n \tcase TEST_TYPE_DMA_MEM_COPY:\n-\t\tret = mem_copy_benchmark(case_cfg, true);\n-\t\tbreak;\n \tcase TEST_TYPE_CPU_MEM_COPY:\n-\t\tret = mem_copy_benchmark(case_cfg, false);\n+\t\tret = mem_copy_benchmark(case_cfg);\n \t\tbreak;\n \tdefault:\n \t\tprintf(\"Unknown test type. %s\\n\", case_cfg->test_type_str);\n@@ -325,7 +323,8 @@ load_configs(const char *path)\n \tchar section_name[CFG_NAME_LEN];\n \tconst char *case_type;\n \tconst char *lcore_dma;\n-\tconst char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str;\n+\tconst char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str,\n+\t\t*src_ptrs_str, *dst_ptrs_str;\n \tint args_nr, nb_vp;\n \tbool is_dma;\n \n@@ -361,12 +360,14 @@ load_configs(const char *path)\n \t\t\ttest_case->test_type = TEST_TYPE_CPU_MEM_COPY;\n \t\t\ttest_case->test_type_str = CPU_MEM_COPY;\n \t\t\tis_dma = false;\n+\n \t\t} else {\n \t\t\tprintf(\"Error: Wrong test case type %s in case%d.\\n\", case_type, i + 1);\n \t\t\ttest_case->is_valid = false;\n \t\t\tcontinue;\n \t\t}\n \n+\t\ttest_case->is_dma = is_dma;\n \t\ttest_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n \t\t\t\t\t\t\t\tsection_name, \"src_numa_node\"));\n \t\ttest_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n@@ -401,6 +402,32 @@ load_configs(const char *path)\n \t\t\t} else if (args_nr == 4)\n \t\t\t\tnb_vp++;\n \n+\t\t\tsrc_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name,\n+\t\t\t\t\t\t\t\t\"dma_ptrs_src\");\n+\t\t\tif (src_ptrs_str != NULL) {\n+\t\t\t\ttest_case->src_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n+\t\t\t\t\t\t\t\tsection_name, \"dma_ptrs_src\"));\n+\t\t\t}\n+\n+\t\t\tdst_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name,\n+\t\t\t\t\t\t\t\t\"dma_ptrs_dst\");\n+\t\t\tif (dst_ptrs_str != NULL) {\n+\t\t\t\ttest_case->dst_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n+\t\t\t\t\t\t\t\tsection_name, \"dma_ptrs_dst\"));\n+\t\t\t}\n+\n+\t\t\tif ((src_ptrs_str != NULL && dst_ptrs_str == NULL) ||\n+\t\t\t (src_ptrs_str == NULL && dst_ptrs_str != NULL)) {\n+\t\t\t\tprintf(\"parse dma_ptrs_src, dma_ptrs_dst error in case %d.\\n\",\n+\t\t\t\t\ti + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t} else if (src_ptrs_str != NULL && dst_ptrs_str != NULL) {\n+\t\t\t\ttest_case->is_sg = true;\n+\t\t\t} else {\n+\t\t\t\ttest_case->is_sg = false;\n+\t\t\t}\n+\n \t\t\tkick_batch_str = rte_cfgfile_get_entry(cfgfile, section_name, \"kick_batch\");\n \t\t\targs_nr = parse_entry(kick_batch_str, &test_case->kick_batch);\n \t\t\tif (args_nr < 0) {\ndiff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h\nindex 57a9f71a06..9a3a32a018 100644\n--- a/app/test-dma-perf/main.h\n+++ b/app/test-dma-perf/main.h\n@@ -47,11 +47,14 @@ struct test_configure {\n \tuint16_t dst_numa_node;\n \tuint16_t opcode;\n \tbool is_dma;\n+\tbool is_sg;\n \tstruct lcore_dma_map_t lcore_dma_map;\n \tstruct test_configure_entry mem_size;\n \tstruct test_configure_entry buf_size;\n \tstruct test_configure_entry ring_size;\n \tstruct test_configure_entry kick_batch;\n+\tuint8_t src_ptrs;\n+\tuint8_t dst_ptrs;\n \tuint8_t cache_flush;\n \tuint32_t nr_buf;\n \tuint16_t test_secs;\n@@ -59,6 +62,6 @@ struct test_configure {\n \tuint8_t scenario_id;\n };\n \n-int mem_copy_benchmark(struct test_configure *cfg, bool is_dma);\n+int mem_copy_benchmark(struct test_configure *cfg);\n \n #endif /* _MAIN_H_ */\n", "prefixes": [] }