From patchwork Thu Aug 10 10:09:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 130072 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5449D4301C; Thu, 10 Aug 2023 12:09:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4014E42D12; Thu, 10 Aug 2023 12:09:34 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9D21240691 for ; Thu, 10 Aug 2023 12:09:32 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37A57Pw1014697; Thu, 10 Aug 2023 03:09:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=JwRbIaCCSDsMUKqkY+INsvMZpRJu0NcEfledYo/jT/E=; b=CDxTeGny7PfKowguasNuyOZM3xDfuAzs9dsV8Txk5vLWflIh/Dhig/oWuViMOtQlvFcT x1z8kwMIW+V4ZNSIXhW/32fpT1EONhxeEDE9ifBCFvN+YVbdZs7DaeoC0a6W18xY/Z18 gu3U/n3waBAShEVys38ObKtDjPE/1wQhRCMXywAP/zmil4lARg82CfF0BfzXbAum5I04 JgNxxwkCOk1T9dv3qxc9DJK1ighTztwa9B7tbwP73hTfQu9rveheC0cvqVkbld08O/A7 SFVzGDtHhRBhh5lFVHHgVBUVflN8qLeNaHHwE4iNGjLdXcIHuULK85sg2PeisG3J9hTy NQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sc57snu99-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 10 Aug 2023 03:09:31 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 10 Aug 2023 03:09:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 10 Aug 2023 03:09:29 -0700 Received: from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34]) by maili.marvell.com (Postfix) with ESMTP id E90D03F705B; Thu, 10 Aug 2023 03:09:27 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , Cheng Jiang , "Gowrishankar Muthukrishnan" Subject: [PATCH] app/dma-perf: add SG copy support Date: Thu, 10 Aug 2023 15:39:08 +0530 Message-ID: <20230810100908.1756-1-gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Proofpoint-GUID: AO4usnTg8m0Ye-7fJAwWPafOxn_kdNT- X-Proofpoint-ORIG-GUID: AO4usnTg8m0Ye-7fJAwWPafOxn_kdNT- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_09,2023-08-09_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add SG copy support. Signed-off-by: Gowrishankar Muthukrishnan Change-Id: I17c736bec5c8309b4c9cbe9fb1eafa5b5a00a3fe --- app/test-dma-perf/benchmark.c | 204 +++++++++++++++++++++++++++++----- app/test-dma-perf/config.ini | 17 +++ app/test-dma-perf/main.c | 35 +++++- app/test-dma-perf/main.h | 5 +- 4 files changed, 231 insertions(+), 30 deletions(-) diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c index 9e5b5dc770..5f03f99b7b 100644 --- a/app/test-dma-perf/benchmark.c +++ b/app/test-dma-perf/benchmark.c @@ -46,6 +46,10 @@ struct lcore_params { uint16_t test_secs; struct rte_mbuf **srcs; struct rte_mbuf **dsts; + struct rte_dma_sge **src_sges; + struct rte_dma_sge **dst_sges; + uint8_t src_ptrs; + uint8_t dst_ptrs; volatile struct worker_info worker_info; }; @@ -86,21 +90,31 @@ calc_result(uint32_t buf_size, uint32_t nr_buf, uint16_t nb_workers, uint16_t te } static void -output_result(uint8_t scenario_id, uint32_t lcore_id, char *dma_name, uint16_t ring_size, - uint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size, uint32_t nr_buf, - float memory, float bandwidth, float mops, bool is_dma) +output_result(struct test_configure *cfg, struct lcore_params *para, + uint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size, + uint32_t nr_buf, float memory, float bandwidth, float mops) { - if (is_dma) - printf("lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u.\n", - lcore_id, dma_name, ring_size, kick_batch); - else + uint16_t ring_size = cfg->ring_size.cur; + uint8_t scenario_id = cfg->scenario_id; + uint32_t lcore_id = para->lcore_id; + char *dma_name = para->dma_name; + + if (cfg->is_dma) { + printf("lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u", lcore_id, + dma_name, ring_size, kick_batch); + if (cfg->is_sg) + printf(" DMA src ptrs: %u, dst ptrs: %u", + para->src_ptrs, para->dst_ptrs); + printf(".\n"); + } else { printf("lcore %u\n", lcore_id); + } printf("Average Cycles/op: %" PRIu64 ", Buffer Size: %u B, Buffer Number: %u, Memory: %.2lf MB, Frequency: %.3lf Ghz.\n", ave_cycle, buf_size, nr_buf, memory, rte_get_timer_hz()/1000000000.0); printf("Average Bandwidth: %.3lf Gbps, MOps: %.3lf\n", bandwidth, mops); - if (is_dma) + if (cfg->is_dma) snprintf(output_str[lcore_id], MAX_OUTPUT_STR_LEN, CSV_LINE_DMA_FMT, scenario_id, lcore_id, dma_name, ring_size, kick_batch, buf_size, nr_buf, memory, ave_cycle, bandwidth, mops); @@ -130,7 +144,7 @@ cache_flush_buf(__rte_unused struct rte_mbuf **array, /* Configuration of device. */ static void -configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size) +configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size, uint8_t ptrs_max) { uint16_t vchan = 0; struct rte_dma_info info; @@ -153,6 +167,10 @@ configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size) rte_exit(EXIT_FAILURE, "Error, no configured queues reported on device id. %u\n", dev_id); + if (info.max_sges < ptrs_max) + rte_exit(EXIT_FAILURE, "Error, DMA ptrs more than supported by device id %u.\n", + dev_id); + if (rte_dma_start(dev_id) != 0) rte_exit(EXIT_FAILURE, "Error with dma start.\n"); } @@ -166,8 +184,12 @@ config_dmadevs(struct test_configure *cfg) uint32_t i; int dev_id; uint16_t nb_dmadevs = 0; + uint8_t ptrs_max = 0; char *dma_name; + if (cfg->is_sg) + ptrs_max = RTE_MAX(cfg->src_ptrs, cfg->dst_ptrs); + for (i = 0; i < ldm->cnt; i++) { dma_name = ldm->dma_names[i]; dev_id = rte_dma_get_dev_id_by_name(dma_name); @@ -177,7 +199,7 @@ config_dmadevs(struct test_configure *cfg) } ldm->dma_ids[i] = dev_id; - configure_dmadev_queue(dev_id, ring_size); + configure_dmadev_queue(dev_id, ring_size, ptrs_max); ++nb_dmadevs; } @@ -217,7 +239,7 @@ do_dma_submit_and_poll(uint16_t dev_id, uint64_t *async_cnt, } static inline int -do_dma_mem_copy(void *p) +do_dma_plain_mem_copy(void *p) { struct lcore_params *para = (struct lcore_params *)p; volatile struct worker_info *worker_info = &(para->worker_info); @@ -270,6 +292,61 @@ do_dma_mem_copy(void *p) return 0; } +static inline int +do_dma_sg_mem_copy(void *p) +{ + struct lcore_params *para = (struct lcore_params *)p; + volatile struct worker_info *worker_info = &(para->worker_info); + struct rte_dma_sge **src_sges = para->src_sges; + struct rte_dma_sge **dst_sges = para->dst_sges; + const uint16_t dev_id = para->dev_id; + const uint32_t nr_buf = para->nr_buf; + const uint16_t kick_batch = para->kick_batch; + const uint8_t src_ptrs = para->src_ptrs; + const uint8_t dst_ptrs = para->dst_ptrs; + uint16_t nr_cpl; + uint64_t async_cnt = 0; + uint32_t i; + uint32_t poll_cnt = 0; + int ret; + + worker_info->stop_flag = false; + worker_info->ready_flag = true; + + while (!worker_info->start_flag) + ; + + while (1) { + for (i = 0; i < nr_buf; i++) { +dma_copy: + ret = rte_dma_copy_sg(dev_id, 0, src_sges[i], dst_sges[i], + src_ptrs, dst_ptrs, 0); + if (unlikely(ret < 0)) { + if (ret == -ENOSPC) { + do_dma_submit_and_poll(dev_id, &async_cnt, worker_info); + goto dma_copy; + } else + error_exit(dev_id); + } + async_cnt++; + + if ((async_cnt % kick_batch) == 0) + do_dma_submit_and_poll(dev_id, &async_cnt, worker_info); + } + + if (worker_info->stop_flag) + break; + } + + rte_dma_submit(dev_id, 0); + while ((async_cnt > 0) && (poll_cnt++ < POLL_MAX)) { + nr_cpl = rte_dma_completed(dev_id, 0, MAX_DMA_CPL_NB, NULL, NULL); + async_cnt -= nr_cpl; + } + + return 0; +} + static inline int do_cpu_mem_copy(void *p) { @@ -303,8 +380,9 @@ do_cpu_mem_copy(void *p) } static int -setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, - struct rte_mbuf ***dsts) +setup_memory_env(struct test_configure *cfg, + struct rte_mbuf ***srcs, struct rte_mbuf ***dsts, + struct rte_dma_sge ***src_sges, struct rte_dma_sge ***dst_sges) { unsigned int buf_size = cfg->buf_size.cur; unsigned int nr_sockets, i; @@ -366,15 +444,69 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs, memset(rte_pktmbuf_mtod((*dsts)[i], void *), 0, buf_size); } + if (cfg->is_sg) { + uint8_t src_ptrs = cfg->src_ptrs; + uint8_t dst_ptrs = cfg->dst_ptrs; + uint32_t sglen_src, sglen_dst; + uint32_t nr_buf = cfg->nr_buf; + uint8_t j; + + *src_sges = rte_malloc(NULL, nr_buf * sizeof(struct rte_dma_sge **), 0); + if (*src_sges == NULL) { + printf("Error: src_sges array malloc failed.\n"); + return -1; + } + + for (i = 0; i < nr_buf; i++) { + (*src_sges)[i] = rte_malloc(NULL, src_ptrs * sizeof(struct rte_dma_sge), 0); + if ((*src_sges)[i] == NULL) { + printf("Error: src_sges malloc failed.\n"); + return -1; + } + } + + *dst_sges = rte_malloc(NULL, nr_buf * sizeof(struct rte_dma_sge **), 0); + if (*dst_sges == NULL) { + printf("Error: dst_sges array malloc failed.\n"); + return -1; + } + + for (i = 0; i < nr_buf; i++) { + (*dst_sges)[i] = rte_malloc(NULL, dst_ptrs * sizeof(struct rte_dma_sge), 0); + if ((*dst_sges)[i] == NULL) { + printf("Error: dst_sges malloc failed.\n"); + return -1; + } + } + + sglen_src = buf_size / src_ptrs; + sglen_dst = buf_size / dst_ptrs; + for (i = 0; i < nr_buf; i++) { + for (j = 0; j < src_ptrs; j++) { + (*src_sges)[i][j].addr = rte_pktmbuf_iova((*srcs)[i]) + + sglen_src * j; + (*src_sges)[i][j].length = sglen_src; + } + (*src_sges)[i][j-1].length += buf_size % src_ptrs; + + for (j = 0; j < dst_ptrs; j++) { + (*dst_sges)[i][j].addr = rte_pktmbuf_iova((*dsts)[i]) + + sglen_dst * j; + (*dst_sges)[i][j].length = sglen_dst; + } + (*dst_sges)[i][j-1].length += buf_size % dst_ptrs; + } + } return 0; } int -mem_copy_benchmark(struct test_configure *cfg, bool is_dma) +mem_copy_benchmark(struct test_configure *cfg) { uint16_t i; uint32_t offset; unsigned int lcore_id = 0; + struct rte_dma_sge **src_sges = NULL, **dst_sges = NULL; struct rte_mbuf **srcs = NULL, **dsts = NULL; struct lcore_dma_map_t *ldm = &cfg->lcore_dma_map; unsigned int buf_size = cfg->buf_size.cur; @@ -389,10 +521,10 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) float bandwidth, bandwidth_total; int ret = 0; - if (setup_memory_env(cfg, &srcs, &dsts) < 0) + if (setup_memory_env(cfg, &srcs, &dsts, &src_sges, &dst_sges) < 0) goto out; - if (is_dma) + if (cfg->is_dma) if (config_dmadevs(cfg) < 0) goto out; @@ -412,7 +544,7 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) printf("lcore parameters malloc failure for lcore %d\n", lcore_id); break; } - if (is_dma) { + if (cfg->is_dma) { lcores[i]->dma_name = ldm->dma_names[i]; lcores[i]->dev_id = ldm->dma_ids[i]; lcores[i]->kick_batch = kick_batch; @@ -426,10 +558,23 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) lcores[i]->scenario_id = cfg->scenario_id; lcores[i]->lcore_id = lcore_id; - if (is_dma) - rte_eal_remote_launch(do_dma_mem_copy, (void *)(lcores[i]), lcore_id); - else + if (cfg->is_sg) { + lcores[i]->src_ptrs = cfg->src_ptrs; + lcores[i]->dst_ptrs = cfg->dst_ptrs; + lcores[i]->src_sges = src_sges + offset * cfg->src_ptrs; + lcores[i]->dst_sges = dst_sges + offset * cfg->dst_ptrs; + } + + if (cfg->is_dma) { + if (!cfg->is_sg) + rte_eal_remote_launch(do_dma_plain_mem_copy, (void *)(lcores[i]), + lcore_id); + else + rte_eal_remote_launch(do_dma_sg_mem_copy, (void *)(lcores[i]), + lcore_id); + } else { rte_eal_remote_launch(do_cpu_mem_copy, (void *)(lcores[i]), lcore_id); + } } while (1) { @@ -478,10 +623,8 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) calc_result(buf_size, nr_buf, nb_workers, test_secs, lcores[i]->worker_info.test_cpl, &memory, &avg_cycles, &bandwidth, &mops); - output_result(cfg->scenario_id, lcores[i]->lcore_id, - lcores[i]->dma_name, cfg->ring_size.cur, kick_batch, - avg_cycles, buf_size, nr_buf / nb_workers, memory, - bandwidth, mops, is_dma); + output_result(cfg, lcores[i], kick_batch, avg_cycles, buf_size, + nr_buf / nb_workers, memory, bandwidth, mops); mops_total += mops; bandwidth_total += bandwidth; avg_cycles_total += avg_cycles; @@ -510,13 +653,24 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma) rte_mempool_free(dst_pool); dst_pool = NULL; + /* free sges for mbufs */ + for (i = 0; i < nr_buf; i++) { + rte_free(src_sges[i]); + rte_free(dst_sges[i]); + } + + rte_free(src_sges); + src_sges = NULL; + + rte_free(dst_sges); + dst_sges = NULL; /* free the worker parameters */ for (i = 0; i < nb_workers; i++) { rte_free(lcores[i]); lcores[i] = NULL; } - if (is_dma) { + if (cfg->is_dma) { for (i = 0; i < nb_workers; i++) { printf("Stopping dmadev %d\n", ldm->dma_ids[i]); rte_dma_stop(ldm->dma_ids[i]); diff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini index b550f4b23f..f1b268a384 100644 --- a/app/test-dma-perf/config.ini +++ b/app/test-dma-perf/config.ini @@ -9,6 +9,8 @@ ; "buf_size" denotes the memory size of a single operation. ; "dma_ring_size" denotes the dma ring buffer size. It should be must be a power of two, and between ; 64 and 4096. +; "dma_ptrs_src" denotes number of source segments. +; "dma_ptrs_dst" denotes number of destination segments. ; "kick_batch" denotes the dma operation batch size, and should be greater than 1 normally. ; The format for variables is variable=first,last,increment,ADD|MUL. @@ -50,6 +52,21 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 eal_args=--in-memory --file-prefix=test [case2] +type=DMA_MEM_COPY +mem_size=10 +buf_size=64,8192,2,MUL +dma_ring_size=1024 +dma_ptrs_src=4 +dma_ptrs_dst=1 +kick_batch=32 +src_numa_node=0 +dst_numa_node=0 +cache_flush=0 +test_seconds=2 +lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3 +eal_args=--in-memory --file-prefix=test + +[case3] type=CPU_MEM_COPY mem_size=10 buf_size=64,8192,2,MUL diff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c index bbba06ec1b..a4958d7a0f 100644 --- a/app/test-dma-perf/main.c +++ b/app/test-dma-perf/main.c @@ -93,10 +93,8 @@ run_test_case(struct test_configure *case_cfg) switch (case_cfg->test_type) { case TEST_TYPE_DMA_MEM_COPY: - ret = mem_copy_benchmark(case_cfg, true); - break; case TEST_TYPE_CPU_MEM_COPY: - ret = mem_copy_benchmark(case_cfg, false); + ret = mem_copy_benchmark(case_cfg); break; default: printf("Unknown test type. %s\n", case_cfg->test_type_str); @@ -325,7 +323,8 @@ load_configs(const char *path) char section_name[CFG_NAME_LEN]; const char *case_type; const char *lcore_dma; - const char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str; + const char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str, + *src_ptrs_str, *dst_ptrs_str; int args_nr, nb_vp; bool is_dma; @@ -361,12 +360,14 @@ load_configs(const char *path) test_case->test_type = TEST_TYPE_CPU_MEM_COPY; test_case->test_type_str = CPU_MEM_COPY; is_dma = false; + } else { printf("Error: Wrong test case type %s in case%d.\n", case_type, i + 1); test_case->is_valid = false; continue; } + test_case->is_dma = is_dma; test_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile, section_name, "src_numa_node")); test_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile, @@ -401,6 +402,32 @@ load_configs(const char *path) } else if (args_nr == 4) nb_vp++; + src_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name, + "dma_ptrs_src"); + if (src_ptrs_str != NULL) { + test_case->src_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile, + section_name, "dma_ptrs_src")); + } + + dst_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name, + "dma_ptrs_dst"); + if (dst_ptrs_str != NULL) { + test_case->dst_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile, + section_name, "dma_ptrs_dst")); + } + + if ((src_ptrs_str != NULL && dst_ptrs_str == NULL) || + (src_ptrs_str == NULL && dst_ptrs_str != NULL)) { + printf("parse dma_ptrs_src, dma_ptrs_dst error in case %d.\n", + i + 1); + test_case->is_valid = false; + continue; + } else if (src_ptrs_str != NULL && dst_ptrs_str != NULL) { + test_case->is_sg = true; + } else { + test_case->is_sg = false; + } + kick_batch_str = rte_cfgfile_get_entry(cfgfile, section_name, "kick_batch"); args_nr = parse_entry(kick_batch_str, &test_case->kick_batch); if (args_nr < 0) { diff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h index 57a9f71a06..9a3a32a018 100644 --- a/app/test-dma-perf/main.h +++ b/app/test-dma-perf/main.h @@ -47,11 +47,14 @@ struct test_configure { uint16_t dst_numa_node; uint16_t opcode; bool is_dma; + bool is_sg; struct lcore_dma_map_t lcore_dma_map; struct test_configure_entry mem_size; struct test_configure_entry buf_size; struct test_configure_entry ring_size; struct test_configure_entry kick_batch; + uint8_t src_ptrs; + uint8_t dst_ptrs; uint8_t cache_flush; uint32_t nr_buf; uint16_t test_secs; @@ -59,6 +62,6 @@ struct test_configure { uint8_t scenario_id; }; -int mem_copy_benchmark(struct test_configure *cfg, bool is_dma); +int mem_copy_benchmark(struct test_configure *cfg); #endif /* _MAIN_H_ */