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GET /api/patches/126539/?format=api
{ "id": 126539, "url": "http://patches.dpdk.org/api/patches/126539/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230426102259.205992-7-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230426102259.205992-7-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230426102259.205992-7-wenjing.qiao@intel.com", "date": "2023-04-26T10:22:50", "name": "[v3,06/15] common/idpf/base: modify SSO/LSO and ITR fields", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fc3f49d77c6a4ed1ea1dfb53238bf5036207a523", "submitter": { "id": 2680, "url": "http://patches.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230426102259.205992-7-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 27874, "url": "http://patches.dpdk.org/api/series/27874/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=27874", "date": "2023-04-26T10:22:44", "name": "update idpf base code", "version": 3, "mbox": "http://patches.dpdk.org/series/27874/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/126539/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/126539/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0A4AA42A02;\n\tWed, 26 Apr 2023 12:28:39 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9CE8042D46;\n\tWed, 26 Apr 2023 12:28:08 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 3D50F42D3D\n for <dev@dpdk.org>; Wed, 26 Apr 2023 12:28:04 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 03:28:03 -0700", "from dpdk-wenjing-01.sh.intel.com ([10.67.118.239])\n by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:01 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682504884; x=1714040884;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=GhO87oGG11ZM1yvafwTCi0+S6V7GZh/8I+81IGbEIfg=;\n b=kJRLRB2yGqTJOawhg8er9Ib6gz1z9jJhvtkPQFaOZ7aSU9uatAxE6O4G\n 6wZ7XQ9ek9S24YoCQzPrhoaOk4eNKEJuUoDVI5F+UEdZJtkpTeAnLPCm6\n 0Yej3iLdxvCY/j97vBFJeuV+kvy818pFck8ap4MnwprMiHdbTmRZxbq2K\n CqHojoIW7qgF7Qh87ZoqJALMu63IZxu0cXwQ1DuTKRLAo0LItaxoCmXqF\n 1lae0+1KwO5pFav3S0V7u69Ps0YgO7ndkpd7Pz6hXSrGLx3+afJi1s1tN\n YZFo2HWMCn68mUHr7eV/JaL1J960+i1nTCLjc6ncYfUg6zsXbqh2Cy5av g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10691\"; a=\"327391517\"", "E=Sophos;i=\"5.99,227,1677571200\"; d=\"scan'208\";a=\"327391517\"", "E=McAfee;i=\"6600,9927,10691\"; a=\"1023552695\"", "E=Sophos;i=\"5.99,227,1677571200\"; d=\"scan'208\";a=\"1023552695\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com,\n Wenjing Qiao <wenjing.qiao@intel.com>,\n Pavan Kumar Linga <pavan.kumar.linga@intel.com>", "Subject": "[PATCH v3 06/15] common/idpf/base: modify SSO/LSO and ITR fields", "Date": "Wed, 26 Apr 2023 06:22:50 -0400", "Message-Id": "<20230426102259.205992-7-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230426102259.205992-1-wenjing.qiao@intel.com>", "References": "<20230421084043.135503-2-wenjing.qiao@intel.com>\n <20230426102259.205992-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "- Driver assumes minimum packet length for sso as 17 bytes\nbut it should be a negotiated value from CP.\n- Similarly, the number of header buffers for lso that are\nsupported by the device should also be a negotiated value.\n\nAdd min_sso_packet_len, max_hdr_buf_per_lso to address the\nabove.\n\nAlso, the existing 'itrn_reg_spacing' should be used for\nspacing between ITRn registers of 2 consecutive vectors and\nadd a new spacing field to get the spacing between ITR\nregisters of the same vector.\n\n- ITR_IDX 2 is not used in the current code. Bring it back\nif there exists any use case in the future.\n- NO_ITR is not really a register index and it is used only\nin the IDPF base code, so virtchnl support is not required for\nthat\n- itr_idx_map is also not used as by default driver assumes\nat the minimum 2 ITRs are supported by the device. If any\nadditional ITRs are also supported, then those should be\nnegotiated.\n\nRemove all the above said fields and mark them as reserved.\n\nSigned-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com>\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/common/idpf/base/virtchnl2.h | 25 ++++++++++++++-----------\n 1 file changed, 14 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h\nindex 32d8fe8c06..edf3f200b3 100644\n--- a/drivers/common/idpf/base/virtchnl2.h\n+++ b/drivers/common/idpf/base/virtchnl2.h\n@@ -289,8 +289,6 @@\n */\n #define VIRTCHNL2_ITR_IDX_0\t\t\t0\n #define VIRTCHNL2_ITR_IDX_1\t\t\t1\n-#define VIRTCHNL2_ITR_IDX_2\t\t\t2\n-#define VIRTCHNL2_ITR_IDX_NO_ITR\t\t3\n \n /* VIRTCHNL2_VECTOR_LIMITS\n * Since PF/VF messages are limited by __le16 size, precalculate the maximum\n@@ -510,9 +508,7 @@ struct virtchnl2_get_capabilities {\n \t */\n \tu8 max_sg_bufs_per_tx_pkt;\n \n-\t/* see VIRTCHNL2_ITR_IDX definition */\n-\tu8 itr_idx_map;\n-\n+\tu8 reserved1;\n \t__le16 pad1;\n \n \t/* version of Control Plane that is running */\n@@ -521,7 +517,12 @@ struct virtchnl2_get_capabilities {\n \t/* see VIRTCHNL2_DEVICE_TYPE definitions */\n \t__le32 device_type;\n \n-\tu8 reserved[12];\n+\t/* min packet length supported by device for single segment offload */\n+\tu8 min_sso_packet_len;\n+\t/* max number of header buffers that can be used for an LSO */\n+\tu8 max_hdr_buf_per_lso;\n+\n+\tu8 reserved[10];\n };\n \n VIRTCHNL2_CHECK_STRUCT_LEN(80, virtchnl2_get_capabilities);\n@@ -789,15 +790,17 @@ struct virtchnl2_vector_chunk {\n \t * interrupt indices without modifying the state of the interrupt.\n \t */\n \t__le32 dynctl_reg_start;\n-\t/* register spacing to find the next dynctl and itrn register offset\n-\t * from the provided dynctl_reg_start and itrn_reg_start respectively\n-\t */\n+\t/* register spacing between dynctl registers of 2 consecutive vectors */\n \t__le32 dynctl_reg_spacing;\n \n \t__le32 itrn_reg_start;\n-\t/* register spacing to find the individual itrn register where n=0..2 */\n+\t/* register spacing between itrn registers of 2 consecutive vectors */\n \t__le32 itrn_reg_spacing;\n-\tu8 reserved[8];\n+\t/* register spacing between itrn registers of the same vector\n+\t * where n=0..2\n+\t */\n+\t__le32 itrn_index_spacing;\n+\tu8 reserved[4];\n };\n \n VIRTCHNL2_CHECK_STRUCT_LEN(32, virtchnl2_vector_chunk);\n", "prefixes": [ "v3", "06/15" ] }