From patchwork Wed Apr 26 10:22:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126533 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B4E242A02; Wed, 26 Apr 2023 12:27:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F0A9D427F2; Wed, 26 Apr 2023 12:27:57 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 0F8BD427F2 for ; Wed, 26 Apr 2023 12:27:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504875; x=1714040875; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XdbiX6mn7EOi3CHvhaJX8B1GB1qVqtcWbOA680U3Pvk=; b=TNuxFGMuwHWgmpacva28AomQW4MVPMBRaA7nLb2UpMMttNZkDUOK+N3f EUlPK15kCwRKsXq0yWnULcaH27e+cNW8xVlpZtxG/torj7sj994g1nKSi yI9QcSzI31NSW9UiEqjFLhwKWDe9Om96khUNRHRgQTMpOVJTelUXO3Sj2 0/jriFfz11YThyT90N2zdUoJjMVtP8+YEULQ3TmplcPAcUmL0F7mc5id5 FBR7ry8KNkI4L4G7Vu07vbiU2sKGT3C3DfcJXI2AM/JyiUEna0Kg8PUAo 2OSO4tEdhuui/UTNSkqmIWOOmQAj/xeiJwu/jyJ3bUA4RTXEyWl0RwhOl Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391467" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391467" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:27:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552618" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552618" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:50 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao Subject: [PATCH v3 01/15] common/idpf/base: remove virtchnl related base code Date: Wed, 26 Apr 2023 06:22:45 -0400 Message-Id: <20230426102259.205992-2-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Since virtchnl related base code of iavf and idpf has the same sourse, so remove virtual related base code of idpf. Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- drivers/common/idpf/base/virtchnl.h | 2866 ----------------- .../common/idpf/base/virtchnl_inline_ipsec.h | 567 ---- drivers/common/idpf/meson.build | 2 + 5 files changed, 4 insertions(+), 3435 deletions(-) delete mode 100644 drivers/common/idpf/base/virtchnl.h delete mode 100644 drivers/common/idpf/base/virtchnl_inline_ipsec.h diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 3a9fdb1878..41e0d05623 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -4,7 +4,7 @@ #include "idpf_type.h" #include "idpf_prototype.h" -#include "virtchnl.h" +#include /** diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index 529b62212d..3090f4cc2a 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -15,7 +15,7 @@ #include "idpf_lan_pf_regs.h" #include "idpf_lan_vf_regs.h" #include "idpf_lan_txrx.h" -#include "virtchnl.h" +#include #define APF diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h deleted file mode 100644 index ea798e3971..0000000000 --- a/drivers/common/idpf/base/virtchnl.h +++ /dev/null @@ -1,2866 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation - */ - -#ifndef _VIRTCHNL_H_ -#define _VIRTCHNL_H_ - -/* Description: - * This header file describes the Virtual Function (VF) - Physical Function - * (PF) communication protocol used by the drivers for all devices starting - * from our 40G product line - * - * Admin queue buffer usage: - * desc->opcode is always aqc_opc_send_msg_to_pf - * flags, retval, datalen, and data addr are all used normally. - * The Firmware copies the cookie fields when sending messages between the - * PF and VF, but uses all other fields internally. Due to this limitation, - * we must send all messages as "indirect", i.e. using an external buffer. - * - * All the VSI indexes are relative to the VF. Each VF can have maximum of - * three VSIs. All the queue indexes are relative to the VSI. Each VF can - * have a maximum of sixteen queues for all of its VSIs. - * - * The PF is required to return a status code in v_retval for all messages - * except RESET_VF, which does not require any response. The returned value - * is of virtchnl_status_code type, defined here. - * - * In general, VF driver initialization should roughly follow the order of - * these opcodes. The VF driver must first validate the API version of the - * PF driver, then request a reset, then get resources, then configure - * queues and interrupts. After these operations are complete, the VF - * driver may start its queues, optionally add MAC and VLAN filters, and - * process traffic. - */ - -/* START GENERIC DEFINES - * Need to ensure the following enums and defines hold the same meaning and - * value in current and future projects - */ - -#define VIRTCHNL_ETH_LENGTH_OF_ADDRESS 6 - -/* These macros are used to generate compilation errors if a structure/union - * is not exactly the correct length. It gives a divide by zero error if the - * structure/union is not of the correct size, otherwise it creates an enum - * that is never used. - */ -#define VIRTCHNL_CHECK_STRUCT_LEN(n, X) enum virtchnl_static_assert_enum_##X \ - { virtchnl_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } -#define VIRTCHNL_CHECK_UNION_LEN(n, X) enum virtchnl_static_asset_enum_##X \ - { virtchnl_static_assert_##X = (n)/((sizeof(union X) == (n)) ? 1 : 0) } - - -/* Error Codes - * Note that many older versions of various iAVF drivers convert the reported - * status code directly into an iavf_status enumeration. For this reason, it - * is important that the values of these enumerations line up. - */ -enum virtchnl_status_code { - VIRTCHNL_STATUS_SUCCESS = 0, - VIRTCHNL_STATUS_ERR_PARAM = -5, - VIRTCHNL_STATUS_ERR_NO_MEMORY = -18, - VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH = -38, - VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR = -39, - VIRTCHNL_STATUS_ERR_INVALID_VF_ID = -40, - VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR = -53, - VIRTCHNL_STATUS_ERR_NOT_SUPPORTED = -64, -}; - -/* Backward compatibility */ -#define VIRTCHNL_ERR_PARAM VIRTCHNL_STATUS_ERR_PARAM -#define VIRTCHNL_STATUS_NOT_SUPPORTED VIRTCHNL_STATUS_ERR_NOT_SUPPORTED - -#define VIRTCHNL_LINK_SPEED_2_5GB_SHIFT 0x0 -#define VIRTCHNL_LINK_SPEED_100MB_SHIFT 0x1 -#define VIRTCHNL_LINK_SPEED_1000MB_SHIFT 0x2 -#define VIRTCHNL_LINK_SPEED_10GB_SHIFT 0x3 -#define VIRTCHNL_LINK_SPEED_40GB_SHIFT 0x4 -#define VIRTCHNL_LINK_SPEED_20GB_SHIFT 0x5 -#define VIRTCHNL_LINK_SPEED_25GB_SHIFT 0x6 -#define VIRTCHNL_LINK_SPEED_5GB_SHIFT 0x7 - -enum virtchnl_link_speed { - VIRTCHNL_LINK_SPEED_UNKNOWN = 0, - VIRTCHNL_LINK_SPEED_100MB = BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT), - VIRTCHNL_LINK_SPEED_1GB = BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT), - VIRTCHNL_LINK_SPEED_10GB = BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT), - VIRTCHNL_LINK_SPEED_40GB = BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT), - VIRTCHNL_LINK_SPEED_20GB = BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT), - VIRTCHNL_LINK_SPEED_25GB = BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT), - VIRTCHNL_LINK_SPEED_2_5GB = BIT(VIRTCHNL_LINK_SPEED_2_5GB_SHIFT), - VIRTCHNL_LINK_SPEED_5GB = BIT(VIRTCHNL_LINK_SPEED_5GB_SHIFT), -}; - -/* for hsplit_0 field of Rx HMC context */ -/* deprecated with AVF 1.0 */ -enum virtchnl_rx_hsplit { - VIRTCHNL_RX_HSPLIT_NO_SPLIT = 0, - VIRTCHNL_RX_HSPLIT_SPLIT_L2 = 1, - VIRTCHNL_RX_HSPLIT_SPLIT_IP = 2, - VIRTCHNL_RX_HSPLIT_SPLIT_TCP_UDP = 4, - VIRTCHNL_RX_HSPLIT_SPLIT_SCTP = 8, -}; - -enum virtchnl_bw_limit_type { - VIRTCHNL_BW_SHAPER = 0, -}; -/* END GENERIC DEFINES */ - -/* Opcodes for VF-PF communication. These are placed in the v_opcode field - * of the virtchnl_msg structure. - */ -enum virtchnl_ops { -/* The PF sends status change events to VFs using - * the VIRTCHNL_OP_EVENT opcode. - * VFs send requests to the PF using the other ops. - * Use of "advanced opcode" features must be negotiated as part of capabilities - * exchange and are not considered part of base mode feature set. - * - */ - VIRTCHNL_OP_UNKNOWN = 0, - VIRTCHNL_OP_VERSION = 1, /* must ALWAYS be 1 */ - VIRTCHNL_OP_RESET_VF = 2, - VIRTCHNL_OP_GET_VF_RESOURCES = 3, - VIRTCHNL_OP_CONFIG_TX_QUEUE = 4, - VIRTCHNL_OP_CONFIG_RX_QUEUE = 5, - VIRTCHNL_OP_CONFIG_VSI_QUEUES = 6, - VIRTCHNL_OP_CONFIG_IRQ_MAP = 7, - VIRTCHNL_OP_ENABLE_QUEUES = 8, - VIRTCHNL_OP_DISABLE_QUEUES = 9, - VIRTCHNL_OP_ADD_ETH_ADDR = 10, - VIRTCHNL_OP_DEL_ETH_ADDR = 11, - VIRTCHNL_OP_ADD_VLAN = 12, - VIRTCHNL_OP_DEL_VLAN = 13, - VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE = 14, - VIRTCHNL_OP_GET_STATS = 15, - VIRTCHNL_OP_RSVD = 16, - VIRTCHNL_OP_EVENT = 17, /* must ALWAYS be 17 */ - /* opcode 19 is reserved */ - /* opcodes 20, 21, and 22 are reserved */ - VIRTCHNL_OP_CONFIG_RSS_KEY = 23, - VIRTCHNL_OP_CONFIG_RSS_LUT = 24, - VIRTCHNL_OP_GET_RSS_HENA_CAPS = 25, - VIRTCHNL_OP_SET_RSS_HENA = 26, - VIRTCHNL_OP_ENABLE_VLAN_STRIPPING = 27, - VIRTCHNL_OP_DISABLE_VLAN_STRIPPING = 28, - VIRTCHNL_OP_REQUEST_QUEUES = 29, - VIRTCHNL_OP_ENABLE_CHANNELS = 30, - VIRTCHNL_OP_DISABLE_CHANNELS = 31, - VIRTCHNL_OP_ADD_CLOUD_FILTER = 32, - VIRTCHNL_OP_DEL_CLOUD_FILTER = 33, - /* opcode 34 is reserved */ - /* opcodes 38, 39, 40, 41, 42 and 43 are reserved */ - /* opcode 44 is reserved */ - VIRTCHNL_OP_ADD_RSS_CFG = 45, - VIRTCHNL_OP_DEL_RSS_CFG = 46, - VIRTCHNL_OP_ADD_FDIR_FILTER = 47, - VIRTCHNL_OP_DEL_FDIR_FILTER = 48, - VIRTCHNL_OP_GET_MAX_RSS_QREGION = 50, - VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS = 51, - VIRTCHNL_OP_ADD_VLAN_V2 = 52, - VIRTCHNL_OP_DEL_VLAN_V2 = 53, - VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 = 54, - VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2 = 55, - VIRTCHNL_OP_ENABLE_VLAN_INSERTION_V2 = 56, - VIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2 = 57, - VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2 = 58, - VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2 = 59, - VIRTCHNL_OP_1588_PTP_GET_CAPS = 60, - VIRTCHNL_OP_1588_PTP_GET_TIME = 61, - VIRTCHNL_OP_1588_PTP_SET_TIME = 62, - VIRTCHNL_OP_1588_PTP_ADJ_TIME = 63, - VIRTCHNL_OP_1588_PTP_ADJ_FREQ = 64, - VIRTCHNL_OP_1588_PTP_TX_TIMESTAMP = 65, - VIRTCHNL_OP_GET_QOS_CAPS = 66, - VIRTCHNL_OP_CONFIG_QUEUE_TC_MAP = 67, - VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS = 68, - VIRTCHNL_OP_1588_PTP_SET_PIN_CFG = 69, - VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP = 70, - VIRTCHNL_OP_ENABLE_QUEUES_V2 = 107, - VIRTCHNL_OP_DISABLE_QUEUES_V2 = 108, - VIRTCHNL_OP_MAP_QUEUE_VECTOR = 111, - VIRTCHNL_OP_CONFIG_QUEUE_BW = 112, - VIRTCHNL_OP_CONFIG_QUANTA = 113, - VIRTCHNL_OP_MAX, -}; - -static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode) -{ - switch (v_opcode) { - case VIRTCHNL_OP_UNKNOWN: - return "VIRTCHNL_OP_UNKNOWN"; - case VIRTCHNL_OP_VERSION: - return "VIRTCHNL_OP_VERSION"; - case VIRTCHNL_OP_RESET_VF: - return "VIRTCHNL_OP_RESET_VF"; - case VIRTCHNL_OP_GET_VF_RESOURCES: - return "VIRTCHNL_OP_GET_VF_RESOURCES"; - case VIRTCHNL_OP_CONFIG_TX_QUEUE: - return "VIRTCHNL_OP_CONFIG_TX_QUEUE"; - case VIRTCHNL_OP_CONFIG_RX_QUEUE: - return "VIRTCHNL_OP_CONFIG_RX_QUEUE"; - case VIRTCHNL_OP_CONFIG_VSI_QUEUES: - return "VIRTCHNL_OP_CONFIG_VSI_QUEUES"; - case VIRTCHNL_OP_CONFIG_IRQ_MAP: - return "VIRTCHNL_OP_CONFIG_IRQ_MAP"; - case VIRTCHNL_OP_ENABLE_QUEUES: - return "VIRTCHNL_OP_ENABLE_QUEUES"; - case VIRTCHNL_OP_DISABLE_QUEUES: - return "VIRTCHNL_OP_DISABLE_QUEUES"; - case VIRTCHNL_OP_ADD_ETH_ADDR: - return "VIRTCHNL_OP_ADD_ETH_ADDR"; - case VIRTCHNL_OP_DEL_ETH_ADDR: - return "VIRTCHNL_OP_DEL_ETH_ADDR"; - case VIRTCHNL_OP_ADD_VLAN: - return "VIRTCHNL_OP_ADD_VLAN"; - case VIRTCHNL_OP_DEL_VLAN: - return "VIRTCHNL_OP_DEL_VLAN"; - case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: - return "VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE"; - case VIRTCHNL_OP_GET_STATS: - return "VIRTCHNL_OP_GET_STATS"; - case VIRTCHNL_OP_RSVD: - return "VIRTCHNL_OP_RSVD"; - case VIRTCHNL_OP_EVENT: - return "VIRTCHNL_OP_EVENT"; - case VIRTCHNL_OP_CONFIG_RSS_KEY: - return "VIRTCHNL_OP_CONFIG_RSS_KEY"; - case VIRTCHNL_OP_CONFIG_RSS_LUT: - return "VIRTCHNL_OP_CONFIG_RSS_LUT"; - case VIRTCHNL_OP_GET_RSS_HENA_CAPS: - return "VIRTCHNL_OP_GET_RSS_HENA_CAPS"; - case VIRTCHNL_OP_SET_RSS_HENA: - return "VIRTCHNL_OP_SET_RSS_HENA"; - case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING: - return "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING"; - case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING: - return "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING"; - case VIRTCHNL_OP_REQUEST_QUEUES: - return "VIRTCHNL_OP_REQUEST_QUEUES"; - case VIRTCHNL_OP_ENABLE_CHANNELS: - return "VIRTCHNL_OP_ENABLE_CHANNELS"; - case VIRTCHNL_OP_DISABLE_CHANNELS: - return "VIRTCHNL_OP_DISABLE_CHANNELS"; - case VIRTCHNL_OP_ADD_CLOUD_FILTER: - return "VIRTCHNL_OP_ADD_CLOUD_FILTER"; - case VIRTCHNL_OP_DEL_CLOUD_FILTER: - return "VIRTCHNL_OP_DEL_CLOUD_FILTER"; - case VIRTCHNL_OP_ADD_RSS_CFG: - return "VIRTCHNL_OP_ADD_RSS_CFG"; - case VIRTCHNL_OP_DEL_RSS_CFG: - return "VIRTCHNL_OP_DEL_RSS_CFG"; - case VIRTCHNL_OP_ADD_FDIR_FILTER: - return "VIRTCHNL_OP_ADD_FDIR_FILTER"; - case VIRTCHNL_OP_DEL_FDIR_FILTER: - return "VIRTCHNL_OP_DEL_FDIR_FILTER"; - case VIRTCHNL_OP_GET_MAX_RSS_QREGION: - return "VIRTCHNL_OP_GET_MAX_RSS_QREGION"; - case VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS: - return "VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS"; - case VIRTCHNL_OP_ADD_VLAN_V2: - return "VIRTCHNL_OP_ADD_VLAN_V2"; - case VIRTCHNL_OP_DEL_VLAN_V2: - return "VIRTCHNL_OP_DEL_VLAN_V2"; - case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2: - return "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2"; - case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2: - return "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2"; - case VIRTCHNL_OP_ENABLE_VLAN_INSERTION_V2: - return "VIRTCHNL_OP_ENABLE_VLAN_INSERTION_V2"; - case VIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2: - return "VIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2"; - case VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2: - return "VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2"; - case VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2: - return "VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2"; - case VIRTCHNL_OP_1588_PTP_GET_CAPS: - return "VIRTCHNL_OP_1588_PTP_GET_CAPS"; - case VIRTCHNL_OP_1588_PTP_GET_TIME: - return "VIRTCHNL_OP_1588_PTP_GET_TIME"; - case VIRTCHNL_OP_1588_PTP_SET_TIME: - return "VIRTCHNL_OP_1588_PTP_SET_TIME"; - case VIRTCHNL_OP_1588_PTP_ADJ_TIME: - return "VIRTCHNL_OP_1588_PTP_ADJ_TIME"; - case VIRTCHNL_OP_1588_PTP_ADJ_FREQ: - return "VIRTCHNL_OP_1588_PTP_ADJ_FREQ"; - case VIRTCHNL_OP_1588_PTP_TX_TIMESTAMP: - return "VIRTCHNL_OP_1588_PTP_TX_TIMESTAMP"; - case VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS: - return "VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS"; - case VIRTCHNL_OP_1588_PTP_SET_PIN_CFG: - return "VIRTCHNL_OP_1588_PTP_SET_PIN_CFG"; - case VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP: - return "VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP"; - case VIRTCHNL_OP_ENABLE_QUEUES_V2: - return "VIRTCHNL_OP_ENABLE_QUEUES_V2"; - case VIRTCHNL_OP_DISABLE_QUEUES_V2: - return "VIRTCHNL_OP_DISABLE_QUEUES_V2"; - case VIRTCHNL_OP_MAP_QUEUE_VECTOR: - return "VIRTCHNL_OP_MAP_QUEUE_VECTOR"; - case VIRTCHNL_OP_MAX: - return "VIRTCHNL_OP_MAX"; - default: - return "Unsupported (update virtchnl.h)"; - } -} - -static inline const char *virtchnl_stat_str(enum virtchnl_status_code v_status) -{ - switch (v_status) { - case VIRTCHNL_STATUS_SUCCESS: - return "VIRTCHNL_STATUS_SUCCESS"; - case VIRTCHNL_STATUS_ERR_PARAM: - return "VIRTCHNL_STATUS_ERR_PARAM"; - case VIRTCHNL_STATUS_ERR_NO_MEMORY: - return "VIRTCHNL_STATUS_ERR_NO_MEMORY"; - case VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH: - return "VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH"; - case VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR: - return "VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR"; - case VIRTCHNL_STATUS_ERR_INVALID_VF_ID: - return "VIRTCHNL_STATUS_ERR_INVALID_VF_ID"; - case VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR: - return "VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR"; - case VIRTCHNL_STATUS_ERR_NOT_SUPPORTED: - return "VIRTCHNL_STATUS_ERR_NOT_SUPPORTED"; - default: - return "Unknown status code (update virtchnl.h)"; - } -} - -/* Virtual channel message descriptor. This overlays the admin queue - * descriptor. All other data is passed in external buffers. - */ - -struct virtchnl_msg { - u8 pad[8]; /* AQ flags/opcode/len/retval fields */ - - /* avoid confusion with desc->opcode */ - enum virtchnl_ops v_opcode; - - /* ditto for desc->retval */ - enum virtchnl_status_code v_retval; - u32 vfid; /* used by PF when sending to VF */ -}; - -VIRTCHNL_CHECK_STRUCT_LEN(20, virtchnl_msg); - -/* Message descriptions and data structures. */ - -/* VIRTCHNL_OP_VERSION - * VF posts its version number to the PF. PF responds with its version number - * in the same format, along with a return code. - * Reply from PF has its major/minor versions also in param0 and param1. - * If there is a major version mismatch, then the VF cannot operate. - * If there is a minor version mismatch, then the VF can operate but should - * add a warning to the system log. - * - * This enum element MUST always be specified as == 1, regardless of other - * changes in the API. The PF must always respond to this message without - * error regardless of version mismatch. - */ -#define VIRTCHNL_VERSION_MAJOR 1 -#define VIRTCHNL_VERSION_MINOR 1 -#define VIRTCHNL_VERSION_MAJOR_2 2 -#define VIRTCHNL_VERSION_MINOR_0 0 -#define VIRTCHNL_VERSION_MINOR_NO_VF_CAPS 0 - -struct virtchnl_version_info { - u32 major; - u32 minor; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_version_info); - -#define VF_IS_V10(_ver) (((_ver)->major == 1) && ((_ver)->minor == 0)) -#define VF_IS_V11(_ver) (((_ver)->major == 1) && ((_ver)->minor == 1)) -#define VF_IS_V20(_ver) (((_ver)->major == 2) && ((_ver)->minor == 0)) - -/* VIRTCHNL_OP_RESET_VF - * VF sends this request to PF with no parameters - * PF does NOT respond! VF driver must delay then poll VFGEN_RSTAT register - * until reset completion is indicated. The admin queue must be reinitialized - * after this operation. - * - * When reset is complete, PF must ensure that all queues in all VSIs associated - * with the VF are stopped, all queue configurations in the HMC are set to 0, - * and all MAC and VLAN filters (except the default MAC address) on all VSIs - * are cleared. - */ - -/* VSI types that use VIRTCHNL interface for VF-PF communication. VSI_SRIOV - * vsi_type should always be 6 for backward compatibility. Add other fields - * as needed. - */ -enum virtchnl_vsi_type { - VIRTCHNL_VSI_TYPE_INVALID = 0, - VIRTCHNL_VSI_SRIOV = 6, -}; - -/* VIRTCHNL_OP_GET_VF_RESOURCES - * Version 1.0 VF sends this request to PF with no parameters - * Version 1.1 VF sends this request to PF with u32 bitmap of its capabilities - * PF responds with an indirect message containing - * virtchnl_vf_resource and one or more - * virtchnl_vsi_resource structures. - */ - -struct virtchnl_vsi_resource { - u16 vsi_id; - u16 num_queue_pairs; - - /* see enum virtchnl_vsi_type */ - s32 vsi_type; - u16 qset_handle; - u8 default_mac_addr[VIRTCHNL_ETH_LENGTH_OF_ADDRESS]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); - -/* VF capability flags - * VIRTCHNL_VF_OFFLOAD_L2 flag is inclusive of base mode L2 offloads including - * TX/RX Checksum offloading and TSO for non-tunnelled packets. - */ -#define VIRTCHNL_VF_OFFLOAD_L2 BIT(0) -#define VIRTCHNL_VF_OFFLOAD_IWARP BIT(1) -#define VIRTCHNL_VF_CAP_RDMA VIRTCHNL_VF_OFFLOAD_IWARP -#define VIRTCHNL_VF_OFFLOAD_RSS_AQ BIT(3) -#define VIRTCHNL_VF_OFFLOAD_RSS_REG BIT(4) -#define VIRTCHNL_VF_OFFLOAD_WB_ON_ITR BIT(5) -#define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES BIT(6) -/* used to negotiate communicating link speeds in Mbps */ -#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED BIT(7) - /* BIT(8) is reserved */ -#define VIRTCHNL_VF_LARGE_NUM_QPAIRS BIT(9) -#define VIRTCHNL_VF_OFFLOAD_CRC BIT(10) -#define VIRTCHNL_VF_OFFLOAD_VLAN_V2 BIT(15) -#define VIRTCHNL_VF_OFFLOAD_VLAN BIT(16) -#define VIRTCHNL_VF_OFFLOAD_RX_POLLING BIT(17) -#define VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2 BIT(18) -#define VIRTCHNL_VF_OFFLOAD_RSS_PF BIT(19) -#define VIRTCHNL_VF_OFFLOAD_ENCAP BIT(20) -#define VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM BIT(21) -#define VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM BIT(22) -#define VIRTCHNL_VF_OFFLOAD_ADQ BIT(23) -#define VIRTCHNL_VF_OFFLOAD_ADQ_V2 BIT(24) -#define VIRTCHNL_VF_OFFLOAD_USO BIT(25) - /* BIT(26) is reserved */ -#define VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF BIT(27) -#define VIRTCHNL_VF_OFFLOAD_FDIR_PF BIT(28) -#define VIRTCHNL_VF_OFFLOAD_QOS BIT(29) - /* BIT(30) is reserved */ -#define VIRTCHNL_VF_CAP_PTP BIT(31) - -#define VF_BASE_MODE_OFFLOADS (VIRTCHNL_VF_OFFLOAD_L2 | \ - VIRTCHNL_VF_OFFLOAD_VLAN | \ - VIRTCHNL_VF_OFFLOAD_RSS_PF) - -struct virtchnl_vf_resource { - u16 num_vsis; - u16 num_queue_pairs; - u16 max_vectors; - u16 max_mtu; - - u32 vf_cap_flags; - u32 rss_key_size; - u32 rss_lut_size; - - struct virtchnl_vsi_resource vsi_res[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(36, virtchnl_vf_resource); - -/* VIRTCHNL_OP_CONFIG_TX_QUEUE - * VF sends this message to set up parameters for one TX queue. - * External data buffer contains one instance of virtchnl_txq_info. - * PF configures requested queue and returns a status code. - */ - -/* Tx queue config info */ -struct virtchnl_txq_info { - u16 vsi_id; - u16 queue_id; - u16 ring_len; /* number of descriptors, multiple of 8 */ - u16 headwb_enabled; /* deprecated with AVF 1.0 */ - u64 dma_ring_addr; - u64 dma_headwb_addr; /* deprecated with AVF 1.0 */ -}; - -VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_txq_info); - -/* RX descriptor IDs (range from 0 to 63) */ -enum virtchnl_rx_desc_ids { - VIRTCHNL_RXDID_0_16B_BASE = 0, - VIRTCHNL_RXDID_1_32B_BASE = 1, - VIRTCHNL_RXDID_2_FLEX_SQ_NIC = 2, - VIRTCHNL_RXDID_3_FLEX_SQ_SW = 3, - VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB = 4, - VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL = 5, - VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2 = 6, - VIRTCHNL_RXDID_7_HW_RSVD = 7, - /* 8 through 15 are reserved */ - VIRTCHNL_RXDID_16_COMMS_GENERIC = 16, - VIRTCHNL_RXDID_17_COMMS_AUX_VLAN = 17, - VIRTCHNL_RXDID_18_COMMS_AUX_IPV4 = 18, - VIRTCHNL_RXDID_19_COMMS_AUX_IPV6 = 19, - VIRTCHNL_RXDID_20_COMMS_AUX_FLOW = 20, - VIRTCHNL_RXDID_21_COMMS_AUX_TCP = 21, - /* 22 through 63 are reserved */ -}; - -/* RX descriptor ID bitmasks */ -enum virtchnl_rx_desc_id_bitmasks { - VIRTCHNL_RXDID_0_16B_BASE_M = BIT(VIRTCHNL_RXDID_0_16B_BASE), - VIRTCHNL_RXDID_1_32B_BASE_M = BIT(VIRTCHNL_RXDID_1_32B_BASE), - VIRTCHNL_RXDID_2_FLEX_SQ_NIC_M = BIT(VIRTCHNL_RXDID_2_FLEX_SQ_NIC), - VIRTCHNL_RXDID_3_FLEX_SQ_SW_M = BIT(VIRTCHNL_RXDID_3_FLEX_SQ_SW), - VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB_M = BIT(VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB), - VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL_M = BIT(VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL), - VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2_M = BIT(VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2), - VIRTCHNL_RXDID_7_HW_RSVD_M = BIT(VIRTCHNL_RXDID_7_HW_RSVD), - /* 9 through 15 are reserved */ - VIRTCHNL_RXDID_16_COMMS_GENERIC_M = BIT(VIRTCHNL_RXDID_16_COMMS_GENERIC), - VIRTCHNL_RXDID_17_COMMS_AUX_VLAN_M = BIT(VIRTCHNL_RXDID_17_COMMS_AUX_VLAN), - VIRTCHNL_RXDID_18_COMMS_AUX_IPV4_M = BIT(VIRTCHNL_RXDID_18_COMMS_AUX_IPV4), - VIRTCHNL_RXDID_19_COMMS_AUX_IPV6_M = BIT(VIRTCHNL_RXDID_19_COMMS_AUX_IPV6), - VIRTCHNL_RXDID_20_COMMS_AUX_FLOW_M = BIT(VIRTCHNL_RXDID_20_COMMS_AUX_FLOW), - VIRTCHNL_RXDID_21_COMMS_AUX_TCP_M = BIT(VIRTCHNL_RXDID_21_COMMS_AUX_TCP), - /* 22 through 63 are reserved */ -}; - -/* virtchnl_rxq_info_flags - * - * Definition of bits in the flags field of the virtchnl_rxq_info structure. - */ -enum virtchnl_rxq_info_flags { - /* If the VIRTCHNL_PTP_RX_TSTAMP bit of the flag field is set, this is - * a request to enable Rx timestamp. Other flag bits are currently - * reserved and they may be extended in the future. - */ - VIRTCHNL_PTP_RX_TSTAMP = BIT(0), -}; - -/* VIRTCHNL_OP_CONFIG_RX_QUEUE - * VF sends this message to set up parameters for one RX queue. - * External data buffer contains one instance of virtchnl_rxq_info. - * PF configures requested queue and returns a status code. The - * crc_disable flag disables CRC stripping on the VF. Setting - * the crc_disable flag to 1 will disable CRC stripping for each - * queue in the VF where the flag is set. The VIRTCHNL_VF_OFFLOAD_CRC - * offload must have been set prior to sending this info or the PF - * will ignore the request. This flag should be set the same for - * all of the queues for a VF. - */ - -/* Rx queue config info */ -struct virtchnl_rxq_info { - u16 vsi_id; - u16 queue_id; - u32 ring_len; /* number of descriptors, multiple of 32 */ - u16 hdr_size; - u16 splithdr_enabled; /* deprecated with AVF 1.0 */ - u32 databuffer_size; - u32 max_pkt_size; - u8 crc_disable; - u8 pad1[3]; - u64 dma_ring_addr; - - /* see enum virtchnl_rx_hsplit; deprecated with AVF 1.0 */ - s32 rx_split_pos; - u32 pad2; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_rxq_info); - -/* VIRTCHNL_OP_CONFIG_VSI_QUEUES - * VF sends this message to set parameters for active TX and RX queues - * associated with the specified VSI. - * PF configures queues and returns status. - * If the number of queues specified is greater than the number of queues - * associated with the VSI, an error is returned and no queues are configured. - * NOTE: The VF is not required to configure all queues in a single request. - * It may send multiple messages. PF drivers must correctly handle all VF - * requests. - */ -struct virtchnl_queue_pair_info { - /* NOTE: vsi_id and queue_id should be identical for both queues. */ - struct virtchnl_txq_info txq; - struct virtchnl_rxq_info rxq; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(64, virtchnl_queue_pair_info); - -struct virtchnl_vsi_queue_config_info { - u16 vsi_id; - u16 num_queue_pairs; - u32 pad; - struct virtchnl_queue_pair_info qpair[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_vsi_queue_config_info); - -/* VIRTCHNL_OP_REQUEST_QUEUES - * VF sends this message to request the PF to allocate additional queues to - * this VF. Each VF gets a guaranteed number of queues on init but asking for - * additional queues must be negotiated. This is a best effort request as it - * is possible the PF does not have enough queues left to support the request. - * If the PF cannot support the number requested it will respond with the - * maximum number it is able to support. If the request is successful, PF will - * then reset the VF to institute required changes. - */ - -/* VF resource request */ -struct virtchnl_vf_res_request { - u16 num_queue_pairs; -}; - -/* VIRTCHNL_OP_CONFIG_IRQ_MAP - * VF uses this message to map vectors to queues. - * The rxq_map and txq_map fields are bitmaps used to indicate which queues - * are to be associated with the specified vector. - * The "other" causes are always mapped to vector 0. The VF may not request - * that vector 0 be used for traffic. - * PF configures interrupt mapping and returns status. - * NOTE: due to hardware requirements, all active queues (both TX and RX) - * should be mapped to interrupts, even if the driver intends to operate - * only in polling mode. In this case the interrupt may be disabled, but - * the ITR timer will still run to trigger writebacks. - */ -struct virtchnl_vector_map { - u16 vsi_id; - u16 vector_id; - u16 rxq_map; - u16 txq_map; - u16 rxitr_idx; - u16 txitr_idx; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_vector_map); - -struct virtchnl_irq_map_info { - u16 num_vectors; - struct virtchnl_vector_map vecmap[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(14, virtchnl_irq_map_info); - -/* VIRTCHNL_OP_ENABLE_QUEUES - * VIRTCHNL_OP_DISABLE_QUEUES - * VF sends these message to enable or disable TX/RX queue pairs. - * The queues fields are bitmaps indicating which queues to act upon. - * (Currently, we only support 16 queues per VF, but we make the field - * u32 to allow for expansion.) - * PF performs requested action and returns status. - * NOTE: The VF is not required to enable/disable all queues in a single - * request. It may send multiple messages. - * PF drivers must correctly handle all VF requests. - */ -struct virtchnl_queue_select { - u16 vsi_id; - u16 pad; - u32 rx_queues; - u32 tx_queues; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_select); - -/* VIRTCHNL_OP_GET_MAX_RSS_QREGION - * - * if VIRTCHNL_VF_LARGE_NUM_QPAIRS was negotiated in VIRTCHNL_OP_GET_VF_RESOURCES - * then this op must be supported. - * - * VF sends this message in order to query the max RSS queue region - * size supported by PF, when VIRTCHNL_VF_LARGE_NUM_QPAIRS is enabled. - * This information should be used when configuring the RSS LUT and/or - * configuring queue region based filters. - * - * The maximum RSS queue region is 2^qregion_width. So, a qregion_width - * of 6 would inform the VF that the PF supports a maximum RSS queue region - * of 64. - * - * A queue region represents a range of queues that can be used to configure - * a RSS LUT. For example, if a VF is given 64 queues, but only a max queue - * region size of 16 (i.e. 2^qregion_width = 16) then it will only be able - * to configure the RSS LUT with queue indices from 0 to 15. However, other - * filters can be used to direct packets to queues >15 via specifying a queue - * base/offset and queue region width. - */ -struct virtchnl_max_rss_qregion { - u16 vport_id; - u16 qregion_width; - u8 pad[4]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_max_rss_qregion); - -/* VIRTCHNL_OP_ADD_ETH_ADDR - * VF sends this message in order to add one or more unicast or multicast - * address filters for the specified VSI. - * PF adds the filters and returns status. - */ - -/* VIRTCHNL_OP_DEL_ETH_ADDR - * VF sends this message in order to remove one or more unicast or multicast - * filters for the specified VSI. - * PF removes the filters and returns status. - */ - -/* VIRTCHNL_ETHER_ADDR_LEGACY - * Prior to adding the @type member to virtchnl_ether_addr, there were 2 pad - * bytes. Moving forward all VF drivers should not set type to - * VIRTCHNL_ETHER_ADDR_LEGACY. This is only here to not break previous/legacy - * behavior. The control plane function (i.e. PF) can use a best effort method - * of tracking the primary/device unicast in this case, but there is no - * guarantee and functionality depends on the implementation of the PF. - */ - -/* VIRTCHNL_ETHER_ADDR_PRIMARY - * All VF drivers should set @type to VIRTCHNL_ETHER_ADDR_PRIMARY for the - * primary/device unicast MAC address filter for VIRTCHNL_OP_ADD_ETH_ADDR and - * VIRTCHNL_OP_DEL_ETH_ADDR. This allows for the underlying control plane - * function (i.e. PF) to accurately track and use this MAC address for - * displaying on the host and for VM/function reset. - */ - -/* VIRTCHNL_ETHER_ADDR_EXTRA - * All VF drivers should set @type to VIRTCHNL_ETHER_ADDR_EXTRA for any extra - * unicast and/or multicast filters that are being added/deleted via - * VIRTCHNL_OP_DEL_ETH_ADDR/VIRTCHNL_OP_ADD_ETH_ADDR respectively. - */ -struct virtchnl_ether_addr { - u8 addr[VIRTCHNL_ETH_LENGTH_OF_ADDRESS]; - u8 type; -#define VIRTCHNL_ETHER_ADDR_LEGACY 0 -#define VIRTCHNL_ETHER_ADDR_PRIMARY 1 -#define VIRTCHNL_ETHER_ADDR_EXTRA 2 -#define VIRTCHNL_ETHER_ADDR_TYPE_MASK 3 /* first two bits of type are valid */ - u8 pad; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_ether_addr); - -struct virtchnl_ether_addr_list { - u16 vsi_id; - u16 num_elements; - struct virtchnl_ether_addr list[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_ether_addr_list); - -/* VIRTCHNL_OP_ADD_VLAN - * VF sends this message to add one or more VLAN tag filters for receives. - * PF adds the filters and returns status. - * If a port VLAN is configured by the PF, this operation will return an - * error to the VF. - */ - -/* VIRTCHNL_OP_DEL_VLAN - * VF sends this message to remove one or more VLAN tag filters for receives. - * PF removes the filters and returns status. - * If a port VLAN is configured by the PF, this operation will return an - * error to the VF. - */ - -struct virtchnl_vlan_filter_list { - u16 vsi_id; - u16 num_elements; - u16 vlan_id[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_vlan_filter_list); - -/* This enum is used for all of the VIRTCHNL_VF_OFFLOAD_VLAN_V2_CAPS related - * structures and opcodes. - * - * VIRTCHNL_VLAN_UNSUPPORTED - This field is not supported and if a VF driver - * populates it the PF should return VIRTCHNL_STATUS_ERR_NOT_SUPPORTED. - * - * VIRTCHNL_VLAN_ETHERTYPE_8100 - This field supports 0x8100 ethertype. - * VIRTCHNL_VLAN_ETHERTYPE_88A8 - This field supports 0x88A8 ethertype. - * VIRTCHNL_VLAN_ETHERTYPE_9100 - This field supports 0x9100 ethertype. - * - * VIRTCHNL_VLAN_ETHERTYPE_AND - Used when multiple ethertypes can be supported - * by the PF concurrently. For example, if the PF can support - * VIRTCHNL_VLAN_ETHERTYPE_8100 AND VIRTCHNL_VLAN_ETHERTYPE_88A8 filters it - * would OR the following bits: - * - * VIRTHCNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_AND; - * - * The VF would interpret this as VLAN filtering can be supported on both 0x8100 - * and 0x88A8 VLAN ethertypes. - * - * VIRTCHNL_ETHERTYPE_XOR - Used when only a single ethertype can be supported - * by the PF concurrently. For example if the PF can support - * VIRTCHNL_VLAN_ETHERTYPE_8100 XOR VIRTCHNL_VLAN_ETHERTYPE_88A8 stripping - * offload it would OR the following bits: - * - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_XOR; - * - * The VF would interpret this as VLAN stripping can be supported on either - * 0x8100 or 0x88a8 VLAN ethertypes. So when requesting VLAN stripping via - * VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 the specified ethertype will override - * the previously set value. - * - * VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1 - Used to tell the VF to insert and/or - * strip the VLAN tag using the L2TAG1 field of the Tx/Rx descriptors. - * - * VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2 - Used to tell the VF to insert hardware - * offloaded VLAN tags using the L2TAG2 field of the Tx descriptor. - * - * VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2 - Used to tell the VF to strip hardware - * offloaded VLAN tags using the L2TAG2_2 field of the Rx descriptor. - * - * VIRTCHNL_VLAN_PRIO - This field supports VLAN priority bits. This is used for - * VLAN filtering if the underlying PF supports it. - * - * VIRTCHNL_VLAN_TOGGLE_ALLOWED - This field is used to say whether a - * certain VLAN capability can be toggled. For example if the underlying PF/CP - * allows the VF to toggle VLAN filtering, stripping, and/or insertion it should - * set this bit along with the supported ethertypes. - */ -enum virtchnl_vlan_support { - VIRTCHNL_VLAN_UNSUPPORTED = 0, - VIRTCHNL_VLAN_ETHERTYPE_8100 = 0x00000001, - VIRTCHNL_VLAN_ETHERTYPE_88A8 = 0x00000002, - VIRTCHNL_VLAN_ETHERTYPE_9100 = 0x00000004, - VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1 = 0x00000100, - VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2 = 0x00000200, - VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2 = 0x00000400, - VIRTCHNL_VLAN_PRIO = 0x01000000, - VIRTCHNL_VLAN_FILTER_MASK = 0x10000000, - VIRTCHNL_VLAN_ETHERTYPE_AND = 0x20000000, - VIRTCHNL_VLAN_ETHERTYPE_XOR = 0x40000000, - VIRTCHNL_VLAN_TOGGLE = 0x80000000 -}; - -/* This structure is used as part of the VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS - * for filtering, insertion, and stripping capabilities. - * - * If only outer capabilities are supported (for filtering, insertion, and/or - * stripping) then this refers to the outer most or single VLAN from the VF's - * perspective. - * - * If only inner capabilities are supported (for filtering, insertion, and/or - * stripping) then this refers to the outer most or single VLAN from the VF's - * perspective. Functionally this is the same as if only outer capabilities are - * supported. The VF driver is just forced to use the inner fields when - * adding/deleting filters and enabling/disabling offloads (if supported). - * - * If both outer and inner capabilities are supported (for filtering, insertion, - * and/or stripping) then outer refers to the outer most or single VLAN and - * inner refers to the second VLAN, if it exists, in the packet. - * - * There is no support for tunneled VLAN offloads, so outer or inner are never - * referring to a tunneled packet from the VF's perspective. - */ -struct virtchnl_vlan_supported_caps { - u32 outer; - u32 inner; -}; - -/* The PF populates these fields based on the supported VLAN filtering. If a - * field is VIRTCHNL_VLAN_UNSUPPORTED then it's not supported and the PF will - * reject any VIRTCHNL_OP_ADD_VLAN_V2 or VIRTCHNL_OP_DEL_VLAN_V2 messages using - * the unsupported fields. - * - * Also, a VF is only allowed to toggle its VLAN filtering setting if the - * VIRTCHNL_VLAN_TOGGLE bit is set. - * - * The ethertype(s) specified in the ethertype_init field are the ethertypes - * enabled for VLAN filtering. VLAN filtering in this case refers to the outer - * most VLAN from the VF's perspective. If both inner and outer filtering are - * allowed then ethertype_init only refers to the outer most VLAN as only - * VLAN ethertype supported for inner VLAN filtering is - * VIRTCHNL_VLAN_ETHERTYPE_8100. By default, inner VLAN filtering is disabled - * when both inner and outer filtering are allowed. - * - * The max_filters field tells the VF how many VLAN filters it's allowed to have - * at any one time. If it exceeds this amount and tries to add another filter, - * then the request will be rejected by the PF. To prevent failures, the VF - * should keep track of how many VLAN filters it has added and not attempt to - * add more than max_filters. - */ -struct virtchnl_vlan_filtering_caps { - struct virtchnl_vlan_supported_caps filtering_support; - u32 ethertype_init; - u16 max_filters; - u8 pad[2]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vlan_filtering_caps); - -/* This enum is used for the virtchnl_vlan_offload_caps structure to specify - * if the PF supports a different ethertype for stripping and insertion. - * - * VIRTCHNL_ETHERTYPE_STRIPPING_MATCHES_INSERTION - The ethertype(s) specified - * for stripping affect the ethertype(s) specified for insertion and visa versa - * as well. If the VF tries to configure VLAN stripping via - * VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 with VIRTCHNL_VLAN_ETHERTYPE_8100 then - * that will be the ethertype for both stripping and insertion. - * - * VIRTCHNL_ETHERTYPE_MATCH_NOT_REQUIRED - The ethertype(s) specified for - * stripping do not affect the ethertype(s) specified for insertion and visa - * versa. - */ -enum virtchnl_vlan_ethertype_match { - VIRTCHNL_ETHERTYPE_STRIPPING_MATCHES_INSERTION = 0, - VIRTCHNL_ETHERTYPE_MATCH_NOT_REQUIRED = 1, -}; - -/* The PF populates these fields based on the supported VLAN offloads. If a - * field is VIRTCHNL_VLAN_UNSUPPORTED then it's not supported and the PF will - * reject any VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 or - * VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2 messages using the unsupported fields. - * - * Also, a VF is only allowed to toggle its VLAN offload setting if the - * VIRTCHNL_VLAN_TOGGLE_ALLOWED bit is set. - * - * The VF driver needs to be aware of how the tags are stripped by hardware and - * inserted by the VF driver based on the level of offload support. The PF will - * populate these fields based on where the VLAN tags are expected to be - * offloaded via the VIRTHCNL_VLAN_TAG_LOCATION_* bits. The VF will need to - * interpret these fields. See the definition of the - * VIRTCHNL_VLAN_TAG_LOCATION_* bits above the virtchnl_vlan_support - * enumeration. - */ -struct virtchnl_vlan_offload_caps { - struct virtchnl_vlan_supported_caps stripping_support; - struct virtchnl_vlan_supported_caps insertion_support; - u32 ethertype_init; - u8 ethertype_match; - u8 pad[3]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_vlan_offload_caps); - -/* VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS - * VF sends this message to determine its VLAN capabilities. - * - * PF will mark which capabilities it supports based on hardware support and - * current configuration. For example, if a port VLAN is configured the PF will - * not allow outer VLAN filtering, stripping, or insertion to be configured so - * it will block these features from the VF. - * - * The VF will need to cross reference its capabilities with the PFs - * capabilities in the response message from the PF to determine the VLAN - * support. - */ -struct virtchnl_vlan_caps { - struct virtchnl_vlan_filtering_caps filtering; - struct virtchnl_vlan_offload_caps offloads; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_vlan_caps); - -struct virtchnl_vlan { - u16 tci; /* tci[15:13] = PCP and tci[11:0] = VID */ - u16 tci_mask; /* only valid if VIRTCHNL_VLAN_FILTER_MASK set in - * filtering caps - */ - u16 tpid; /* 0x8100, 0x88a8, etc. and only type(s) set in - * filtering caps. Note that tpid here does not refer to - * VIRTCHNL_VLAN_ETHERTYPE_*, but it refers to the - * actual 2-byte VLAN TPID - */ - u8 pad[2]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_vlan); - -struct virtchnl_vlan_filter { - struct virtchnl_vlan inner; - struct virtchnl_vlan outer; - u8 pad[16]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(32, virtchnl_vlan_filter); - -/* VIRTCHNL_OP_ADD_VLAN_V2 - * VIRTCHNL_OP_DEL_VLAN_V2 - * - * VF sends these messages to add/del one or more VLAN tag filters for Rx - * traffic. - * - * The PF attempts to add the filters and returns status. - * - * The VF should only ever attempt to add/del virtchnl_vlan_filter(s) using the - * supported fields negotiated via VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS. - */ -struct virtchnl_vlan_filter_list_v2 { - u16 vport_id; - u16 num_elements; - u8 pad[4]; - struct virtchnl_vlan_filter filters[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_vlan_filter_list_v2); - -/* VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 - * VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2 - * VIRTCHNL_OP_ENABLE_VLAN_INSERTION_V2 - * VIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2 - * - * VF sends this message to enable or disable VLAN stripping or insertion. It - * also needs to specify an ethertype. The VF knows which VLAN ethertypes are - * allowed and whether or not it's allowed to enable/disable the specific - * offload via the VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS message. The VF needs to - * parse the virtchnl_vlan_caps.offloads fields to determine which offload - * messages are allowed. - * - * For example, if the PF populates the virtchnl_vlan_caps.offloads in the - * following manner the VF will be allowed to enable and/or disable 0x8100 inner - * VLAN insertion and/or stripping via the opcodes listed above. Inner in this - * case means the outer most or single VLAN from the VF's perspective. This is - * because no outer offloads are supported. See the comments above the - * virtchnl_vlan_supported_caps structure for more details. - * - * virtchnl_vlan_caps.offloads.stripping_support.inner = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100; - * - * virtchnl_vlan_caps.offloads.insertion_support.inner = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100; - * - * In order to enable inner (again note that in this case inner is the outer - * most or single VLAN from the VF's perspective) VLAN stripping for 0x8100 - * VLANs, the VF would populate the virtchnl_vlan_setting structure in the - * following manner and send the VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 message. - * - * virtchnl_vlan_setting.inner_ethertype_setting = - * VIRTCHNL_VLAN_ETHERTYPE_8100; - * - * virtchnl_vlan_setting.vport_id = vport_id or vsi_id assigned to the VF on - * initialization. - * - * The reason that VLAN TPID(s) are not being used for the - * outer_ethertype_setting and inner_ethertype_setting fields is because it's - * possible a device could support VLAN insertion and/or stripping offload on - * multiple ethertypes concurrently, so this method allows a VF to request - * multiple ethertypes in one message using the virtchnl_vlan_support - * enumeration. - * - * For example, if the PF populates the virtchnl_vlan_caps.offloads in the - * following manner the VF will be allowed to enable 0x8100 and 0x88a8 outer - * VLAN insertion and stripping simultaneously. The - * virtchnl_vlan_caps.offloads.ethertype_match field will also have to be - * populated based on what the PF can support. - * - * virtchnl_vlan_caps.offloads.stripping_support.outer = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_AND; - * - * virtchnl_vlan_caps.offloads.insertion_support.outer = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_AND; - * - * In order to enable outer VLAN stripping for 0x8100 and 0x88a8 VLANs, the VF - * would populate the virthcnl_vlan_offload_structure in the following manner - * and send the VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 message. - * - * virtchnl_vlan_setting.outer_ethertype_setting = - * VIRTHCNL_VLAN_ETHERTYPE_8100 | - * VIRTHCNL_VLAN_ETHERTYPE_88A8; - * - * virtchnl_vlan_setting.vport_id = vport_id or vsi_id assigned to the VF on - * initialization. - * - * There is also the case where a PF and the underlying hardware can support - * VLAN offloads on multiple ethertypes, but not concurrently. For example, if - * the PF populates the virtchnl_vlan_caps.offloads in the following manner the - * VF will be allowed to enable and/or disable 0x8100 XOR 0x88a8 outer VLAN - * offloads. The ethertypes must match for stripping and insertion. - * - * virtchnl_vlan_caps.offloads.stripping_support.outer = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_XOR; - * - * virtchnl_vlan_caps.offloads.insertion_support.outer = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_XOR; - * - * virtchnl_vlan_caps.offloads.ethertype_match = - * VIRTCHNL_ETHERTYPE_STRIPPING_MATCHES_INSERTION; - * - * In order to enable outer VLAN stripping for 0x88a8 VLANs, the VF would - * populate the virtchnl_vlan_setting structure in the following manner and send - * the VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2. Also, this will change the - * ethertype for VLAN insertion if it's enabled. So, for completeness, a - * VIRTCHNL_OP_ENABLE_VLAN_INSERTION_V2 with the same ethertype should be sent. - * - * virtchnl_vlan_setting.outer_ethertype_setting = VIRTHCNL_VLAN_ETHERTYPE_88A8; - * - * virtchnl_vlan_setting.vport_id = vport_id or vsi_id assigned to the VF on - * initialization. - * - * VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2 - * VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2 - * - * VF sends this message to enable or disable VLAN filtering. It also needs to - * specify an ethertype. The VF knows which VLAN ethertypes are allowed and - * whether or not it's allowed to enable/disable filtering via the - * VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS message. The VF needs to - * parse the virtchnl_vlan_caps.filtering fields to determine which, if any, - * filtering messages are allowed. - * - * For example, if the PF populates the virtchnl_vlan_caps.filtering in the - * following manner the VF will be allowed to enable/disable 0x8100 and 0x88a8 - * outer VLAN filtering together. Note, that the VIRTCHNL_VLAN_ETHERTYPE_AND - * means that all filtering ethertypes will to be enabled and disabled together - * regardless of the request from the VF. This means that the underlying - * hardware only supports VLAN filtering for all VLAN the specified ethertypes - * or none of them. - * - * virtchnl_vlan_caps.filtering.filtering_support.outer = - * VIRTCHNL_VLAN_TOGGLE | - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTHCNL_VLAN_ETHERTYPE_88A8 | - * VIRTCHNL_VLAN_ETHERTYPE_9100 | - * VIRTCHNL_VLAN_ETHERTYPE_AND; - * - * In order to enable outer VLAN filtering for 0x88a8 and 0x8100 VLANs (0x9100 - * VLANs aren't supported by the VF driver), the VF would populate the - * virtchnl_vlan_setting structure in the following manner and send the - * VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2. The same message format would be used - * to disable outer VLAN filtering for 0x88a8 and 0x8100 VLANs, but the - * VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2 opcode is used. - * - * virtchnl_vlan_setting.outer_ethertype_setting = - * VIRTCHNL_VLAN_ETHERTYPE_8100 | - * VIRTCHNL_VLAN_ETHERTYPE_88A8; - * - */ -struct virtchnl_vlan_setting { - u32 outer_ethertype_setting; - u32 inner_ethertype_setting; - u16 vport_id; - u8 pad[6]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vlan_setting); - -/* VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE - * VF sends VSI id and flags. - * PF returns status code in retval. - * Note: we assume that broadcast accept mode is always enabled. - */ -struct virtchnl_promisc_info { - u16 vsi_id; - u16 flags; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(4, virtchnl_promisc_info); - -#define FLAG_VF_UNICAST_PROMISC 0x00000001 -#define FLAG_VF_MULTICAST_PROMISC 0x00000002 - -/* VIRTCHNL_OP_GET_STATS - * VF sends this message to request stats for the selected VSI. VF uses - * the virtchnl_queue_select struct to specify the VSI. The queue_id - * field is ignored by the PF. - * - * PF replies with struct virtchnl_eth_stats in an external buffer. - */ - -struct virtchnl_eth_stats { - u64 rx_bytes; /* received bytes */ - u64 rx_unicast; /* received unicast pkts */ - u64 rx_multicast; /* received multicast pkts */ - u64 rx_broadcast; /* received broadcast pkts */ - u64 rx_discards; - u64 rx_unknown_protocol; - u64 tx_bytes; /* transmitted bytes */ - u64 tx_unicast; /* transmitted unicast pkts */ - u64 tx_multicast; /* transmitted multicast pkts */ - u64 tx_broadcast; /* transmitted broadcast pkts */ - u64 tx_discards; - u64 tx_errors; -}; - -/* VIRTCHNL_OP_CONFIG_RSS_KEY - * VIRTCHNL_OP_CONFIG_RSS_LUT - * VF sends these messages to configure RSS. Only supported if both PF - * and VF drivers set the VIRTCHNL_VF_OFFLOAD_RSS_PF bit during - * configuration negotiation. If this is the case, then the RSS fields in - * the VF resource struct are valid. - * Both the key and LUT are initialized to 0 by the PF, meaning that - * RSS is effectively disabled until set up by the VF. - */ -struct virtchnl_rss_key { - u16 vsi_id; - u16 key_len; - u8 key[1]; /* RSS hash key, packed bytes */ -}; - -VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_rss_key); - -struct virtchnl_rss_lut { - u16 vsi_id; - u16 lut_entries; - u8 lut[1]; /* RSS lookup table */ -}; - -VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_rss_lut); - -/* enum virthcnl_hash_filter - * - * Bits defining the hash filters in the hena field of the virtchnl_rss_hena - * structure. Each bit indicates a specific hash filter for RSS. - * - * Note that not all bits are supported on all hardware. The VF should use - * VIRTCHNL_OP_GET_RSS_HENA_CAPS to determine which bits the PF is capable of - * before using VIRTCHNL_OP_SET_RSS_HENA to enable specific filters. - */ -enum virtchnl_hash_filter { - /* Bits 0 through 28 are reserved for future use */ - /* Bit 29, 30, and 32 are not supported on XL710 a X710 */ - VIRTCHNL_HASH_FILTER_UNICAST_IPV4_UDP = 29, - VIRTCHNL_HASH_FILTER_MULTICAST_IPV4_UDP = 30, - VIRTCHNL_HASH_FILTER_IPV4_UDP = 31, - VIRTCHNL_HASH_FILTER_IPV4_TCP_SYN_NO_ACK = 32, - VIRTCHNL_HASH_FILTER_IPV4_TCP = 33, - VIRTCHNL_HASH_FILTER_IPV4_SCTP = 34, - VIRTCHNL_HASH_FILTER_IPV4_OTHER = 35, - VIRTCHNL_HASH_FILTER_FRAG_IPV4 = 36, - /* Bits 37 and 38 are reserved for future use */ - /* Bit 39, 40, and 42 are not supported on XL710 a X710 */ - VIRTCHNL_HASH_FILTER_UNICAST_IPV6_UDP = 39, - VIRTCHNL_HASH_FILTER_MULTICAST_IPV6_UDP = 40, - VIRTCHNL_HASH_FILTER_IPV6_UDP = 41, - VIRTCHNL_HASH_FILTER_IPV6_TCP_SYN_NO_ACK = 42, - VIRTCHNL_HASH_FILTER_IPV6_TCP = 43, - VIRTCHNL_HASH_FILTER_IPV6_SCTP = 44, - VIRTCHNL_HASH_FILTER_IPV6_OTHER = 45, - VIRTCHNL_HASH_FILTER_FRAG_IPV6 = 46, - /* Bit 37 is reserved for future use */ - VIRTCHNL_HASH_FILTER_FCOE_OX = 48, - VIRTCHNL_HASH_FILTER_FCOE_RX = 49, - VIRTCHNL_HASH_FILTER_FCOE_OTHER = 50, - /* Bits 51 through 62 are reserved for future use */ - VIRTCHNL_HASH_FILTER_L2_PAYLOAD = 63, -}; - -#define VIRTCHNL_HASH_FILTER_INVALID (0) - -/* VIRTCHNL_OP_GET_RSS_HENA_CAPS - * VIRTCHNL_OP_SET_RSS_HENA - * VF sends these messages to get and set the hash filter enable bits for RSS. - * By default, the PF sets these to all possible traffic types that the - * hardware supports. The VF can query this value if it wants to change the - * traffic types that are hashed by the hardware. - */ -struct virtchnl_rss_hena { - /* see enum virtchnl_hash_filter */ - u64 hena; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_rss_hena); - -/* Type of RSS algorithm */ -enum virtchnl_rss_algorithm { - VIRTCHNL_RSS_ALG_TOEPLITZ_ASYMMETRIC = 0, - VIRTCHNL_RSS_ALG_R_ASYMMETRIC = 1, - VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC = 2, - VIRTCHNL_RSS_ALG_XOR_SYMMETRIC = 3, -}; - -/* This is used by PF driver to enforce how many channels can be supported. - * When ADQ_V2 capability is negotiated, it will allow 16 channels otherwise - * PF driver will allow only max 4 channels - */ -#define VIRTCHNL_MAX_ADQ_CHANNELS 4 -#define VIRTCHNL_MAX_ADQ_V2_CHANNELS 16 - -/* VIRTCHNL_OP_ENABLE_CHANNELS - * VIRTCHNL_OP_DISABLE_CHANNELS - * VF sends these messages to enable or disable channels based on - * the user specified queue count and queue offset for each traffic class. - * This struct encompasses all the information that the PF needs from - * VF to create a channel. - */ -struct virtchnl_channel_info { - u16 count; /* number of queues in a channel */ - u16 offset; /* queues in a channel start from 'offset' */ - u32 pad; - u64 max_tx_rate; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_channel_info); - -struct virtchnl_tc_info { - u32 num_tc; - u32 pad; - struct virtchnl_channel_info list[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_tc_info); - -/* VIRTCHNL_ADD_CLOUD_FILTER - * VIRTCHNL_DEL_CLOUD_FILTER - * VF sends these messages to add or delete a cloud filter based on the - * user specified match and action filters. These structures encompass - * all the information that the PF needs from the VF to add/delete a - * cloud filter. - */ - -struct virtchnl_l4_spec { - u8 src_mac[VIRTCHNL_ETH_LENGTH_OF_ADDRESS]; - u8 dst_mac[VIRTCHNL_ETH_LENGTH_OF_ADDRESS]; - /* vlan_prio is part of this 16 bit field even from OS perspective - * vlan_id:12 is actual vlan_id, then vlanid:bit14..12 is vlan_prio - * in future, when decided to offload vlan_prio, pass that information - * as part of the "vlan_id" field, Bit14..12 - */ - __be16 vlan_id; - __be16 pad; /* reserved for future use */ - __be32 src_ip[4]; - __be32 dst_ip[4]; - __be16 src_port; - __be16 dst_port; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(52, virtchnl_l4_spec); - -union virtchnl_flow_spec { - struct virtchnl_l4_spec tcp_spec; - u8 buffer[128]; /* reserved for future use */ -}; - -VIRTCHNL_CHECK_UNION_LEN(128, virtchnl_flow_spec); - -enum virtchnl_action { - /* action types */ - VIRTCHNL_ACTION_DROP = 0, - VIRTCHNL_ACTION_TC_REDIRECT, - VIRTCHNL_ACTION_PASSTHRU, - VIRTCHNL_ACTION_QUEUE, - VIRTCHNL_ACTION_Q_REGION, - VIRTCHNL_ACTION_MARK, - VIRTCHNL_ACTION_COUNT, -}; - -enum virtchnl_flow_type { - /* flow types */ - VIRTCHNL_TCP_V4_FLOW = 0, - VIRTCHNL_TCP_V6_FLOW, - VIRTCHNL_UDP_V4_FLOW, - VIRTCHNL_UDP_V6_FLOW, -}; - -struct virtchnl_filter { - union virtchnl_flow_spec data; - union virtchnl_flow_spec mask; - - /* see enum virtchnl_flow_type */ - s32 flow_type; - - /* see enum virtchnl_action */ - s32 action; - u32 action_meta; - u8 field_flags; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter); - -struct virtchnl_shaper_bw { - /* Unit is Kbps */ - u32 committed; - u32 peak; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_shaper_bw); - - - -/* VIRTCHNL_OP_EVENT - * PF sends this message to inform the VF driver of events that may affect it. - * No direct response is expected from the VF, though it may generate other - * messages in response to this one. - */ -enum virtchnl_event_codes { - VIRTCHNL_EVENT_UNKNOWN = 0, - VIRTCHNL_EVENT_LINK_CHANGE, - VIRTCHNL_EVENT_RESET_IMPENDING, - VIRTCHNL_EVENT_PF_DRIVER_CLOSE, -}; - -#define PF_EVENT_SEVERITY_INFO 0 -#define PF_EVENT_SEVERITY_ATTENTION 1 -#define PF_EVENT_SEVERITY_ACTION_REQUIRED 2 -#define PF_EVENT_SEVERITY_CERTAIN_DOOM 255 - -struct virtchnl_pf_event { - /* see enum virtchnl_event_codes */ - s32 event; - union { - /* If the PF driver does not support the new speed reporting - * capabilities then use link_event else use link_event_adv to - * get the speed and link information. The ability to understand - * new speeds is indicated by setting the capability flag - * VIRTCHNL_VF_CAP_ADV_LINK_SPEED in vf_cap_flags parameter - * in virtchnl_vf_resource struct and can be used to determine - * which link event struct to use below. - */ - struct { - enum virtchnl_link_speed link_speed; - bool link_status; - u8 pad[3]; - } link_event; - struct { - /* link_speed provided in Mbps */ - u32 link_speed; - u8 link_status; - u8 pad[3]; - } link_event_adv; - } event_data; - - s32 severity; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_pf_event); - - -/* VF reset states - these are written into the RSTAT register: - * VFGEN_RSTAT on the VF - * When the PF initiates a reset, it writes 0 - * When the reset is complete, it writes 1 - * When the PF detects that the VF has recovered, it writes 2 - * VF checks this register periodically to determine if a reset has occurred, - * then polls it to know when the reset is complete. - * If either the PF or VF reads the register while the hardware - * is in a reset state, it will return DEADBEEF, which, when masked - * will result in 3. - */ -enum virtchnl_vfr_states { - VIRTCHNL_VFR_INPROGRESS = 0, - VIRTCHNL_VFR_COMPLETED, - VIRTCHNL_VFR_VFACTIVE, -}; - -#define VIRTCHNL_MAX_NUM_PROTO_HDRS 32 -#define VIRTCHNL_MAX_SIZE_RAW_PACKET 1024 -#define PROTO_HDR_SHIFT 5 -#define PROTO_HDR_FIELD_START(proto_hdr_type) \ - (proto_hdr_type << PROTO_HDR_SHIFT) -#define PROTO_HDR_FIELD_MASK ((1UL << PROTO_HDR_SHIFT) - 1) - -/* VF use these macros to configure each protocol header. - * Specify which protocol headers and protocol header fields base on - * virtchnl_proto_hdr_type and virtchnl_proto_hdr_field. - * @param hdr: a struct of virtchnl_proto_hdr - * @param hdr_type: ETH/IPV4/TCP, etc - * @param field: SRC/DST/TEID/SPI, etc - */ -#define VIRTCHNL_ADD_PROTO_HDR_FIELD(hdr, field) \ - ((hdr)->field_selector |= BIT((field) & PROTO_HDR_FIELD_MASK)) -#define VIRTCHNL_DEL_PROTO_HDR_FIELD(hdr, field) \ - ((hdr)->field_selector &= ~BIT((field) & PROTO_HDR_FIELD_MASK)) -#define VIRTCHNL_TEST_PROTO_HDR_FIELD(hdr, val) \ - ((hdr)->field_selector & BIT((val) & PROTO_HDR_FIELD_MASK)) -#define VIRTCHNL_GET_PROTO_HDR_FIELD(hdr) ((hdr)->field_selector) - -#define VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, hdr_type, field) \ - (VIRTCHNL_ADD_PROTO_HDR_FIELD(hdr, \ - VIRTCHNL_PROTO_HDR_ ## hdr_type ## _ ## field)) -#define VIRTCHNL_DEL_PROTO_HDR_FIELD_BIT(hdr, hdr_type, field) \ - (VIRTCHNL_DEL_PROTO_HDR_FIELD(hdr, \ - VIRTCHNL_PROTO_HDR_ ## hdr_type ## _ ## field)) - -#define VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, hdr_type) \ - ((hdr)->type = VIRTCHNL_PROTO_HDR_ ## hdr_type) -#define VIRTCHNL_GET_PROTO_HDR_TYPE(hdr) \ - (((hdr)->type) >> PROTO_HDR_SHIFT) -#define VIRTCHNL_TEST_PROTO_HDR_TYPE(hdr, val) \ - ((hdr)->type == ((s32)((val) >> PROTO_HDR_SHIFT))) -#define VIRTCHNL_TEST_PROTO_HDR(hdr, val) \ - (VIRTCHNL_TEST_PROTO_HDR_TYPE(hdr, val) && \ - VIRTCHNL_TEST_PROTO_HDR_FIELD(hdr, val)) - -/* Protocol header type within a packet segment. A segment consists of one or - * more protocol headers that make up a logical group of protocol headers. Each - * logical group of protocol headers encapsulates or is encapsulated using/by - * tunneling or encapsulation protocols for network virtualization. - */ -enum virtchnl_proto_hdr_type { - VIRTCHNL_PROTO_HDR_NONE, - VIRTCHNL_PROTO_HDR_ETH, - VIRTCHNL_PROTO_HDR_S_VLAN, - VIRTCHNL_PROTO_HDR_C_VLAN, - VIRTCHNL_PROTO_HDR_IPV4, - VIRTCHNL_PROTO_HDR_IPV6, - VIRTCHNL_PROTO_HDR_TCP, - VIRTCHNL_PROTO_HDR_UDP, - VIRTCHNL_PROTO_HDR_SCTP, - VIRTCHNL_PROTO_HDR_GTPU_IP, - VIRTCHNL_PROTO_HDR_GTPU_EH, - VIRTCHNL_PROTO_HDR_GTPU_EH_PDU_DWN, - VIRTCHNL_PROTO_HDR_GTPU_EH_PDU_UP, - VIRTCHNL_PROTO_HDR_PPPOE, - VIRTCHNL_PROTO_HDR_L2TPV3, - VIRTCHNL_PROTO_HDR_ESP, - VIRTCHNL_PROTO_HDR_AH, - VIRTCHNL_PROTO_HDR_PFCP, - VIRTCHNL_PROTO_HDR_GTPC, - VIRTCHNL_PROTO_HDR_ECPRI, - VIRTCHNL_PROTO_HDR_L2TPV2, - VIRTCHNL_PROTO_HDR_PPP, - /* IPv4 and IPv6 Fragment header types are only associated to - * VIRTCHNL_PROTO_HDR_IPV4 and VIRTCHNL_PROTO_HDR_IPV6 respectively, - * cannot be used independently. - */ - VIRTCHNL_PROTO_HDR_IPV4_FRAG, - VIRTCHNL_PROTO_HDR_IPV6_EH_FRAG, - VIRTCHNL_PROTO_HDR_GRE, -}; - -/* Protocol header field within a protocol header. */ -enum virtchnl_proto_hdr_field { - /* ETHER */ - VIRTCHNL_PROTO_HDR_ETH_SRC = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_ETH), - VIRTCHNL_PROTO_HDR_ETH_DST, - VIRTCHNL_PROTO_HDR_ETH_ETHERTYPE, - /* S-VLAN */ - VIRTCHNL_PROTO_HDR_S_VLAN_ID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_S_VLAN), - /* C-VLAN */ - VIRTCHNL_PROTO_HDR_C_VLAN_ID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_C_VLAN), - /* IPV4 */ - VIRTCHNL_PROTO_HDR_IPV4_SRC = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_IPV4), - VIRTCHNL_PROTO_HDR_IPV4_DST, - VIRTCHNL_PROTO_HDR_IPV4_DSCP, - VIRTCHNL_PROTO_HDR_IPV4_TTL, - VIRTCHNL_PROTO_HDR_IPV4_PROT, - VIRTCHNL_PROTO_HDR_IPV4_CHKSUM, - /* IPV6 */ - VIRTCHNL_PROTO_HDR_IPV6_SRC = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_IPV6), - VIRTCHNL_PROTO_HDR_IPV6_DST, - VIRTCHNL_PROTO_HDR_IPV6_TC, - VIRTCHNL_PROTO_HDR_IPV6_HOP_LIMIT, - VIRTCHNL_PROTO_HDR_IPV6_PROT, - /* IPV6 Prefix */ - VIRTCHNL_PROTO_HDR_IPV6_PREFIX32_SRC, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX32_DST, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX40_SRC, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX40_DST, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX48_SRC, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX48_DST, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX56_SRC, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX56_DST, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX64_SRC, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX64_DST, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX96_SRC, - VIRTCHNL_PROTO_HDR_IPV6_PREFIX96_DST, - /* TCP */ - VIRTCHNL_PROTO_HDR_TCP_SRC_PORT = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_TCP), - VIRTCHNL_PROTO_HDR_TCP_DST_PORT, - VIRTCHNL_PROTO_HDR_TCP_CHKSUM, - /* UDP */ - VIRTCHNL_PROTO_HDR_UDP_SRC_PORT = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_UDP), - VIRTCHNL_PROTO_HDR_UDP_DST_PORT, - VIRTCHNL_PROTO_HDR_UDP_CHKSUM, - /* SCTP */ - VIRTCHNL_PROTO_HDR_SCTP_SRC_PORT = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_SCTP), - VIRTCHNL_PROTO_HDR_SCTP_DST_PORT, - VIRTCHNL_PROTO_HDR_SCTP_CHKSUM, - /* GTPU_IP */ - VIRTCHNL_PROTO_HDR_GTPU_IP_TEID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_GTPU_IP), - /* GTPU_EH */ - VIRTCHNL_PROTO_HDR_GTPU_EH_PDU = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_GTPU_EH), - VIRTCHNL_PROTO_HDR_GTPU_EH_QFI, - /* PPPOE */ - VIRTCHNL_PROTO_HDR_PPPOE_SESS_ID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_PPPOE), - /* L2TPV3 */ - VIRTCHNL_PROTO_HDR_L2TPV3_SESS_ID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_L2TPV3), - /* ESP */ - VIRTCHNL_PROTO_HDR_ESP_SPI = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_ESP), - /* AH */ - VIRTCHNL_PROTO_HDR_AH_SPI = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_AH), - /* PFCP */ - VIRTCHNL_PROTO_HDR_PFCP_S_FIELD = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_PFCP), - VIRTCHNL_PROTO_HDR_PFCP_SEID, - /* GTPC */ - VIRTCHNL_PROTO_HDR_GTPC_TEID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_GTPC), - /* ECPRI */ - VIRTCHNL_PROTO_HDR_ECPRI_MSG_TYPE = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_ECPRI), - VIRTCHNL_PROTO_HDR_ECPRI_PC_RTC_ID, - /* IPv4 Dummy Fragment */ - VIRTCHNL_PROTO_HDR_IPV4_FRAG_PKID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_IPV4_FRAG), - /* IPv6 Extension Fragment */ - VIRTCHNL_PROTO_HDR_IPV6_EH_FRAG_PKID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_IPV6_EH_FRAG), - /* GTPU_DWN/UP */ - VIRTCHNL_PROTO_HDR_GTPU_DWN_QFI = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_GTPU_EH_PDU_DWN), - VIRTCHNL_PROTO_HDR_GTPU_UP_QFI = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_GTPU_EH_PDU_UP), - /* L2TPv2 */ - VIRTCHNL_PROTO_HDR_L2TPV2_SESS_ID = - PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_L2TPV2), - VIRTCHNL_PROTO_HDR_L2TPV2_LEN_SESS_ID, -}; - -struct virtchnl_proto_hdr { - /* see enum virtchnl_proto_hdr_type */ - s32 type; - u32 field_selector; /* a bit mask to select field for header type */ - u8 buffer[64]; - /** - * binary buffer in network order for specific header type. - * For example, if type = VIRTCHNL_PROTO_HDR_IPV4, a IPv4 - * header is expected to be copied into the buffer. - */ -}; - -VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_proto_hdr); - -struct virtchnl_proto_hdrs { - u8 tunnel_level; - /** - * specify where protocol header start from. - * must be 0 when sending a raw packet request. - * 0 - from the outer layer - * 1 - from the first inner layer - * 2 - from the second inner layer - * .... - */ - int count; - /** - * number of proto layers, must < VIRTCHNL_MAX_NUM_PROTO_HDRS - * must be 0 for a raw packet request. - */ - union { - struct virtchnl_proto_hdr - proto_hdr[VIRTCHNL_MAX_NUM_PROTO_HDRS]; - struct { - u16 pkt_len; - u8 spec[VIRTCHNL_MAX_SIZE_RAW_PACKET]; - u8 mask[VIRTCHNL_MAX_SIZE_RAW_PACKET]; - } raw; - }; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(2312, virtchnl_proto_hdrs); - -struct virtchnl_rss_cfg { - struct virtchnl_proto_hdrs proto_hdrs; /* protocol headers */ - - /* see enum virtchnl_rss_algorithm; rss algorithm type */ - s32 rss_algorithm; - u8 reserved[128]; /* reserve for future */ -}; - -VIRTCHNL_CHECK_STRUCT_LEN(2444, virtchnl_rss_cfg); - -/* action configuration for FDIR */ -struct virtchnl_filter_action { - /* see enum virtchnl_action type */ - s32 type; - union { - /* used for queue and qgroup action */ - struct { - u16 index; - u8 region; - } queue; - /* used for count action */ - struct { - /* share counter ID with other flow rules */ - u8 shared; - u32 id; /* counter ID */ - } count; - /* used for mark action */ - u32 mark_id; - u8 reserve[32]; - } act_conf; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(36, virtchnl_filter_action); - -#define VIRTCHNL_MAX_NUM_ACTIONS 8 - -struct virtchnl_filter_action_set { - /* action number must be less then VIRTCHNL_MAX_NUM_ACTIONS */ - int count; - struct virtchnl_filter_action actions[VIRTCHNL_MAX_NUM_ACTIONS]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(292, virtchnl_filter_action_set); - -/* pattern and action for FDIR rule */ -struct virtchnl_fdir_rule { - struct virtchnl_proto_hdrs proto_hdrs; - struct virtchnl_filter_action_set action_set; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(2604, virtchnl_fdir_rule); - -/* Status returned to VF after VF requests FDIR commands - * VIRTCHNL_FDIR_SUCCESS - * VF FDIR related request is successfully done by PF - * The request can be OP_ADD/DEL/QUERY_FDIR_FILTER. - * - * VIRTCHNL_FDIR_FAILURE_RULE_NORESOURCE - * OP_ADD_FDIR_FILTER request is failed due to no Hardware resource. - * - * VIRTCHNL_FDIR_FAILURE_RULE_EXIST - * OP_ADD_FDIR_FILTER request is failed due to the rule is already existed. - * - * VIRTCHNL_FDIR_FAILURE_RULE_CONFLICT - * OP_ADD_FDIR_FILTER request is failed due to conflict with existing rule. - * - * VIRTCHNL_FDIR_FAILURE_RULE_NONEXIST - * OP_DEL_FDIR_FILTER request is failed due to this rule doesn't exist. - * - * VIRTCHNL_FDIR_FAILURE_RULE_INVALID - * OP_ADD_FDIR_FILTER request is failed due to parameters validation - * or HW doesn't support. - * - * VIRTCHNL_FDIR_FAILURE_RULE_TIMEOUT - * OP_ADD/DEL_FDIR_FILTER request is failed due to timing out - * for programming. - * - * VIRTCHNL_FDIR_FAILURE_QUERY_INVALID - * OP_QUERY_FDIR_FILTER request is failed due to parameters validation, - * for example, VF query counter of a rule who has no counter action. - */ -enum virtchnl_fdir_prgm_status { - VIRTCHNL_FDIR_SUCCESS = 0, - VIRTCHNL_FDIR_FAILURE_RULE_NORESOURCE, - VIRTCHNL_FDIR_FAILURE_RULE_EXIST, - VIRTCHNL_FDIR_FAILURE_RULE_CONFLICT, - VIRTCHNL_FDIR_FAILURE_RULE_NONEXIST, - VIRTCHNL_FDIR_FAILURE_RULE_INVALID, - VIRTCHNL_FDIR_FAILURE_RULE_TIMEOUT, - VIRTCHNL_FDIR_FAILURE_QUERY_INVALID, -}; - -/* VIRTCHNL_OP_ADD_FDIR_FILTER - * VF sends this request to PF by filling out vsi_id, - * validate_only and rule_cfg. PF will return flow_id - * if the request is successfully done and return add_status to VF. - */ -struct virtchnl_fdir_add { - u16 vsi_id; /* INPUT */ - /* - * 1 for validating a fdir rule, 0 for creating a fdir rule. - * Validate and create share one ops: VIRTCHNL_OP_ADD_FDIR_FILTER. - */ - u16 validate_only; /* INPUT */ - u32 flow_id; /* OUTPUT */ - struct virtchnl_fdir_rule rule_cfg; /* INPUT */ - - /* see enum virtchnl_fdir_prgm_status; OUTPUT */ - s32 status; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(2616, virtchnl_fdir_add); - -/* VIRTCHNL_OP_DEL_FDIR_FILTER - * VF sends this request to PF by filling out vsi_id - * and flow_id. PF will return del_status to VF. - */ -struct virtchnl_fdir_del { - u16 vsi_id; /* INPUT */ - u16 pad; - u32 flow_id; /* INPUT */ - - /* see enum virtchnl_fdir_prgm_status; OUTPUT */ - s32 status; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_fdir_del); - -/* VIRTCHNL_OP_GET_QOS_CAPS - * VF sends this message to get its QoS Caps, such as - * TC number, Arbiter and Bandwidth. - */ -struct virtchnl_qos_cap_elem { - u8 tc_num; - u8 tc_prio; -#define VIRTCHNL_ABITER_STRICT 0 -#define VIRTCHNL_ABITER_ETS 2 - u8 arbiter; -#define VIRTCHNL_STRICT_WEIGHT 1 - u8 weight; - enum virtchnl_bw_limit_type type; - union { - struct virtchnl_shaper_bw shaper; - u8 pad2[32]; - }; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_qos_cap_elem); - -struct virtchnl_qos_cap_list { - u16 vsi_id; - u16 num_elem; - struct virtchnl_qos_cap_elem cap[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(44, virtchnl_qos_cap_list); - -/* VIRTCHNL_OP_CONFIG_QUEUE_TC_MAP - * VF sends message virtchnl_queue_tc_mapping to set queue to tc - * mapping for all the Tx and Rx queues with a specified VSI, and - * would get response about bitmap of valid user priorities - * associated with queues. - */ -struct virtchnl_queue_tc_mapping { - u16 vsi_id; - u16 num_tc; - u16 num_queue_pairs; - u8 pad[2]; - union { - struct { - u16 start_queue_id; - u16 queue_count; - } req; - struct { -#define VIRTCHNL_USER_PRIO_TYPE_UP 0 -#define VIRTCHNL_USER_PRIO_TYPE_DSCP 1 - u16 prio_type; - u16 valid_prio_bitmap; - } resp; - } tc[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_tc_mapping); - -/* VIRTCHNL_OP_CONFIG_QUEUE_BW */ -struct virtchnl_queue_bw { - u16 queue_id; - u8 tc; - u8 pad; - struct virtchnl_shaper_bw shaper; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_bw); - -struct virtchnl_queues_bw_cfg { - u16 vsi_id; - u16 num_queues; - struct virtchnl_queue_bw cfg[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_queues_bw_cfg); - -/* queue types */ -enum virtchnl_queue_type { - VIRTCHNL_QUEUE_TYPE_TX = 0, - VIRTCHNL_QUEUE_TYPE_RX = 1, -}; - -/* structure to specify a chunk of contiguous queues */ -struct virtchnl_queue_chunk { - /* see enum virtchnl_queue_type */ - s32 type; - u16 start_queue_id; - u16 num_queues; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_queue_chunk); - -/* structure to specify several chunks of contiguous queues */ -struct virtchnl_queue_chunks { - u16 num_chunks; - u16 rsvd; - struct virtchnl_queue_chunk chunks[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_chunks); - -/* VIRTCHNL_OP_ENABLE_QUEUES_V2 - * VIRTCHNL_OP_DISABLE_QUEUES_V2 - * - * These opcodes can be used if VIRTCHNL_VF_LARGE_NUM_QPAIRS was negotiated in - * VIRTCHNL_OP_GET_VF_RESOURCES - * - * VF sends virtchnl_ena_dis_queues struct to specify the queues to be - * enabled/disabled in chunks. Also applicable to single queue RX or - * TX. PF performs requested action and returns status. - */ -struct virtchnl_del_ena_dis_queues { - u16 vport_id; - u16 pad; - struct virtchnl_queue_chunks chunks; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_del_ena_dis_queues); - -/* Virtchannel interrupt throttling rate index */ -enum virtchnl_itr_idx { - VIRTCHNL_ITR_IDX_0 = 0, - VIRTCHNL_ITR_IDX_1 = 1, - VIRTCHNL_ITR_IDX_NO_ITR = 3, -}; - -/* Queue to vector mapping */ -struct virtchnl_queue_vector { - u16 queue_id; - u16 vector_id; - u8 pad[4]; - - /* see enum virtchnl_itr_idx */ - s32 itr_idx; - - /* see enum virtchnl_queue_type */ - s32 queue_type; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_queue_vector); - -/* VIRTCHNL_OP_MAP_QUEUE_VECTOR - * - * This opcode can be used only if VIRTCHNL_VF_LARGE_NUM_QPAIRS was negotiated - * in VIRTCHNL_OP_GET_VF_RESOURCES - * - * VF sends this message to map queues to vectors and ITR index registers. - * External data buffer contains virtchnl_queue_vector_maps structure - * that contains num_qv_maps of virtchnl_queue_vector structures. - * PF maps the requested queue vector maps after validating the queue and vector - * ids and returns a status code. - */ -struct virtchnl_queue_vector_maps { - u16 vport_id; - u16 num_qv_maps; - u8 pad[4]; - struct virtchnl_queue_vector qv_maps[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_queue_vector_maps); - -struct virtchnl_quanta_cfg { - u16 quanta_size; - struct virtchnl_queue_chunk queue_select; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); - -/* VIRTCHNL_VF_CAP_PTP - * VIRTCHNL_OP_1588_PTP_GET_CAPS - * VIRTCHNL_OP_1588_PTP_GET_TIME - * VIRTCHNL_OP_1588_PTP_SET_TIME - * VIRTCHNL_OP_1588_PTP_ADJ_TIME - * VIRTCHNL_OP_1588_PTP_ADJ_FREQ - * VIRTCHNL_OP_1588_PTP_TX_TIMESTAMP - * VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS - * VIRTCHNL_OP_1588_PTP_SET_PIN_CFG - * VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP - * - * Support for offloading control of the device PTP hardware clock (PHC) is enabled - * by VIRTCHNL_VF_CAP_PTP. This capability allows a VF to request that PF - * enable Tx and Rx timestamps, and request access to read and/or write the - * PHC on the device, as well as query if the VF has direct access to the PHC - * time registers. - * - * The VF must set VIRTCHNL_VF_CAP_PTP in its capabilities when requesting - * resources. If the capability is set in reply, the VF must then send - * a VIRTCHNL_OP_1588_PTP_GET_CAPS request during initialization. The VF indicates - * what extended capabilities it wants by setting the appropriate flags in the - * caps field. The PF reply will indicate what features are enabled for - * that VF. - */ -#define VIRTCHNL_1588_PTP_CAP_TX_TSTAMP BIT(0) -#define VIRTCHNL_1588_PTP_CAP_RX_TSTAMP BIT(1) -#define VIRTCHNL_1588_PTP_CAP_READ_PHC BIT(2) -#define VIRTCHNL_1588_PTP_CAP_WRITE_PHC BIT(3) -#define VIRTCHNL_1588_PTP_CAP_PHC_REGS BIT(4) -#define VIRTCHNL_1588_PTP_CAP_PIN_CFG BIT(5) - -/** - * virtchnl_phc_regs - * - * Structure defines how the VF should access PHC related registers. The VF - * must request VIRTCHNL_1588_PTP_CAP_PHC_REGS. If the VF has access to PHC - * registers, the PF will reply with the capability flag set, and with this - * structure detailing what PCIe region and what offsets to use. If direct - * access is not available, this entire structure is reserved and the fields - * will be zero. - * - * If necessary in a future extension, a separate capability mutually - * exclusive with VIRTCHNL_1588_PTP_CAP_PHC_REGS might be used to change the - * entire format of this structure within virtchnl_ptp_caps. - * - * @clock_hi: Register offset of the high 32 bits of clock time - * @clock_lo: Register offset of the low 32 bits of clock time - * @pcie_region: The PCIe region the registers are located in. - * @rsvd: Reserved bits for future extension - */ -struct virtchnl_phc_regs { - u32 clock_hi; - u32 clock_lo; - u8 pcie_region; - u8 rsvd[15]; -}; -VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_phc_regs); - -/* timestamp format enumeration - * - * VIRTCHNL_1588_PTP_TSTAMP_40BIT - * - * This format indicates a timestamp that uses the 40bit format from the - * flexible Rx descriptors. It is also the default Tx timestamp format used - * today. - * - * Such a timestamp has the following 40bit format: - * - * *--------------------------------*-------------------------------*-----------* - * | 32 bits of time in nanoseconds | 7 bits of sub-nanosecond time | valid bit | - * *--------------------------------*-------------------------------*-----------* - * - * The timestamp is passed in a u64, with the upper 24bits of the field - * reserved as zero. - * - * With this format, in order to report a full 64bit timestamp to userspace - * applications, the VF is responsible for performing timestamp extension by - * carefully comparing the timestamp with the PHC time. This can correctly - * be achieved with a recent cached copy of the PHC time by doing delta - * comparison between the 32bits of nanoseconds in the timestamp with the - * lower 32 bits of the clock time. For this to work, the cached PHC time - * must be from within 2^31 nanoseconds (~2.1 seconds) of when the timestamp - * was captured. - * - * VIRTCHNL_1588_PTP_TSTAMP_64BIT_NS - * - * This format indicates a timestamp that is 64 bits of nanoseconds. - */ -enum virtchnl_ptp_tstamp_format { - VIRTCHNL_1588_PTP_TSTAMP_40BIT = 0, - VIRTCHNL_1588_PTP_TSTAMP_64BIT_NS = 1, -}; - -/** - * virtchnl_ptp_caps - * - * Structure that defines the PTP capabilities available to the VF. The VF - * sends VIRTCHNL_OP_1588_PTP_GET_CAPS, and must fill in the ptp_caps field - * indicating what capabilities it is requesting. The PF will respond with the - * same message with the virtchnl_ptp_caps structure indicating what is - * enabled for the VF. - * - * @phc_regs: If VIRTCHNL_1588_PTP_CAP_PHC_REGS is set, contains information - * on the PHC related registers available to the VF. - * @caps: On send, VF sets what capabilities it requests. On reply, PF - * indicates what has been enabled for this VF. The PF shall not set - * bits which were not requested by the VF. - * @max_adj: The maximum adjustment capable of being requested by - * VIRTCHNL_OP_1588_PTP_ADJ_FREQ, in parts per billion. Note that 1 ppb - * is approximately 65.5 scaled_ppm. The PF shall clamp any - * frequency adjustment in VIRTCHNL_op_1588_ADJ_FREQ to +/- max_adj. - * Use of ppb in this field allows fitting the value into 4 bytes - * instead of potentially requiring 8 if scaled_ppm units were used. - * @tx_tstamp_idx: The Tx timestamp index to set in the transmit descriptor - * when requesting a timestamp for an outgoing packet. - * Reserved if VIRTCHNL_1588_PTP_CAP_TX_TSTAMP is not enabled. - * @n_ext_ts: Number of external timestamp functions available. Reserved - * if VIRTCHNL_1588_PTP_CAP_PIN_CFG is not enabled. - * @n_per_out: Number of periodic output functions available. Reserved if - * VIRTCHNL_1588_PTP_CAP_PIN_CFG is not enabled. - * @n_pins: Number of physical programmable pins able to be controlled. - * Reserved if VIRTCHNL_1588_PTP_CAP_PIN_CFG is not enabled. - * @tx_tstamp_format: Format of the Tx timestamps. Valid formats are defined - * by the virtchnl_ptp_tstamp enumeration. Note that Rx - * timestamps are tied to the descriptor format, and do not - * have a separate format field. - * @rsvd: Reserved bits for future extension. - * - * PTP capabilities - * - * VIRTCHNL_1588_PTP_CAP_TX_TSTAMP indicates that the VF can request transmit - * timestamps for packets in its transmit descriptors. If this is unset, - * transmit timestamp requests are ignored. Note that only one outstanding Tx - * timestamp request will be honored at a time. The PF shall handle receipt of - * the timestamp from the hardware, and will forward this to the VF by sending - * a VIRTCHNL_OP_1588_TX_TIMESTAMP message. - * - * VIRTCHNL_1588_PTP_CAP_RX_TSTAMP indicates that the VF receive queues have - * receive timestamps enabled in the flexible descriptors. Note that this - * requires a VF to also negotiate to enable advanced flexible descriptors in - * the receive path instead of the default legacy descriptor format. - * - * For a detailed description of the current Tx and Rx timestamp format, see - * the section on virtchnl_phc_tx_tstamp. Future extensions may indicate - * timestamp format in the capability structure. - * - * VIRTCHNL_1588_PTP_CAP_READ_PHC indicates that the VF may read the PHC time - * via the VIRTCHNL_OP_1588_PTP_GET_TIME command, or by directly reading PHC - * registers if VIRTCHNL_1588_PTP_CAP_PHC_REGS is also set. - * - * VIRTCHNL_1588_PTP_CAP_WRITE_PHC indicates that the VF may request updates - * to the PHC time via VIRTCHNL_OP_1588_PTP_SET_TIME, - * VIRTCHNL_OP_1588_PTP_ADJ_TIME, and VIRTCHNL_OP_1588_PTP_ADJ_FREQ. - * - * VIRTCHNL_1588_PTP_CAP_PHC_REGS indicates that the VF has direct access to - * certain PHC related registers, primarily for lower latency access to the - * PHC time. If this is set, the VF shall read the virtchnl_phc_regs section - * of the capabilities to determine the location of the clock registers. If - * this capability is not set, the entire 24 bytes of virtchnl_phc_regs is - * reserved as zero. Future extensions define alternative formats for this - * data, in which case they will be mutually exclusive with this capability. - * - * VIRTCHNL_1588_PTP_CAP_PIN_CFG indicates that the VF has the capability to - * control software defined pins. These pins can be assigned either as an - * input to timestamp external events, or as an output to cause a periodic - * signal output. - * - * Note that in the future, additional capability flags may be added which - * indicate additional extended support. All fields marked as reserved by this - * header will be set to zero. VF implementations should verify this to ensure - * that future extensions do not break compatibility. - */ -struct virtchnl_ptp_caps { - struct virtchnl_phc_regs phc_regs; - u32 caps; - s32 max_adj; - u8 tx_tstamp_idx; - u8 n_ext_ts; - u8 n_per_out; - u8 n_pins; - /* see enum virtchnl_ptp_tstamp_format */ - u8 tx_tstamp_format; - u8 rsvd[11]; -}; -VIRTCHNL_CHECK_STRUCT_LEN(48, virtchnl_ptp_caps); - -/** - * virtchnl_phc_time - * @time: PHC time in nanoseconds - * @rsvd: Reserved for future extension - * - * Structure sent with VIRTCHNL_OP_1588_PTP_SET_TIME and received with - * VIRTCHNL_OP_1588_PTP_GET_TIME. Contains the 64bits of PHC clock time in - * nanoseconds. - * - * VIRTCHNL_OP_1588_PTP_SET_TIME may be sent by the VF if - * VIRTCHNL_1588_PTP_CAP_WRITE_PHC is set. This will request that the PHC time - * be set to the requested value. This operation is non-atomic and thus does - * not adjust for the delay between request and completion. It is recommended - * that the VF use VIRTCHNL_OP_1588_PTP_ADJ_TIME and - * VIRTCHNL_OP_1588_PTP_ADJ_FREQ when possible to steer the PHC clock. - * - * VIRTCHNL_OP_1588_PTP_GET_TIME may be sent to request the current time of - * the PHC. This op is available in case direct access via the PHC registers - * is not available. - */ -struct virtchnl_phc_time { - u64 time; - u8 rsvd[8]; -}; -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_time); - -/** - * virtchnl_phc_adj_time - * @delta: offset requested to adjust clock by - * @rsvd: reserved for future extension - * - * Sent with VIRTCHNL_OP_1588_PTP_ADJ_TIME. Used to request an adjustment of - * the clock time by the provided delta, with negative values representing - * subtraction. VIRTCHNL_OP_1588_PTP_ADJ_TIME may not be sent unless - * VIRTCHNL_1588_PTP_CAP_WRITE_PHC is set. - * - * The atomicity of this operation is not guaranteed. The PF should perform an - * atomic update using appropriate mechanisms if possible. However, this is - * not guaranteed. - */ -struct virtchnl_phc_adj_time { - s64 delta; - u8 rsvd[8]; -}; -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_adj_time); - -/** - * virtchnl_phc_adj_freq - * @scaled_ppm: frequency adjustment represented in scaled parts per million - * @rsvd: Reserved for future extension - * - * Sent with the VIRTCHNL_OP_1588_PTP_ADJ_FREQ to request an adjustment to the - * clock frequency. The adjustment is in scaled_ppm, which is parts per - * million with a 16bit binary fractional portion. 1 part per billion is - * approximately 65.5 scaled_ppm. - * - * ppm = scaled_ppm / 2^16 - * - * ppb = scaled_ppm * 1000 / 2^16 or - * - * ppb = scaled_ppm * 125 / 2^13 - * - * The PF shall clamp any adjustment request to plus or minus the specified - * max_adj in the PTP capabilities. - * - * Requests for adjustment are always based off of nominal clock frequency and - * not compounding. To reset clock frequency, send a request with a scaled_ppm - * of 0. - */ -struct virtchnl_phc_adj_freq { - s64 scaled_ppm; - u8 rsvd[8]; -}; -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_adj_freq); - -/** - * virtchnl_phc_tx_stamp - * @tstamp: timestamp value - * @rsvd: Reserved for future extension - * - * Sent along with VIRTCHNL_OP_1588_PTP_TX_TIMESTAMP from the PF when a Tx - * timestamp for the index associated with this VF in the tx_tstamp_idx field - * is captured by hardware. - * - * If VIRTCHNL_1588_PTP_CAP_TX_TSTAMP is set, the VF may request a timestamp - * for a packet in its transmit context descriptor by setting the appropriate - * flag and setting the timestamp index provided by the PF. On transmission, - * the timestamp will be captured and sent to the PF. The PF will forward this - * timestamp to the VF via the VIRTCHNL_1588_PTP_CAP_TX_TSTAMP op. - * - * The timestamp format is defined by the tx_tstamp_format field of the - * virtchnl_ptp_caps structure. - */ -struct virtchnl_phc_tx_tstamp { - u64 tstamp; - u8 rsvd[8]; -}; -VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_tx_tstamp); - -enum virtchnl_phc_pin_func { - VIRTCHNL_PHC_PIN_FUNC_NONE = 0, /* Not assigned to any function */ - VIRTCHNL_PHC_PIN_FUNC_EXT_TS = 1, /* Assigned to external timestamp */ - VIRTCHNL_PHC_PIN_FUNC_PER_OUT = 2, /* Assigned to periodic output */ -}; - -/* Length of the pin configuration data. All pin configurations belong within - * the same union and *must* have this length in bytes. - */ -#define VIRTCHNL_PIN_CFG_LEN 64 - -/* virtchnl_phc_ext_ts_mode - * - * Mode of the external timestamp, indicating which edges of the input signal - * to timestamp. - */ -enum virtchnl_phc_ext_ts_mode { - VIRTCHNL_PHC_EXT_TS_NONE = 0, - VIRTCHNL_PHC_EXT_TS_RISING_EDGE = 1, - VIRTCHNL_PHC_EXT_TS_FALLING_EDGE = 2, - VIRTCHNL_PHC_EXT_TS_BOTH_EDGES = 3, -}; - -/** - * virtchnl_phc_ext_ts - * @mode: mode of external timestamp request - * @rsvd: reserved for future extension - * - * External timestamp configuration. Defines the configuration for this - * external timestamp function. - * - * If mode is VIRTCHNL_PHC_EXT_TS_NONE, the function is essentially disabled, - * timestamping nothing. - * - * If mode is VIRTCHNL_PHC_EXT_TS_RISING_EDGE, the function shall timestamp - * the rising edge of the input when it transitions from low to high signal. - * - * If mode is VIRTCHNL_PHC_EXT_TS_FALLING_EDGE, the function shall timestamp - * the falling edge of the input when it transitions from high to low signal. - * - * If mode is VIRTCHNL_PHC_EXT_TS_BOTH_EDGES, the function shall timestamp - * both the rising and falling edge of the signal whenever it changes. - * - * The PF shall return an error if the requested mode cannot be implemented on - * the function. - */ -struct virtchnl_phc_ext_ts { - u8 mode; /* see virtchnl_phc_ext_ts_mode */ - u8 rsvd[63]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(VIRTCHNL_PIN_CFG_LEN, virtchnl_phc_ext_ts); - -/* virtchnl_phc_per_out_flags - * - * Flags defining periodic output functionality. - */ -enum virtchnl_phc_per_out_flags { - VIRTCHNL_PHC_PER_OUT_PHASE_START = BIT(0), -}; - -/** - * virtchnl_phc_per_out - * @start: absolute start time (if VIRTCHNL_PHC_PER_OUT_PHASE_START unset) - * @phase: phase offset to start (if VIRTCHNL_PHC_PER_OUT_PHASE_START set) - * @period: time to complete a full clock cycle (low - > high -> low) - * @on: length of time the signal should stay high - * @flags: flags defining the periodic output operation. - * rsvd: reserved for future extension - * - * Configuration for a periodic output signal. Used to define the signal that - * should be generated on a given function. - * - * The period field determines the full length of the clock cycle, including - * both duration hold high transition and duration to hold low transition in - * nanoseconds. - * - * The on field determines how long the signal should remain high. For - * a traditional square wave clock that is on for some duration and off for - * the same duration, use an on length of precisely half the period. The duty - * cycle of the clock is period/on. - * - * If VIRTCHNL_PHC_PER_OUT_PHASE_START is unset, then the request is to start - * a clock an absolute time. This means that the clock should start precisely - * at the specified time in the start field. If the start time is in the past, - * then the periodic output should start at the next valid multiple of the - * period plus the start time: - * - * new_start = (n * period) + start - * (choose n such that new start is in the future) - * - * Note that the PF should not reject a start time in the past because it is - * possible that such a start time was valid when the request was made, but - * became invalid due to delay in programming the pin. - * - * If VIRTCHNL_PHC_PER_OUT_PHASE_START is set, then the request is to start - * the next multiple of the period plus the phase offset. The phase must be - * less than the period. In this case, the clock should start as soon possible - * at the next available multiple of the period. To calculate a start time - * when programming this mode, use: - * - * start = (n * period) + phase - * (choose n such that start is in the future) - * - * A period of zero should be treated as a request to disable the clock - * output. - */ -struct virtchnl_phc_per_out { - union { - u64 start; - u64 phase; - }; - u64 period; - u64 on; - u32 flags; - u8 rsvd[36]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(VIRTCHNL_PIN_CFG_LEN, virtchnl_phc_per_out); - -/* virtchnl_phc_pin_cfg_flags - * - * Definition of bits in the flags field of the virtchnl_phc_pin_cfg - * structure. - */ -enum virtchnl_phc_pin_cfg_flags { - /* Valid for VIRTCHNL_OP_1588_PTP_SET_PIN_CFG. If set, indicates this - * is a request to verify if the function can be assigned to the - * provided pin. In this case, the ext_ts and per_out fields are - * ignored, and the PF response must be an error if the pin cannot be - * assigned to that function index. - */ - VIRTCHNL_PHC_PIN_CFG_VERIFY = BIT(0), -}; - -/** - * virtchnl_phc_set_pin - * @pin_index: The pin to get or set - * @func: the function type the pin is assigned to - * @func_index: the index of the function the pin is assigned to - * @ext_ts: external timestamp configuration - * @per_out: periodic output configuration - * @rsvd1: Reserved for future extension - * @rsvd2: Reserved for future extension - * - * Sent along with the VIRTCHNL_OP_1588_PTP_SET_PIN_CFG op. - * - * The VF issues a VIRTCHNL_OP_1588_PTP_SET_PIN_CFG to assign the pin to one - * of the functions. It must set the pin_index field, the func field, and - * the func_index field. The pin_index must be less than n_pins, and the - * func_index must be less than the n_ext_ts or n_per_out depending on which - * function type is selected. If func is for an external timestamp, the - * ext_ts field must be filled in with the desired configuration. Similarly, - * if the function is for a periodic output, the per_out field must be - * configured. - * - * If the VIRTCHNL_PHC_PIN_CFG_VERIFY bit of the flag field is set, this is - * a request only to verify the configuration, not to set it. In this case, - * the PF should simply report an error if the requested pin cannot be - * assigned to the requested function. This allows VF to determine whether or - * not a given function can be assigned to a specific pin. Other flag bits are - * currently reserved and must be verified as zero on both sides. They may be - * extended in the future. - */ -struct virtchnl_phc_set_pin { - u32 flags; /* see virtchnl_phc_pin_cfg_flags */ - u8 pin_index; - u8 func; /* see virtchnl_phc_pin_func */ - u8 func_index; - u8 rsvd1; - union { - struct virtchnl_phc_ext_ts ext_ts; - struct virtchnl_phc_per_out per_out; - }; - u8 rsvd2[8]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(80, virtchnl_phc_set_pin); - -/** - * virtchnl_phc_pin - * @pin_index: The pin to get or set - * @func: the function type the pin is assigned to - * @func_index: the index of the function the pin is assigned to - * @rsvd: Reserved for future extension - * @name: human readable pin name, supplied by PF on GET_PIN_CFGS - * - * Sent by the PF as part of the VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS response. - * - * The VF issues a VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS request to the PF in - * order to obtain the current pin configuration for all of the pins that were - * assigned to this VF. - * - * This structure details the pin configuration state, including a pin name - * and which function is assigned to the pin currently. - */ -struct virtchnl_phc_pin { - u8 pin_index; - u8 func; /* see virtchnl_phc_pin_func */ - u8 func_index; - u8 rsvd[5]; - char name[64]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_phc_pin); - -/** - * virtchnl_phc_pin_cfg - * @len: length of the variable pin config array - * @pins: variable length pin configuration array - * - * Variable structure sent by the PF in reply to - * VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS. The VF does not send this structure with - * its request of the operation. - * - * It is possible that the PF may need to send more pin configuration data - * than can be sent in one virtchnl message. To handle this, the PF should - * issue multiple VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS responses. Each response - * will indicate the number of pins it covers. The VF should be ready to wait - * for multiple responses until it has received a total length equal to the - * number of n_pins negotiated during extended PTP capabilities exchange. - */ -struct virtchnl_phc_get_pins { - u8 len; - u8 rsvd[7]; - struct virtchnl_phc_pin pins[1]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(80, virtchnl_phc_get_pins); - -/** - * virtchnl_phc_ext_stamp - * @tstamp: timestamp value - * @tstamp_rsvd: Reserved for future extension of the timestamp value. - * @tstamp_format: format of the timstamp - * @func_index: external timestamp function this timestamp is for - * @rsvd2: Reserved for future extension - * - * Sent along with the VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP from the PF when an - * external timestamp function is triggered. - * - * This will be sent only if one of the external timestamp functions is - * configured by the VF, and is only valid if VIRTCHNL_1588_PTP_CAP_PIN_CFG is - * negotiated with the PF. - * - * The timestamp format is defined by the tstamp_format field using the - * virtchnl_ptp_tstamp_format enumeration. The tstamp_rsvd field is - * exclusively reserved for possible future variants of the timestamp format, - * and its access will be controlled by the tstamp_format field. - */ -struct virtchnl_phc_ext_tstamp { - u64 tstamp; - u8 tstamp_rsvd[8]; - u8 tstamp_format; - u8 func_index; - u8 rsvd2[6]; -}; - -VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_phc_ext_tstamp); - -/* Since VF messages are limited by u16 size, precalculate the maximum possible - * values of nested elements in virtchnl structures that virtual channel can - * possibly handle in a single message. - */ -enum virtchnl_vector_limits { - VIRTCHNL_OP_CONFIG_VSI_QUEUES_MAX = - ((u16)(~0) - sizeof(struct virtchnl_vsi_queue_config_info)) / - sizeof(struct virtchnl_queue_pair_info), - - VIRTCHNL_OP_CONFIG_IRQ_MAP_MAX = - ((u16)(~0) - sizeof(struct virtchnl_irq_map_info)) / - sizeof(struct virtchnl_vector_map), - - VIRTCHNL_OP_ADD_DEL_ETH_ADDR_MAX = - ((u16)(~0) - sizeof(struct virtchnl_ether_addr_list)) / - sizeof(struct virtchnl_ether_addr), - - VIRTCHNL_OP_ADD_DEL_VLAN_MAX = - ((u16)(~0) - sizeof(struct virtchnl_vlan_filter_list)) / - sizeof(u16), - - - VIRTCHNL_OP_ENABLE_CHANNELS_MAX = - ((u16)(~0) - sizeof(struct virtchnl_tc_info)) / - sizeof(struct virtchnl_channel_info), - - VIRTCHNL_OP_ENABLE_DISABLE_DEL_QUEUES_V2_MAX = - ((u16)(~0) - sizeof(struct virtchnl_del_ena_dis_queues)) / - sizeof(struct virtchnl_queue_chunk), - - VIRTCHNL_OP_MAP_UNMAP_QUEUE_VECTOR_MAX = - ((u16)(~0) - sizeof(struct virtchnl_queue_vector_maps)) / - sizeof(struct virtchnl_queue_vector), - - VIRTCHNL_OP_ADD_DEL_VLAN_V2_MAX = - ((u16)(~0) - sizeof(struct virtchnl_vlan_filter_list_v2)) / - sizeof(struct virtchnl_vlan_filter), -}; - -/** - * virtchnl_vc_validate_vf_msg - * @ver: Virtchnl version info - * @v_opcode: Opcode for the message - * @msg: pointer to the msg buffer - * @msglen: msg length - * - * validate msg format against struct for each opcode - */ -static inline int -virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, - u8 *msg, u16 msglen) -{ - bool err_msg_format = false; - u32 valid_len = 0; - - /* Validate message length. */ - switch (v_opcode) { - case VIRTCHNL_OP_VERSION: - valid_len = sizeof(struct virtchnl_version_info); - break; - case VIRTCHNL_OP_RESET_VF: - break; - case VIRTCHNL_OP_GET_VF_RESOURCES: - if (VF_IS_V11(ver)) - valid_len = sizeof(u32); - break; - case VIRTCHNL_OP_CONFIG_TX_QUEUE: - valid_len = sizeof(struct virtchnl_txq_info); - break; - case VIRTCHNL_OP_CONFIG_RX_QUEUE: - valid_len = sizeof(struct virtchnl_rxq_info); - break; - case VIRTCHNL_OP_CONFIG_VSI_QUEUES: - valid_len = sizeof(struct virtchnl_vsi_queue_config_info); - if (msglen >= valid_len) { - struct virtchnl_vsi_queue_config_info *vqc = - (struct virtchnl_vsi_queue_config_info *)msg; - - if (vqc->num_queue_pairs == 0 || vqc->num_queue_pairs > - VIRTCHNL_OP_CONFIG_VSI_QUEUES_MAX) { - err_msg_format = true; - break; - } - - valid_len += (vqc->num_queue_pairs * - sizeof(struct - virtchnl_queue_pair_info)); - } - break; - case VIRTCHNL_OP_CONFIG_IRQ_MAP: - valid_len = sizeof(struct virtchnl_irq_map_info); - if (msglen >= valid_len) { - struct virtchnl_irq_map_info *vimi = - (struct virtchnl_irq_map_info *)msg; - - if (vimi->num_vectors == 0 || vimi->num_vectors > - VIRTCHNL_OP_CONFIG_IRQ_MAP_MAX) { - err_msg_format = true; - break; - } - - valid_len += (vimi->num_vectors * - sizeof(struct virtchnl_vector_map)); - } - break; - case VIRTCHNL_OP_ENABLE_QUEUES: - case VIRTCHNL_OP_DISABLE_QUEUES: - valid_len = sizeof(struct virtchnl_queue_select); - break; - case VIRTCHNL_OP_GET_MAX_RSS_QREGION: - break; - case VIRTCHNL_OP_ADD_ETH_ADDR: - case VIRTCHNL_OP_DEL_ETH_ADDR: - valid_len = sizeof(struct virtchnl_ether_addr_list); - if (msglen >= valid_len) { - struct virtchnl_ether_addr_list *veal = - (struct virtchnl_ether_addr_list *)msg; - - if (veal->num_elements == 0 || veal->num_elements > - VIRTCHNL_OP_ADD_DEL_ETH_ADDR_MAX) { - err_msg_format = true; - break; - } - - valid_len += veal->num_elements * - sizeof(struct virtchnl_ether_addr); - } - break; - case VIRTCHNL_OP_ADD_VLAN: - case VIRTCHNL_OP_DEL_VLAN: - valid_len = sizeof(struct virtchnl_vlan_filter_list); - if (msglen >= valid_len) { - struct virtchnl_vlan_filter_list *vfl = - (struct virtchnl_vlan_filter_list *)msg; - - if (vfl->num_elements == 0 || vfl->num_elements > - VIRTCHNL_OP_ADD_DEL_VLAN_MAX) { - err_msg_format = true; - break; - } - - valid_len += vfl->num_elements * sizeof(u16); - } - break; - case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: - valid_len = sizeof(struct virtchnl_promisc_info); - break; - case VIRTCHNL_OP_GET_STATS: - valid_len = sizeof(struct virtchnl_queue_select); - break; - case VIRTCHNL_OP_CONFIG_RSS_KEY: - valid_len = sizeof(struct virtchnl_rss_key); - if (msglen >= valid_len) { - struct virtchnl_rss_key *vrk = - (struct virtchnl_rss_key *)msg; - - if (vrk->key_len == 0) { - /* zero length is allowed as input */ - break; - } - - valid_len += vrk->key_len - 1; - } - break; - case VIRTCHNL_OP_CONFIG_RSS_LUT: - valid_len = sizeof(struct virtchnl_rss_lut); - if (msglen >= valid_len) { - struct virtchnl_rss_lut *vrl = - (struct virtchnl_rss_lut *)msg; - - if (vrl->lut_entries == 0) { - /* zero entries is allowed as input */ - break; - } - - valid_len += vrl->lut_entries - 1; - } - break; - case VIRTCHNL_OP_GET_RSS_HENA_CAPS: - break; - case VIRTCHNL_OP_SET_RSS_HENA: - valid_len = sizeof(struct virtchnl_rss_hena); - break; - case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING: - case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING: - break; - case VIRTCHNL_OP_REQUEST_QUEUES: - valid_len = sizeof(struct virtchnl_vf_res_request); - break; - case VIRTCHNL_OP_ENABLE_CHANNELS: - valid_len = sizeof(struct virtchnl_tc_info); - if (msglen >= valid_len) { - struct virtchnl_tc_info *vti = - (struct virtchnl_tc_info *)msg; - - if (vti->num_tc == 0 || vti->num_tc > - VIRTCHNL_OP_ENABLE_CHANNELS_MAX) { - err_msg_format = true; - break; - } - - valid_len += (vti->num_tc - 1) * - sizeof(struct virtchnl_channel_info); - } - break; - case VIRTCHNL_OP_DISABLE_CHANNELS: - break; - case VIRTCHNL_OP_ADD_CLOUD_FILTER: - case VIRTCHNL_OP_DEL_CLOUD_FILTER: - valid_len = sizeof(struct virtchnl_filter); - break; - case VIRTCHNL_OP_ADD_RSS_CFG: - case VIRTCHNL_OP_DEL_RSS_CFG: - valid_len = sizeof(struct virtchnl_rss_cfg); - break; - case VIRTCHNL_OP_ADD_FDIR_FILTER: - valid_len = sizeof(struct virtchnl_fdir_add); - break; - case VIRTCHNL_OP_DEL_FDIR_FILTER: - valid_len = sizeof(struct virtchnl_fdir_del); - break; - case VIRTCHNL_OP_GET_QOS_CAPS: - break; - case VIRTCHNL_OP_CONFIG_QUEUE_TC_MAP: - valid_len = sizeof(struct virtchnl_queue_tc_mapping); - if (msglen >= valid_len) { - struct virtchnl_queue_tc_mapping *q_tc = - (struct virtchnl_queue_tc_mapping *)msg; - if (q_tc->num_tc == 0) { - err_msg_format = true; - break; - } - valid_len += (q_tc->num_tc - 1) * - sizeof(q_tc->tc[0]); - } - break; - case VIRTCHNL_OP_CONFIG_QUEUE_BW: - valid_len = sizeof(struct virtchnl_queues_bw_cfg); - if (msglen >= valid_len) { - struct virtchnl_queues_bw_cfg *q_bw = - (struct virtchnl_queues_bw_cfg *)msg; - if (q_bw->num_queues == 0) { - err_msg_format = true; - break; - } - valid_len += (q_bw->num_queues - 1) * - sizeof(q_bw->cfg[0]); - } - break; - case VIRTCHNL_OP_CONFIG_QUANTA: - valid_len = sizeof(struct virtchnl_quanta_cfg); - if (msglen >= valid_len) { - struct virtchnl_quanta_cfg *q_quanta = - (struct virtchnl_quanta_cfg *)msg; - if (q_quanta->quanta_size == 0 || - q_quanta->queue_select.num_queues == 0) { - err_msg_format = true; - break; - } - } - break; - case VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS: - break; - case VIRTCHNL_OP_ADD_VLAN_V2: - case VIRTCHNL_OP_DEL_VLAN_V2: - valid_len = sizeof(struct virtchnl_vlan_filter_list_v2); - if (msglen >= valid_len) { - struct virtchnl_vlan_filter_list_v2 *vfl = - (struct virtchnl_vlan_filter_list_v2 *)msg; - - if (vfl->num_elements == 0 || vfl->num_elements > - VIRTCHNL_OP_ADD_DEL_VLAN_V2_MAX) { - err_msg_format = true; - break; - } - - valid_len += (vfl->num_elements - 1) * - sizeof(struct virtchnl_vlan_filter); - } - break; - case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2: - case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2: - case VIRTCHNL_OP_ENABLE_VLAN_INSERTION_V2: - case VIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2: - case VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2: - case VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2: - valid_len = sizeof(struct virtchnl_vlan_setting); - break; - case VIRTCHNL_OP_1588_PTP_GET_CAPS: - valid_len = sizeof(struct virtchnl_ptp_caps); - break; - case VIRTCHNL_OP_1588_PTP_GET_TIME: - case VIRTCHNL_OP_1588_PTP_SET_TIME: - valid_len = sizeof(struct virtchnl_phc_time); - break; - case VIRTCHNL_OP_1588_PTP_ADJ_TIME: - valid_len = sizeof(struct virtchnl_phc_adj_time); - break; - case VIRTCHNL_OP_1588_PTP_ADJ_FREQ: - valid_len = sizeof(struct virtchnl_phc_adj_freq); - break; - case VIRTCHNL_OP_1588_PTP_TX_TIMESTAMP: - valid_len = sizeof(struct virtchnl_phc_tx_tstamp); - break; - case VIRTCHNL_OP_1588_PTP_SET_PIN_CFG: - valid_len = sizeof(struct virtchnl_phc_set_pin); - break; - case VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS: - break; - case VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP: - valid_len = sizeof(struct virtchnl_phc_ext_tstamp); - break; - case VIRTCHNL_OP_ENABLE_QUEUES_V2: - case VIRTCHNL_OP_DISABLE_QUEUES_V2: - valid_len = sizeof(struct virtchnl_del_ena_dis_queues); - if (msglen >= valid_len) { - struct virtchnl_del_ena_dis_queues *qs = - (struct virtchnl_del_ena_dis_queues *)msg; - if (qs->chunks.num_chunks == 0 || - qs->chunks.num_chunks > VIRTCHNL_OP_ENABLE_DISABLE_DEL_QUEUES_V2_MAX) { - err_msg_format = true; - break; - } - valid_len += (qs->chunks.num_chunks - 1) * - sizeof(struct virtchnl_queue_chunk); - } - break; - case VIRTCHNL_OP_MAP_QUEUE_VECTOR: - valid_len = sizeof(struct virtchnl_queue_vector_maps); - if (msglen >= valid_len) { - struct virtchnl_queue_vector_maps *v_qp = - (struct virtchnl_queue_vector_maps *)msg; - if (v_qp->num_qv_maps == 0 || - v_qp->num_qv_maps > VIRTCHNL_OP_MAP_UNMAP_QUEUE_VECTOR_MAX) { - err_msg_format = true; - break; - } - valid_len += (v_qp->num_qv_maps - 1) * - sizeof(struct virtchnl_queue_vector); - } - break; - /* These are always errors coming from the VF. */ - case VIRTCHNL_OP_EVENT: - case VIRTCHNL_OP_UNKNOWN: - default: - return VIRTCHNL_STATUS_ERR_PARAM; - } - /* few more checks */ - if (err_msg_format || valid_len != msglen) - return VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH; - - return 0; -} -#endif /* _VIRTCHNL_H_ */ diff --git a/drivers/common/idpf/base/virtchnl_inline_ipsec.h b/drivers/common/idpf/base/virtchnl_inline_ipsec.h deleted file mode 100644 index e19043ac47..0000000000 --- a/drivers/common/idpf/base/virtchnl_inline_ipsec.h +++ /dev/null @@ -1,567 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation - */ - -#ifndef _VIRTCHNL_INLINE_IPSEC_H_ -#define _VIRTCHNL_INLINE_IPSEC_H_ - -#define VIRTCHNL_IPSEC_MAX_CRYPTO_CAP_NUM 3 -#define VIRTCHNL_IPSEC_MAX_ALGO_CAP_NUM 16 -#define VIRTCHNL_IPSEC_MAX_TX_DESC_NUM 128 -#define VIRTCHNL_IPSEC_MAX_CRYPTO_ITEM_NUMBER 2 -#define VIRTCHNL_IPSEC_MAX_KEY_LEN 128 -#define VIRTCHNL_IPSEC_MAX_SA_DESTROY_NUM 8 -#define VIRTCHNL_IPSEC_SA_DESTROY 0 -#define VIRTCHNL_IPSEC_BROADCAST_VFID 0xFFFFFFFF -#define VIRTCHNL_IPSEC_INVALID_REQ_ID 0xFFFF -#define VIRTCHNL_IPSEC_INVALID_SA_CFG_RESP 0xFFFFFFFF -#define VIRTCHNL_IPSEC_INVALID_SP_CFG_RESP 0xFFFFFFFF - -/* crypto type */ -#define VIRTCHNL_AUTH 1 -#define VIRTCHNL_CIPHER 2 -#define VIRTCHNL_AEAD 3 - -/* caps enabled */ -#define VIRTCHNL_IPSEC_ESN_ENA BIT(0) -#define VIRTCHNL_IPSEC_UDP_ENCAP_ENA BIT(1) -#define VIRTCHNL_IPSEC_SA_INDEX_SW_ENA BIT(2) -#define VIRTCHNL_IPSEC_AUDIT_ENA BIT(3) -#define VIRTCHNL_IPSEC_BYTE_LIMIT_ENA BIT(4) -#define VIRTCHNL_IPSEC_DROP_ON_AUTH_FAIL_ENA BIT(5) -#define VIRTCHNL_IPSEC_ARW_CHECK_ENA BIT(6) -#define VIRTCHNL_IPSEC_24BIT_SPI_ENA BIT(7) - -/* algorithm type */ -/* Hash Algorithm */ -#define VIRTCHNL_HASH_NO_ALG 0 /* NULL algorithm */ -#define VIRTCHNL_AES_CBC_MAC 1 /* AES-CBC-MAC algorithm */ -#define VIRTCHNL_AES_CMAC 2 /* AES CMAC algorithm */ -#define VIRTCHNL_AES_GMAC 3 /* AES GMAC algorithm */ -#define VIRTCHNL_AES_XCBC_MAC 4 /* AES XCBC algorithm */ -#define VIRTCHNL_MD5_HMAC 5 /* HMAC using MD5 algorithm */ -#define VIRTCHNL_SHA1_HMAC 6 /* HMAC using 128 bit SHA algorithm */ -#define VIRTCHNL_SHA224_HMAC 7 /* HMAC using 224 bit SHA algorithm */ -#define VIRTCHNL_SHA256_HMAC 8 /* HMAC using 256 bit SHA algorithm */ -#define VIRTCHNL_SHA384_HMAC 9 /* HMAC using 384 bit SHA algorithm */ -#define VIRTCHNL_SHA512_HMAC 10 /* HMAC using 512 bit SHA algorithm */ -#define VIRTCHNL_SHA3_224_HMAC 11 /* HMAC using 224 bit SHA3 algorithm */ -#define VIRTCHNL_SHA3_256_HMAC 12 /* HMAC using 256 bit SHA3 algorithm */ -#define VIRTCHNL_SHA3_384_HMAC 13 /* HMAC using 384 bit SHA3 algorithm */ -#define VIRTCHNL_SHA3_512_HMAC 14 /* HMAC using 512 bit SHA3 algorithm */ -/* Cipher Algorithm */ -#define VIRTCHNL_CIPHER_NO_ALG 15 /* NULL algorithm */ -#define VIRTCHNL_3DES_CBC 16 /* Triple DES algorithm in CBC mode */ -#define VIRTCHNL_AES_CBC 17 /* AES algorithm in CBC mode */ -#define VIRTCHNL_AES_CTR 18 /* AES algorithm in Counter mode */ -/* AEAD Algorithm */ -#define VIRTCHNL_AES_CCM 19 /* AES algorithm in CCM mode */ -#define VIRTCHNL_AES_GCM 20 /* AES algorithm in GCM mode */ -#define VIRTCHNL_CHACHA20_POLY1305 21 /* algorithm of ChaCha20-Poly1305 */ - -/* protocol type */ -#define VIRTCHNL_PROTO_ESP 1 -#define VIRTCHNL_PROTO_AH 2 -#define VIRTCHNL_PROTO_RSVD1 3 - -/* sa mode */ -#define VIRTCHNL_SA_MODE_TRANSPORT 1 -#define VIRTCHNL_SA_MODE_TUNNEL 2 -#define VIRTCHNL_SA_MODE_TRAN_TUN 3 -#define VIRTCHNL_SA_MODE_UNKNOWN 4 - -/* sa direction */ -#define VIRTCHNL_DIR_INGRESS 1 -#define VIRTCHNL_DIR_EGRESS 2 -#define VIRTCHNL_DIR_INGRESS_EGRESS 3 - -/* sa termination */ -#define VIRTCHNL_TERM_SOFTWARE 1 -#define VIRTCHNL_TERM_HARDWARE 2 - -/* sa ip type */ -#define VIRTCHNL_IPV4 1 -#define VIRTCHNL_IPV6 2 - -/* for virtchnl_ipsec_resp */ -enum inline_ipsec_resp { - INLINE_IPSEC_SUCCESS = 0, - INLINE_IPSEC_FAIL = -1, - INLINE_IPSEC_ERR_FIFO_FULL = -2, - INLINE_IPSEC_ERR_NOT_READY = -3, - INLINE_IPSEC_ERR_VF_DOWN = -4, - INLINE_IPSEC_ERR_INVALID_PARAMS = -5, - INLINE_IPSEC_ERR_NO_MEM = -6, -}; - -/* Detailed opcodes for DPDK and IPsec use */ -enum inline_ipsec_ops { - INLINE_IPSEC_OP_GET_CAP = 0, - INLINE_IPSEC_OP_GET_STATUS = 1, - INLINE_IPSEC_OP_SA_CREATE = 2, - INLINE_IPSEC_OP_SA_UPDATE = 3, - INLINE_IPSEC_OP_SA_DESTROY = 4, - INLINE_IPSEC_OP_SP_CREATE = 5, - INLINE_IPSEC_OP_SP_DESTROY = 6, - INLINE_IPSEC_OP_SA_READ = 7, - INLINE_IPSEC_OP_EVENT = 8, - INLINE_IPSEC_OP_RESP = 9, -}; - -#pragma pack(1) -/* Not all valid, if certain field is invalid, set 1 for all bits */ -struct virtchnl_algo_cap { - u32 algo_type; - - u16 block_size; - - u16 min_key_size; - u16 max_key_size; - u16 inc_key_size; - - u16 min_iv_size; - u16 max_iv_size; - u16 inc_iv_size; - - u16 min_digest_size; - u16 max_digest_size; - u16 inc_digest_size; - - u16 min_aad_size; - u16 max_aad_size; - u16 inc_aad_size; -}; -#pragma pack() - -/* vf record the capability of crypto from the virtchnl */ -struct virtchnl_sym_crypto_cap { - u8 crypto_type; - u8 algo_cap_num; - struct virtchnl_algo_cap algo_cap_list[VIRTCHNL_IPSEC_MAX_ALGO_CAP_NUM]; -}; - -/* VIRTCHNL_OP_GET_IPSEC_CAP - * VF pass virtchnl_ipsec_cap to PF - * and PF return capability of ipsec from virtchnl. - */ -#pragma pack(1) -struct virtchnl_ipsec_cap { - /* max number of SA per VF */ - u16 max_sa_num; - - /* IPsec SA Protocol - value ref VIRTCHNL_PROTO_XXX */ - u8 virtchnl_protocol_type; - - /* IPsec SA Mode - value ref VIRTCHNL_SA_MODE_XXX */ - u8 virtchnl_sa_mode; - - /* IPSec SA Direction - value ref VIRTCHNL_DIR_XXX */ - u8 virtchnl_direction; - - /* termination mode - value ref VIRTCHNL_TERM_XXX */ - u8 termination_mode; - - /* number of supported crypto capability */ - u8 crypto_cap_num; - - /* descriptor ID */ - u16 desc_id; - - /* capabilities enabled - value ref VIRTCHNL_IPSEC_XXX_ENA */ - u32 caps_enabled; - - /* crypto capabilities */ - struct virtchnl_sym_crypto_cap cap[VIRTCHNL_IPSEC_MAX_CRYPTO_CAP_NUM]; -}; - -/* configuration of crypto function */ -struct virtchnl_ipsec_crypto_cfg_item { - u8 crypto_type; - - u32 algo_type; - - /* Length of valid IV data. */ - u16 iv_len; - - /* Length of digest */ - u16 digest_len; - - /* SA salt */ - u32 salt; - - /* The length of the symmetric key */ - u16 key_len; - - /* key data buffer */ - u8 key_data[VIRTCHNL_IPSEC_MAX_KEY_LEN]; -}; -#pragma pack() - -struct virtchnl_ipsec_sym_crypto_cfg { - struct virtchnl_ipsec_crypto_cfg_item - items[VIRTCHNL_IPSEC_MAX_CRYPTO_ITEM_NUMBER]; -}; - -#pragma pack(1) -/* VIRTCHNL_OP_IPSEC_SA_CREATE - * VF send this SA configuration to PF using virtchnl; - * PF create SA as configuration and PF driver will return - * an unique index (sa_idx) for the created SA. - */ -struct virtchnl_ipsec_sa_cfg { - /* IPsec SA Protocol - AH/ESP */ - u8 virtchnl_protocol_type; - - /* termination mode - value ref VIRTCHNL_TERM_XXX */ - u8 virtchnl_termination; - - /* type of outer IP - IPv4/IPv6 */ - u8 virtchnl_ip_type; - - /* type of esn - !0:enable/0:disable */ - u8 esn_enabled; - - /* udp encap - !0:enable/0:disable */ - u8 udp_encap_enabled; - - /* IPSec SA Direction - value ref VIRTCHNL_DIR_XXX */ - u8 virtchnl_direction; - - /* reserved */ - u8 reserved1; - - /* SA security parameter index */ - u32 spi; - - /* outer src ip address */ - u8 src_addr[16]; - - /* outer dst ip address */ - u8 dst_addr[16]; - - /* SPD reference. Used to link an SA with its policy. - * PF drivers may ignore this field. - */ - u16 spd_ref; - - /* high 32 bits of esn */ - u32 esn_hi; - - /* low 32 bits of esn */ - u32 esn_low; - - /* When enabled, sa_index must be valid */ - u8 sa_index_en; - - /* SA index when sa_index_en is true */ - u32 sa_index; - - /* auditing mode - enable/disable */ - u8 audit_en; - - /* lifetime byte limit - enable/disable - * When enabled, byte_limit_hard and byte_limit_soft - * must be valid. - */ - u8 byte_limit_en; - - /* hard byte limit count */ - u64 byte_limit_hard; - - /* soft byte limit count */ - u64 byte_limit_soft; - - /* drop on authentication failure - enable/disable */ - u8 drop_on_auth_fail_en; - - /* anti-reply window check - enable/disable - * When enabled, arw_size must be valid. - */ - u8 arw_check_en; - - /* size of arw window, offset by 1. Setting to 0 - * represents ARW window size of 1. Setting to 127 - * represents ARW window size of 128 - */ - u8 arw_size; - - /* no ip offload mode - enable/disable - * When enabled, ip type and address must not be valid. - */ - u8 no_ip_offload_en; - - /* SA Domain. Used to logical separate an SADB into groups. - * PF drivers supporting a single group ignore this field. - */ - u16 sa_domain; - - /* crypto configuration */ - struct virtchnl_ipsec_sym_crypto_cfg crypto_cfg; -}; -#pragma pack() - -/* VIRTCHNL_OP_IPSEC_SA_UPDATE - * VF send configuration of index of SA to PF - * PF will update SA according to configuration - */ -struct virtchnl_ipsec_sa_update { - u32 sa_index; /* SA to update */ - u32 esn_hi; /* high 32 bits of esn */ - u32 esn_low; /* low 32 bits of esn */ -}; - -#pragma pack(1) -/* VIRTCHNL_OP_IPSEC_SA_DESTROY - * VF send configuration of index of SA to PF - * PF will destroy SA according to configuration - * flag bitmap indicate all SA or just selected SA will - * be destroyed - */ -struct virtchnl_ipsec_sa_destroy { - /* All zero bitmap indicates all SA will be destroyed. - * Non-zero bitmap indicates the selected SA in - * array sa_index will be destroyed. - */ - u8 flag; - - /* selected SA index */ - u32 sa_index[VIRTCHNL_IPSEC_MAX_SA_DESTROY_NUM]; -}; - -/* VIRTCHNL_OP_IPSEC_SA_READ - * VF send this SA configuration to PF using virtchnl; - * PF read SA and will return configuration for the created SA. - */ -struct virtchnl_ipsec_sa_read { - /* SA valid - invalid/valid */ - u8 valid; - - /* SA active - inactive/active */ - u8 active; - - /* SA SN rollover - not_rollover/rollover */ - u8 sn_rollover; - - /* IPsec SA Protocol - AH/ESP */ - u8 virtchnl_protocol_type; - - /* termination mode - value ref VIRTCHNL_TERM_XXX */ - u8 virtchnl_termination; - - /* auditing mode - enable/disable */ - u8 audit_en; - - /* lifetime byte limit - enable/disable - * When set to limit, byte_limit_hard and byte_limit_soft - * must be valid. - */ - u8 byte_limit_en; - - /* hard byte limit count */ - u64 byte_limit_hard; - - /* soft byte limit count */ - u64 byte_limit_soft; - - /* drop on authentication failure - enable/disable */ - u8 drop_on_auth_fail_en; - - /* anti-replay window check - enable/disable - * When set to check, arw_size, arw_top, and arw must be valid - */ - u8 arw_check_en; - - /* size of arw window, offset by 1. Setting to 0 - * represents ARW window size of 1. Setting to 127 - * represents ARW window size of 128 - */ - u8 arw_size; - - /* reserved */ - u8 reserved1; - - /* top of anti-replay-window */ - u64 arw_top; - - /* anti-replay-window */ - u8 arw[16]; - - /* packets processed */ - u64 packets_processed; - - /* bytes processed */ - u64 bytes_processed; - - /* packets dropped */ - u32 packets_dropped; - - /* authentication failures */ - u32 auth_fails; - - /* ARW check failures */ - u32 arw_fails; - - /* type of esn - enable/disable */ - u8 esn; - - /* IPSec SA Direction - value ref VIRTCHNL_DIR_XXX */ - u8 virtchnl_direction; - - /* SA security parameter index */ - u32 spi; - - /* SA salt */ - u32 salt; - - /* high 32 bits of esn */ - u32 esn_hi; - - /* low 32 bits of esn */ - u32 esn_low; - - /* SA Domain. Used to logical separate an SADB into groups. - * PF drivers supporting a single group ignore this field. - */ - u16 sa_domain; - - /* SPD reference. Used to link an SA with its policy. - * PF drivers may ignore this field. - */ - u16 spd_ref; - - /* crypto configuration. Salt and keys are set to 0 */ - struct virtchnl_ipsec_sym_crypto_cfg crypto_cfg; -}; -#pragma pack() - -/* Add allowlist entry in IES */ -struct virtchnl_ipsec_sp_cfg { - u32 spi; - u32 dip[4]; - - /* Drop frame if true or redirect to QAT if false. */ - u8 drop; - - /* Congestion domain. For future use. */ - u8 cgd; - - /* 0 for IPv4 table, 1 for IPv6 table. */ - u8 table_id; - - /* Set TC (congestion domain) if true. For future use. */ - u8 set_tc; - - /* 0 for NAT-T unsupported, 1 for NAT-T supported */ - u8 is_udp; - - /* reserved */ - u8 reserved; - - /* NAT-T UDP port number. Only valid in case NAT-T supported */ - u16 udp_port; -}; - -#pragma pack(1) -/* Delete allowlist entry in IES */ -struct virtchnl_ipsec_sp_destroy { - /* 0 for IPv4 table, 1 for IPv6 table. */ - u8 table_id; - u32 rule_id; -}; -#pragma pack() - -/* Response from IES to allowlist operations */ -struct virtchnl_ipsec_sp_cfg_resp { - u32 rule_id; -}; - -struct virtchnl_ipsec_sa_cfg_resp { - u32 sa_handle; -}; - -#define INLINE_IPSEC_EVENT_RESET 0x1 -#define INLINE_IPSEC_EVENT_CRYPTO_ON 0x2 -#define INLINE_IPSEC_EVENT_CRYPTO_OFF 0x4 - -struct virtchnl_ipsec_event { - u32 ipsec_event_data; -}; - -#define INLINE_IPSEC_STATUS_AVAILABLE 0x1 -#define INLINE_IPSEC_STATUS_UNAVAILABLE 0x2 - -struct virtchnl_ipsec_status { - u32 status; -}; - -struct virtchnl_ipsec_resp { - u32 resp; -}; - -/* Internal message descriptor for VF <-> IPsec communication */ -struct inline_ipsec_msg { - u16 ipsec_opcode; - u16 req_id; - - union { - /* IPsec request */ - struct virtchnl_ipsec_sa_cfg sa_cfg[0]; - struct virtchnl_ipsec_sp_cfg sp_cfg[0]; - struct virtchnl_ipsec_sa_update sa_update[0]; - struct virtchnl_ipsec_sa_destroy sa_destroy[0]; - struct virtchnl_ipsec_sp_destroy sp_destroy[0]; - - /* IPsec response */ - struct virtchnl_ipsec_sa_cfg_resp sa_cfg_resp[0]; - struct virtchnl_ipsec_sp_cfg_resp sp_cfg_resp[0]; - struct virtchnl_ipsec_cap ipsec_cap[0]; - struct virtchnl_ipsec_status ipsec_status[0]; - /* response to del_sa, del_sp, update_sa */ - struct virtchnl_ipsec_resp ipsec_resp[0]; - - /* IPsec event (no req_id is required) */ - struct virtchnl_ipsec_event event[0]; - - /* Reserved */ - struct virtchnl_ipsec_sa_read sa_read[0]; - } ipsec_data; -}; - -static inline u16 virtchnl_inline_ipsec_val_msg_len(u16 opcode) -{ - u16 valid_len = sizeof(struct inline_ipsec_msg); - - switch (opcode) { - case INLINE_IPSEC_OP_GET_CAP: - case INLINE_IPSEC_OP_GET_STATUS: - break; - case INLINE_IPSEC_OP_SA_CREATE: - valid_len += sizeof(struct virtchnl_ipsec_sa_cfg); - break; - case INLINE_IPSEC_OP_SP_CREATE: - valid_len += sizeof(struct virtchnl_ipsec_sp_cfg); - break; - case INLINE_IPSEC_OP_SA_UPDATE: - valid_len += sizeof(struct virtchnl_ipsec_sa_update); - break; - case INLINE_IPSEC_OP_SA_DESTROY: - valid_len += sizeof(struct virtchnl_ipsec_sa_destroy); - break; - case INLINE_IPSEC_OP_SP_DESTROY: - valid_len += sizeof(struct virtchnl_ipsec_sp_destroy); - break; - /* Only for msg length calculation of response to VF in case of - * inline ipsec failure. - */ - case INLINE_IPSEC_OP_RESP: - valid_len += sizeof(struct virtchnl_ipsec_resp); - break; - default: - valid_len = 0; - break; - } - - return valid_len; -} - -#endif /* _VIRTCHNL_INLINE_IPSEC_H_ */ diff --git a/drivers/common/idpf/meson.build b/drivers/common/idpf/meson.build index 63f60accd9..80c8906f80 100644 --- a/drivers/common/idpf/meson.build +++ b/drivers/common/idpf/meson.build @@ -5,6 +5,8 @@ if dpdk_conf.get('RTE_IOVA_IN_MBUF') == 0 subdir_done() endif +includes += include_directories('../iavf') + deps += ['mbuf'] sources = files( From patchwork Wed Apr 26 10:22:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126534 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 406F342A02; Wed, 26 Apr 2023 12:28:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7922942D2D; Wed, 26 Apr 2023 12:28:00 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 9AE8240DDA; Wed, 26 Apr 2023 12:27:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504877; x=1714040877; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VQXRouaK+IKPG/RNj7a4FchRTe4L3XqOPsszmvYTy6E=; b=QyrnOpqVtC9EQC6sXWCxv29czJgaea2tA1mBYKMmPjEjtRVjuKhECVQR 7Xl+CQwoYlf/VYRsrGNajbSalJL1gkbMo1U/fmI6d5UwnpUYw27snibtV vc+2N3YJoT1EohRUBC0bOpn6BzHfOMGdh1Xo18plF2BAeFGAevMbild3V 7JuMEvR6qwu2f1pU5dO3b0ubDgsAj/0mFQ0FafSvrnJa8u/fLl6+NnBcy MjqPgDFSgETnAJltKfOyaxIfLUt69jENl2DQQklj/rZTB706GQL3ByTeP LPaTyiUas2Wfij0LOw2Y2fsO6I9AaaL/MVoxR+7bug+Iaf8Fl5cUoZwDW A==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391480" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391480" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:27:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552621" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552621" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:53 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org, Charles Stoll Subject: [PATCH v3 02/15] common/idpf/base: fix ctlq message send and receive Date: Wed, 26 Apr 2023 06:22:46 -0400 Message-Id: <20230426102259.205992-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes the ctlq send and receive functions to not cast the cookie field to a u64 before programming. By doing a cast, it can cause endianness issues as LE will swap the lower 32 and higher 32 bits whereas BE will not. By treating this field as two 32 bit values, both BE and LE will place the retval and opcode in the correct location. Since this field is now being treated as two 32 bit values, the cfg.data section must also be split into a data high and data low. Macros to easily pack and read these fields have also been added. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Charles Stoll Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 3af81e5a64..8e4d3ee54f 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -311,18 +311,14 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, for (i = 0; i < num_q_msg; i++) { struct idpf_ctlq_msg *msg = &q_msg[i]; - u64 msg_cookie; desc = IDPF_CTLQ_DESC(cq, cq->next_to_use); desc->opcode = CPU_TO_LE16(msg->opcode); desc->pfid_vfid = CPU_TO_LE16(msg->func_id); - msg_cookie = *(u64 *)&msg->cookie; - desc->cookie_high = - CPU_TO_LE32(IDPF_HI_DWORD(msg_cookie)); - desc->cookie_low = - CPU_TO_LE32(IDPF_LO_DWORD(msg_cookie)); + desc->cookie_high = CPU_TO_LE32(msg->cookie.mbx.chnl_opcode); + desc->cookie_low = CPU_TO_LE32(msg->cookie.mbx.chnl_retval); desc->flags = CPU_TO_LE16((msg->host_id & IDPF_HOST_ID_MASK) << IDPF_CTLQ_FLAG_HOST_ID_S); @@ -620,8 +616,6 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, num_to_clean = *num_q_msg; for (i = 0; i < num_to_clean; i++) { - u64 msg_cookie; - /* Fetch next descriptor and check if marked as done */ desc = IDPF_CTLQ_DESC(cq, ntc); flags = LE16_TO_CPU(desc->flags); @@ -639,10 +633,8 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, if (flags & IDPF_CTLQ_FLAG_ERR) ret_code = -EBADMSG; - msg_cookie = (u64)LE32_TO_CPU(desc->cookie_high) << 32; - msg_cookie |= (u64)LE32_TO_CPU(desc->cookie_low); - idpf_memcpy(&q_msg[i].cookie, &msg_cookie, sizeof(u64), - IDPF_NONDMA_TO_NONDMA); + q_msg[i].cookie.mbx.chnl_opcode = LE32_TO_CPU(desc->cookie_high); + q_msg[i].cookie.mbx.chnl_retval = LE32_TO_CPU(desc->cookie_low); q_msg[i].opcode = LE16_TO_CPU(desc->opcode); q_msg[i].data_len = LE16_TO_CPU(desc->datalen); From patchwork Wed Apr 26 10:22:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126535 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D34EB42A02; Wed, 26 Apr 2023 12:28:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E513E42D33; Wed, 26 Apr 2023 12:28:02 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 65DF542D1D; Wed, 26 Apr 2023 12:28:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504880; x=1714040880; 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([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:55 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org, Priyalee Kushwaha Subject: [PATCH v3 03/15] common/idpf/base: fix ITR register definitions for AVF Date: Wed, 26 Apr 2023 06:22:47 -0400 Message-Id: <20230426102259.205992-4-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix ITR register definitions for AVF1.0 and AVF2.0 Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Priyalee Kushwaha Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_lan_pf_regs.h | 9 +++++++-- drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 ++++++++++++----- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 3df2347bd7..7f731ec3d6 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -77,8 +77,13 @@ #define PF_GLINT_DYN_CTL_WB_ON_ITR_M BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S) #define PF_GLINT_DYN_CTL_INTENA_MSK_S 31 #define PF_GLINT_DYN_CTL_INTENA_MSK_M BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S) -#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start)) -#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) * 0x1000)) +/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is + * spacing b/w itrn registers of the same vector. + */ +#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ +#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 #define PF_GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S) diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 9cd4f757d9..13c5c5a7da 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -90,11 +90,18 @@ #define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S) #define VF_INT_DYN_CTLN_INTENA_MSK_S 31 #define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S) -#define VF_INT_ITR0(_i) (0x00004C00 + ((_i) * 4)) -#define VF_INT_ITRN_V2(_i, _reg_start) ((_reg_start) + (((_i)) * 4)) -#define VF_INT_ITRN(_i, _INT) (0x00002800 + ((_i) * 4) + ((_INT) * 0x40)) -#define VF_INT_ITRN_64(_i, _INT) (0x00002C00 + ((_i) * 4) + ((_INT) * 0x100)) -#define VF_INT_ITRN_2K(_i, _INT) (0x00072000 + ((_i) * 4) + ((_INT) * 0x100)) +/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing + * b/w itrn registers of the same vector + */ +#define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) +#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */ +#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) +/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */ +#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) +/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */ +#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 #define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S) From patchwork Wed Apr 26 10:22:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126536 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D00F42A02; Wed, 26 Apr 2023 12:28:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 208D142D1D; Wed, 26 Apr 2023 12:28:06 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 5DA2A42D1D for ; Wed, 26 Apr 2023 12:28:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; 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E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552677" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:57 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH v3 04/15] common/idpf/base: remove qregion struct variables Date: Wed, 26 Apr 2023 06:22:48 -0400 Message-Id: <20230426102259.205992-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Existing qregion variables are not well defined and cannot be used for TC related stuff. Remove them from create vport struct and add those freed bytes to a new reserved field. Add appropriate comments on how to use the dynctl and itrn register spacing variables. Only VF reference was used in get version comments where it should be PF/VF. Note: qregion variables will be added once the requirements are defined properly. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index d496f2388e..5c01734b65 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -426,13 +426,13 @@ /* VIRTCHNL2_OP_VERSION - * VF posts its version number to the CP. CP responds with its version number + * PF/VF posts its version number to the CP. CP responds with its version number * in the same format, along with a return code. - * If there is a major version mismatch, then the VF cannot operate. - * If there is a minor version mismatch, then the VF can operate but should + * If there is a major version mismatch, then the PF/VF cannot operate. + * If there is a minor version mismatch, then the PF/VF can operate but should * add a warning to the system log. * - * This version opcode MUST always be specified as == 1, regardless of other + * This version opcode MUST always be specified as == 1, regardless of other * changes in the API. The CP must always respond to this message without * error regardless of version mismatch. */ @@ -598,11 +598,7 @@ struct virtchnl2_create_vport { /* see VIRTCHNL2_TX_DESC_IDS definitions */ __le64 tx_desc_ids; -#define MAX_Q_REGIONS 16 - __le32 max_qs_per_qregion[MAX_Q_REGIONS]; - __le32 qregion_total_qs; - __le16 qregion_type; - __le16 pad2; + u8 reserved1[72]; /* see VIRTCHNL2_RSS_ALGORITHM definitions */ __le32 rss_algorithm; @@ -665,9 +661,7 @@ struct virtchnl2_txq_info { */ __le16 peer_rx_queue_id; - /* value ranges from 0 to 15 */ - __le16 qregion_id; - u8 pad[2]; + u8 pad[4]; /* Egress pasid is used for SIOV use case */ __le32 egress_pasid; @@ -734,10 +728,7 @@ struct virtchnl2_rxq_info { * if this field is set */ u8 bufq2_ena; - u8 pad2; - - /* value ranges from 0 to 15 */ - __le16 qregion_id; + u8 pad2[3]; /* Ingress pasid is used for SIOV use case */ __le32 ingress_pasid; @@ -801,9 +792,13 @@ struct virtchnl2_vector_chunk { * interrupt indices without modifying the state of the interrupt. */ __le32 dynctl_reg_start; + /* register spacing to find the next dynctl and itrn register offset + * from the provided dynctl_reg_start and itrn_reg_start respectively + */ __le32 dynctl_reg_spacing; __le32 itrn_reg_start; + /* register spacing to find the individual itrn register where n=0..2 */ __le32 itrn_reg_spacing; u8 reserved[8]; }; From patchwork Wed Apr 26 10:22:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126537 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EAEB42A02; Wed, 26 Apr 2023 12:28:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 59E4142D41; Wed, 26 Apr 2023 12:28:07 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 2BC6A42D1D for ; Wed, 26 Apr 2023 12:28:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504882; x=1714040882; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IXY7IFhDXjIrFFog9/DbVPZLHVa/0RPEvZ2TO2r3rEk=; b=XWJftvwkv96yPMpnqFSTjQOFwvm0tBKNolpYaaipu+SIMX1Goz6mYGss 5Gv6XUF6osNcXHEH0RzIUEoA4gmjrbWoxVoKngyiqYZ+tfNV5vS3S/4js KPpX2T6Wgype/AVpTjhxtXPmyTgFOPEqhUgiK0S/oGUmLaEPXGSNDbzjz Ok0jIE+UwL6fb0ujjFIzOYL+FfPwSEAb5nwOXGGeTItrmDkbvYWcxPKby 6zdQlki5vfjzmQSvjQ3yKhajFhgCQJU2s/ZV7tCeN2k5XA83sh4ozFqLB eW/H3pfNj7yb1apP3p1I9/T+m72y+CLdXl0CAfESJ8krVwEKJq41iqFZv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391514" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391514" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552687" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552687" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:00 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH v3 05/15] common/idpf/base: move OEM capability to the last bit Date: Wed, 26 Apr 2023 06:22:49 -0400 Message-Id: <20230426102259.205992-6-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move the existing OEM capability in VIRTCHNL2_OTHER_CAPS to the last bit. This should not break any backward compatibility as it is not used yet. And VIRTCHNL2_MEV_DEVICE is no longer upstreamed. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 5c01734b65..32d8fe8c06 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -208,11 +208,8 @@ #define VIRTCHNL2_CAP_RX_FLEX_DESC BIT(17) #define VIRTCHNL2_CAP_PTYPE BIT(18) #define VIRTCHNL2_CAP_LOOPBACK BIT(19) -#define VIRTCHNL2_CAP_OEM BIT(20) - -/* VIRTCHNL2_DEVICE_TYPE */ -/* underlying device type */ -#define VIRTCHNL2_MEV_DEVICE 0 +/* this must be the last capability */ +#define VIRTCHNL2_CAP_OEM BIT(63) /* VIRTCHNL2_TXQ_SCHED_MODE * Transmit Queue Scheduling Modes - Queue mode is the legacy mode i.e. inorder From patchwork Wed Apr 26 10:22:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126539 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A4AA42A02; Wed, 26 Apr 2023 12:28:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9CE8042D46; Wed, 26 Apr 2023 12:28:08 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 3D50F42D3D for ; Wed, 26 Apr 2023 12:28:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504884; x=1714040884; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GhO87oGG11ZM1yvafwTCi0+S6V7GZh/8I+81IGbEIfg=; b=kJRLRB2yGqTJOawhg8er9Ib6gz1z9jJhvtkPQFaOZ7aSU9uatAxE6O4G 6wZ7XQ9ek9S24YoCQzPrhoaOk4eNKEJuUoDVI5F+UEdZJtkpTeAnLPCm6 0Yej3iLdxvCY/j97vBFJeuV+kvy818pFck8ap4MnwprMiHdbTmRZxbq2K CqHojoIW7qgF7Qh87ZoqJALMu63IZxu0cXwQ1DuTKRLAo0LItaxoCmXqF 1lae0+1KwO5pFav3S0V7u69Ps0YgO7ndkpd7Pz6hXSrGLx3+afJi1s1tN YZFo2HWMCn68mUHr7eV/JaL1J960+i1nTCLjc6ncYfUg6zsXbqh2Cy5av g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391517" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391517" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552695" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552695" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:01 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH v3 06/15] common/idpf/base: modify SSO/LSO and ITR fields Date: Wed, 26 Apr 2023 06:22:50 -0400 Message-Id: <20230426102259.205992-7-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Driver assumes minimum packet length for sso as 17 bytes but it should be a negotiated value from CP. - Similarly, the number of header buffers for lso that are supported by the device should also be a negotiated value. Add min_sso_packet_len, max_hdr_buf_per_lso to address the above. Also, the existing 'itrn_reg_spacing' should be used for spacing between ITRn registers of 2 consecutive vectors and add a new spacing field to get the spacing between ITR registers of the same vector. - ITR_IDX 2 is not used in the current code. Bring it back if there exists any use case in the future. - NO_ITR is not really a register index and it is used only in the IDPF base code, so virtchnl support is not required for that - itr_idx_map is also not used as by default driver assumes at the minimum 2 ITRs are supported by the device. If any additional ITRs are also supported, then those should be negotiated. Remove all the above said fields and mark them as reserved. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 32d8fe8c06..edf3f200b3 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -289,8 +289,6 @@ */ #define VIRTCHNL2_ITR_IDX_0 0 #define VIRTCHNL2_ITR_IDX_1 1 -#define VIRTCHNL2_ITR_IDX_2 2 -#define VIRTCHNL2_ITR_IDX_NO_ITR 3 /* VIRTCHNL2_VECTOR_LIMITS * Since PF/VF messages are limited by __le16 size, precalculate the maximum @@ -510,9 +508,7 @@ struct virtchnl2_get_capabilities { */ u8 max_sg_bufs_per_tx_pkt; - /* see VIRTCHNL2_ITR_IDX definition */ - u8 itr_idx_map; - + u8 reserved1; __le16 pad1; /* version of Control Plane that is running */ @@ -521,7 +517,12 @@ struct virtchnl2_get_capabilities { /* see VIRTCHNL2_DEVICE_TYPE definitions */ __le32 device_type; - u8 reserved[12]; + /* min packet length supported by device for single segment offload */ + u8 min_sso_packet_len; + /* max number of header buffers that can be used for an LSO */ + u8 max_hdr_buf_per_lso; + + u8 reserved[10]; }; VIRTCHNL2_CHECK_STRUCT_LEN(80, virtchnl2_get_capabilities); @@ -789,15 +790,17 @@ struct virtchnl2_vector_chunk { * interrupt indices without modifying the state of the interrupt. */ __le32 dynctl_reg_start; - /* register spacing to find the next dynctl and itrn register offset - * from the provided dynctl_reg_start and itrn_reg_start respectively - */ + /* register spacing between dynctl registers of 2 consecutive vectors */ __le32 dynctl_reg_spacing; __le32 itrn_reg_start; - /* register spacing to find the individual itrn register where n=0..2 */ + /* register spacing between itrn registers of 2 consecutive vectors */ __le32 itrn_reg_spacing; - u8 reserved[8]; + /* register spacing between itrn registers of the same vector + * where n=0..2 + */ + __le32 itrn_index_spacing; + u8 reserved[4]; }; VIRTCHNL2_CHECK_STRUCT_LEN(32, virtchnl2_vector_chunk); From patchwork Wed Apr 26 10:22:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126540 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25D1142A02; Wed, 26 Apr 2023 12:28:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CB79442D49; Wed, 26 Apr 2023 12:28:11 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id A4C6D42D3D for ; Wed, 26 Apr 2023 12:28:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504886; x=1714040886; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=na+DY3kJkdubMbrHkHHTx9PtdNDzHvcFhNbY3+/qo3k=; b=kNkPuwo8NqWqM/vb30amMOylFoQtA4fA8L8Rq9NJHTESCw78mW9l6CTF Mr+Fja0QpyCW5ivI7dZZQnGu1Tc8pNkwmVuMdk2c09kPnuoE74OoZ4tc8 th/X7rqMGkvkcp/ohbHsmCY0prqSSji2ZtLQFU6iqjyYvNfSNrveeZAkR nSOXAeAG8Sf4q8zO+eXZq17CUv1d1i/YSZW1cv36LtC+AWHjuDYuL+ufr dTOfa7age+GWTYWHK1G0AHYLshktAB5Hkru3Op1hLVY2JJLJmWIjB1+tR LKMICqYdYkEX6xlwY5V1yJ5k2pio7Vx3PjdqFPMjp0a5qu8fM71r8Lv/d Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391526" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391526" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552705" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552705" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:04 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Kazatsker Kirill , Pavan Kumar Linga Subject: [PATCH v3 07/15] common/idpf/base: add virtchnl2 error codes Date: Wed, 26 Apr 2023 06:22:51 -0400 Message-Id: <20230426102259.205992-8-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Virtchnl2 error codes are required for meaningful failure information sharing between CP and PF/VF. Introduce the necessary error codes. New error codes were introduced removing the old ones. So the references to the old one should be modified to avoid CI build failures. Use appropriate error codes wherever necessary. Signed-off-by: Kazatsker Kirill Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 40 +++++++++++++++++++++------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index edf3f200b3..415e90358e 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -12,14 +12,34 @@ #include "virtchnl2_lan_desc.h" -/* Error Codes - * Note that many older versions of various iAVF drivers convert the reported - * status code directly into an iavf_status enumeration. For this reason, it - * is important that the values of these enumerations line up. - */ -#define VIRTCHNL2_STATUS_SUCCESS 0 -#define VIRTCHNL2_STATUS_ERR_PARAM -5 -#define VIRTCHNL2_STATUS_ERR_OPCODE_MISMATCH -38 +/* VIRTCHNL2_ERROR_CODES */ +/* success */ +#define VIRTCHNL2_STATUS_SUCCESS 0 +/* Operation not permitted, used in case of command not permitted for sender */ +#define VIRTCHNL2_STATUS_ERR_EPERM 1 +/* Bad opcode - virtchnl interface problem */ +#define VIRTCHNL2_STATUS_ERR_ESRCH 3 +/* I/O error - HW access error */ +#define VIRTCHNL2_STATUS_ERR_EIO 5 +/* No such resource - Referenced resource is not allacated */ +#define VIRTCHNL2_STATUS_ERR_ENXIO 6 +/* Permission denied - Resource is not permitted to caller */ +#define VIRTCHNL2_STATUS_ERR_EACCES 13 +/* Device or resource busy - In case shared resource is in use by others */ +#define VIRTCHNL2_STATUS_ERR_EBUSY 16 +/* Object already exists and not free */ +#define VIRTCHNL2_STATUS_ERR_EEXIST 17 +/* Invalid input argument in command */ +#define VIRTCHNL2_STATUS_ERR_EINVAL 22 +/* No space left or allocation failure */ +#define VIRTCHNL2_STATUS_ERR_ENOSPC 28 +/* Parameter out of range */ +#define VIRTCHNL2_STATUS_ERR_ERANGE 34 + +/* Op not allowed in current dev mode */ +#define VIRTCHNL2_STATUS_ERR_EMODE 200 +/* State Machine error - Command sequence problem */ +#define VIRTCHNL2_STATUS_ERR_ESM 201 /* These macros are used to generate compilation errors if a structure/union * is not exactly the correct length. It gives a divide by zero error if the @@ -1445,11 +1465,11 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 case VIRTCHNL2_OP_EVENT: case VIRTCHNL2_OP_UNKNOWN: default: - return VIRTCHNL2_STATUS_ERR_PARAM; + return VIRTCHNL2_STATUS_ERR_ESRCH; } /* few more checks */ if (err_msg_format || valid_len != msglen) - return VIRTCHNL2_STATUS_ERR_OPCODE_MISMATCH; + return VIRTCHNL2_STATUS_ERR_EINVAL; return 0; } From patchwork Wed Apr 26 10:22:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126541 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D628F42A02; Wed, 26 Apr 2023 12:28:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8EB942D4E; Wed, 26 Apr 2023 12:28:12 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 88AEC42D29 for ; Wed, 26 Apr 2023 12:28:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504888; x=1714040888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iJS8b289BbEG/ftluEVn/OUjC0eQe2qMP8SQk1HdJwY=; b=DcdFgwtU4ldE4haqlfFRfrVlezdK/OGu1pYQTqGo8/t6SnIfb5SklNnq XHnsHKXXen9AVcWyGPOaGNnGl2sbIIPR8+++eX0zRqigkGrOKOlnBrOF6 czKikc7G+mpy506UM4U1TEf7SScZBXkjCKpEktYrCj30MWVhcnZhVkEJm MmnrgLcbtfFfZYtBqOgzX01Ryp3thAXtdkwiveWk0KJK0SVq9IxA0HLpf DRv6veVOeN5QnmD11ukNzCUWvcJYp97V/U2aeUy8KWdCcOzHPOb4vmexg 1YGijtbQPPGRtYbU5Q5qeBiW+yv/7e4ojiN17jqSIznz9zM1mn9bat3J5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391533" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391533" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552713" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552713" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:06 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Charles Stoll Subject: [PATCH v3 08/15] common/idpf/base: swap opcode and retval location in msg struct Date: Wed, 26 Apr 2023 06:22:52 -0400 Message-Id: <20230426102259.205992-9-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org To make the code more readable and make it clearer that the opcode goes in cookie_high and retval goes in cookie_low. Add macro definitions for filling opcode and retval. Signed-off-by: Charles Stoll Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 2 ++ drivers/common/idpf/base/idpf_controlq_api.h | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 8e4d3ee54f..8381e4000f 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -288,6 +288,8 @@ int idpf_ctlq_deinit(struct idpf_hw *hw) * send routine via the q_msg struct / control queue specific data struct. * The control queue will hold a reference to each send message until * the completion for that message has been cleaned. + * Since all q_msgs being sent are store in native endianness, these values + * must be converted to LE before being written to the hw descriptor. */ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_msg, struct idpf_ctlq_msg q_msg[]) diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 32d17baadf..80be282b42 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -63,9 +63,13 @@ struct idpf_ctlq_msg { u16 status; /* when receiving a message */ }; union { +#ifndef __KERNEL__ +#define FILL_OPCODE_V1(msg, opcode) ((msg).cookie.cfg.mbx.chnl_opcode = opcode) +#define FILL_RETVAL_V1(msg, retval) ((msg).cookie.cfg.mbx.chnl_retval = retval) +#endif /* __KERNEL__ */ struct { - u32 chnl_retval; u32 chnl_opcode; + u32 chnl_retval; } mbx; } cookie; union { From patchwork Wed Apr 26 10:22:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126542 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F207042A02; Wed, 26 Apr 2023 12:29:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C0B2542D63; Wed, 26 Apr 2023 12:28:14 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 4118442D48; Wed, 26 Apr 2023 12:28:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504891; x=1714040891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gq0E3LQAyGXnJtOa4/lFTTRiQOjr+yHdJInVYOZb1/Q=; b=PCltyx3Ep6P61u/2gb037tiMYH1OHrYVxkG9DSbYpBeIc/yx6SdXIqx8 pB0kkoct4xtBkPAB+g0S1yRILayUVtcogdR3t8WzM4D2YSnRlen45GtiK NmscdMBm00lRyiuu4R2mzBfwKtI0htZTjiIw/uV5eNshI675l46DScgpB nknK03JZHFiY1gKI0zuVo/yRwJO8NfjUmZIIRIqVGswOiIgXLy2GB4kTi wbo2lYZo4/HtIqQJet15egOOYHw+H2oB0YwPbUQlLuJY6bypklUkE+cZp HXDu5qYL63ykMZNuNLBgRGo90DlFwkkyYnST767XlTk3nNVQykv9GsDLh g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391547" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391547" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552729" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552729" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:08 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org, Christopher Pau Subject: [PATCH v3 09/15] common/idpf/base: fix idpf_send_msg_to_cp prototypes Date: Wed, 26 Apr 2023 06:22:53 -0400 Message-Id: <20230426102259.205992-10-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Virtchnl2 opcodes are no longer in the enum virtchnl_ops. So change these parameters to allow int rather that compiler enum type checking. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Christopher Pau Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 41e0d05623..2394f85580 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -146,7 +146,7 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) * is sent asynchronously, i.e. idpf_asq_send_command() does not wait for * completion before returning. */ -int idpf_send_msg_to_cp(struct idpf_hw *hw, enum virtchnl_ops v_opcode, +int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, int v_retval, u8 *msg, u16 msglen) { struct idpf_ctlq_msg ctlq_msg = { 0 }; diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index 3090f4cc2a..c9812a7f94 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -40,6 +40,6 @@ int idpf_set_rss_key(struct idpf_hw *hw, u16 seid, int idpf_set_mac_type(struct idpf_hw *hw); int idpf_reset(struct idpf_hw *hw); -int idpf_send_msg_to_cp(struct idpf_hw *hw, enum virtchnl_ops v_opcode, +int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, int v_retval, u8 *msg, u16 msglen); #endif /* _IDPF_PROTOTYPE_H_ */ From patchwork Wed Apr 26 10:22:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126543 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8FF4B42A02; Wed, 26 Apr 2023 12:29:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3A8142D61; Wed, 26 Apr 2023 12:28:17 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 5367742D0C; Wed, 26 Apr 2023 12:28:13 +0200 (CEST) DKIM-Signature: v=1; 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d="scan'208";a="1023552739" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:11 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org, Christopher Pau Subject: [PATCH v3 10/15] common/idpf/base: fix memory leaks on ctrlq functions Date: Wed, 26 Apr 2023 06:22:54 -0400 Message-Id: <20230426102259.205992-11-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org idpf_init_hw needs to free it's q_info. idpf_clean_arq_element needs to return buffers via post_rx_buffs Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Christopher Pau Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 2394f85580..da352ea88f 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -130,6 +130,8 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) hw->mac.addr[4] = 0x03; hw->mac.addr[5] = 0x14; + idpf_free(hw, q_info); + return 0; } @@ -219,6 +221,7 @@ bool idpf_check_asq_alive(struct idpf_hw *hw) int idpf_clean_arq_element(struct idpf_hw *hw, struct idpf_arq_event_info *e, u16 *pending) { + struct idpf_dma_mem *dma_mem = NULL; struct idpf_ctlq_msg msg = { 0 }; int status; u16 msg_data_len; @@ -226,6 +229,8 @@ int idpf_clean_arq_element(struct idpf_hw *hw, *pending = 1; status = idpf_ctlq_recv(hw->arq, pending, &msg); + if (status == -ENOMSG) + goto exit; /* ctlq_msg does not align to ctlq_desc, so copy relevant data here */ e->desc.opcode = msg.opcode; @@ -240,7 +245,14 @@ int idpf_clean_arq_element(struct idpf_hw *hw, msg_data_len = msg.data_len; idpf_memcpy(e->msg_buf, msg.ctx.indirect.payload->va, msg_data_len, IDPF_DMA_TO_NONDMA); + dma_mem = msg.ctx.indirect.payload; + } else { + *pending = 0; } + + status = idpf_ctlq_post_rx_buffs(hw, hw->arq, pending, &dma_mem); + +exit: return status; } From patchwork Wed Apr 26 10:22:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126544 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D73542A02; Wed, 26 Apr 2023 12:29:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B48242D74; Wed, 26 Apr 2023 12:28:19 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 3DD6F42D65 for ; Wed, 26 Apr 2023 12:28:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504895; x=1714040895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/qMXlimOGXOHgTycJFONtlh6cWR3/8wdx4D0T48FWvA=; b=ZieiM9h9NfxlyFC0K46XdE68WzU15qial6iHpz+WTfFHdZ5nGBdZgAzz uEr2+irRhxyxGc2b9CpGOtsr8gU7SLr+fuSicfHZgpy5vuH1BNXtHNHRy Ip0W3tEEbY82Iqbzo4Qvq1QEowFVIPyfdGVzxwPZZAbFJtZkKX3p/PFuM +4E6hqaelz9z2TlV+EDPUtDCNzM1QTVNTLTQsnwsdYpsGjhqglOcXTOkI iSg15msf58xB10A9218V3oCT9kZOxKCYQTbbtA/k1XCk8r4AoNFaWSicb ho2jY2SzG4LzePwFBpNG3g3Al+NW354jg8JFsKAT+iDGz+yq2Gx1VkqHJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391560" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391560" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552751" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552751" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:13 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Christopher Pau Subject: [PATCH v3 11/15] common/idpf/base: allocate static buffer at initialization Date: Wed, 26 Apr 2023 06:22:55 -0400 Message-Id: <20230426102259.205992-12-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some OSs don't allow allocating DMA memory at runtime. So create an initial static buffer at initialization to hold this data. Signed-off-by: Christopher Pau Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index da352ea88f..17b2221624 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -6,6 +6,7 @@ #include "idpf_prototype.h" #include +struct idpf_dma_mem send_dma_mem = { 0 }; /** * idpf_set_mac_type - Sets MAC type @@ -132,6 +133,15 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) idpf_free(hw, q_info); + /* + * Need an initial static buffer to copy DMA memory to send + * for drivers that do not allow this allocation at runtime + */ + send_dma_mem.va = (struct idpf_dma_mem *) + idpf_alloc_dma_mem(hw, &send_dma_mem, 4096); + if (!send_dma_mem.va) + return -ENOMEM; + return 0; } @@ -152,7 +162,6 @@ int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, int v_retval, u8 *msg, u16 msglen) { struct idpf_ctlq_msg ctlq_msg = { 0 }; - struct idpf_dma_mem dma_mem = { 0 }; int status; ctlq_msg.opcode = idpf_mbq_opc_send_msg_to_pf; @@ -162,19 +171,11 @@ int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, ctlq_msg.cookie.mbx.chnl_opcode = v_opcode; if (msglen > 0) { - dma_mem.va = (struct idpf_dma_mem *) - idpf_alloc_dma_mem(hw, &dma_mem, msglen); - if (!dma_mem.va) - return -ENOMEM; - - idpf_memcpy(dma_mem.va, msg, msglen, IDPF_NONDMA_TO_DMA); - ctlq_msg.ctx.indirect.payload = &dma_mem; + idpf_memcpy(send_dma_mem.va, msg, msglen, IDPF_NONDMA_TO_DMA); + ctlq_msg.ctx.indirect.payload = &send_dma_mem; } status = idpf_ctlq_send(hw, hw->asq, 1, &ctlq_msg); - if (dma_mem.va) - idpf_free_dma_mem(hw, &dma_mem); - return status; } @@ -262,6 +263,9 @@ int idpf_clean_arq_element(struct idpf_hw *hw, */ int idpf_deinit_hw(struct idpf_hw *hw) { + if (send_dma_mem.va) + idpf_free_dma_mem(hw, &send_dma_mem); + hw->asq = NULL; hw->arq = NULL; From patchwork Wed Apr 26 10:22:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126545 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7A9842A02; Wed, 26 Apr 2023 12:29:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 84BB442D77; Wed, 26 Apr 2023 12:28:20 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 8040F42D40 for ; Wed, 26 Apr 2023 12:28:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504897; x=1714040897; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SXo7/Pjj7jQW2OleKGH8O2pr2IQLIl9HMg3yjKXI2e4=; b=A8JNtp2ZFxyLhJT2TvNvLL7f5lQcN2TJvubR7J2pgWkvviOCwRGSTyNT I4nmQFCKi4KlXIcrki8eUr3xn86cgfXdaOsS1fl07/nTIHsudw7eHrS6B jyYd39pSDbcHgx1RCAOg9rz4E2z9NbpXl+/bYLgorc4cm2RSVKXzBjq5M lXRpbpNy7LNrWaStuEvyWYjh9Lr4p691OUbp/n2TqxmUFiM2QjObuhTvz oxoaY/0Az8dXSxLnI4rTLXSCLiWrxMo1PqvpRYnomHyust4o1ZCRJms/h xhkJkUreJl8dkYl2VQITRRh3X9Vb5LFBat3zCfkyK6mx93v5MNz18rBy4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391572" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391572" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552761" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552761" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:15 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Priyalee Kushwaha Subject: [PATCH v3 12/15] common/idpf/base: replace MAKEMASK to IDPF_M Date: Wed, 26 Apr 2023 06:22:56 -0400 Message-Id: <20230426102259.205992-13-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Replace MAKEMASK to IDPF_M to avoid conflicts with MAKEMASK redefinition from various subcomponents. Signed-off-by: Priyalee Kushwaha Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.h | 3 -- drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 +++++------ drivers/common/idpf/base/idpf_lan_txrx.h | 46 +++++++++---------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +++---- drivers/common/idpf/base/idpf_osdep.h | 2 + drivers/common/idpf/base/idpf_type.h | 2 - drivers/common/idpf/base/virtchnl2_lan_desc.h | 28 +++++------ 7 files changed, 60 insertions(+), 63 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h index e7b0d803b3..47bffcf79f 100644 --- a/drivers/common/idpf/base/idpf_controlq.h +++ b/drivers/common/idpf/base/idpf_controlq.h @@ -97,9 +97,6 @@ struct idpf_ctlq_desc { #define IDPF_CTLQ_FLAG_VFC BIT(IDPF_CTLQ_FLAG_VFC_S) /* 0x800 */ #define IDPF_CTLQ_FLAG_BUF BIT(IDPF_CTLQ_FLAG_BUF_S) /* 0x1000 */ -/* Host ID is a special field that has 3b and not a 1b flag */ -#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S) - struct idpf_mbxq_desc { u8 pad[8]; /* CTLQ flags/opcode/len/retval fields */ u32 chnl_opcode; /* avoid confusion with desc->opcode */ diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 7f731ec3d6..1c665d1f3b 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -24,7 +24,7 @@ #define PF_FW_ARQBAH (PF_FW_BASE + 0x4) #define PF_FW_ARQLEN (PF_FW_BASE + 0x8) #define PF_FW_ARQLEN_ARQLEN_S 0 -#define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) +#define PF_FW_ARQLEN_ARQLEN_M IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) #define PF_FW_ARQLEN_ARQVFE_S 28 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S) #define PF_FW_ARQLEN_ARQOVFL_S 29 @@ -35,14 +35,14 @@ #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) #define PF_FW_ARQH (PF_FW_BASE + 0xC) #define PF_FW_ARQH_ARQH_S 0 -#define PF_FW_ARQH_ARQH_M MAKEMASK(0x1FFF, PF_FW_ARQH_ARQH_S) +#define PF_FW_ARQH_ARQH_M IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S) #define PF_FW_ARQT (PF_FW_BASE + 0x10) #define PF_FW_ATQBAL (PF_FW_BASE + 0x14) #define PF_FW_ATQBAH (PF_FW_BASE + 0x18) #define PF_FW_ATQLEN (PF_FW_BASE + 0x1C) #define PF_FW_ATQLEN_ATQLEN_S 0 -#define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, PF_FW_ATQLEN_ATQLEN_S) +#define PF_FW_ATQLEN_ATQLEN_M IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S) #define PF_FW_ATQLEN_ATQVFE_S 28 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S) #define PF_FW_ATQLEN_ATQOVFL_S 29 @@ -53,7 +53,7 @@ #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) #define PF_FW_ATQH (PF_FW_BASE + 0x20) #define PF_FW_ATQH_ATQH_S 0 -#define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, PF_FW_ATQH_ATQH_S) +#define PF_FW_ATQH_ATQH_M IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S) #define PF_FW_ATQT (PF_FW_BASE + 0x24) /* Interrupts */ @@ -66,7 +66,7 @@ #define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S) #define PF_GLINT_DYN_CTL_ITR_INDX_S 3 -#define PF_GLINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) +#define PF_GLINT_DYN_CTL_ITR_INDX_M IDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) #define PF_GLINT_DYN_CTL_INTERVAL_S 5 #define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S) #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 @@ -86,13 +86,13 @@ #define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 -#define PF_GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S) +#define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) /* Timesync registers */ #define PF_TIMESYNC_BASE 0x08404000 #define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE) #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0 -#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M MAKEMASK(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) +#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M IDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S) #define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4) @@ -104,23 +104,23 @@ /* Generic registers */ #define PF_INT_DIR_OICR_ENA 0x08406000 #define PF_INT_DIR_OICR_ENA_S 0 -#define PF_INT_DIR_OICR_ENA_M MAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) +#define PF_INT_DIR_OICR_ENA_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) #define PF_INT_DIR_OICR 0x08406004 #define PF_INT_DIR_OICR_TSYN_EVNT 0 #define PF_INT_DIR_OICR_PHY_TS_0 BIT(1) #define PF_INT_DIR_OICR_PHY_TS_1 BIT(2) #define PF_INT_DIR_OICR_CAUSE 0x08406008 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S 0 -#define PF_INT_DIR_OICR_CAUSE_CAUSE_M MAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) +#define PF_INT_DIR_OICR_CAUSE_CAUSE_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) #define PF_INT_PBA_CLEAR 0x0840600C #define PF_FUNC_RID 0x08406010 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 -#define PF_FUNC_RID_FUNCTION_NUMBER_M MAKEMASK(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) +#define PF_FUNC_RID_FUNCTION_NUMBER_M IDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) #define PF_FUNC_RID_DEVICE_NUMBER_S 3 -#define PF_FUNC_RID_DEVICE_NUMBER_M MAKEMASK(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) +#define PF_FUNC_RID_DEVICE_NUMBER_M IDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) #define PF_FUNC_RID_BUS_NUMBER_S 8 -#define PF_FUNC_RID_BUS_NUMBER_M MAKEMASK(0xFF, PF_FUNC_RID_BUS_NUMBER_S) +#define PF_FUNC_RID_BUS_NUMBER_M IDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S) /* Reset registers */ #define PFGEN_RTRIG 0x08407000 @@ -132,7 +132,7 @@ #define PFGEN_RTRIG_IMCR_M BIT(2) #define PFGEN_RSTAT 0x08407008 /* PFR Status */ #define PFGEN_RSTAT_PFR_STATE_S 0 -#define PFGEN_RSTAT_PFR_STATE_M MAKEMASK(0x3, PFGEN_RSTAT_PFR_STATE_S) +#define PFGEN_RSTAT_PFR_STATE_M IDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S) #define PFGEN_CTRL 0x0840700C #define PFGEN_CTRL_PFSWR BIT(0) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 98484b267c..82742857be 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -68,9 +68,9 @@ enum idpf_rss_hash { #define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S) #define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M \ - MAKEMASK(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) + IDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) #define IDPF_TXD_COMPLQ_QID_S 0 -#define IDPF_TXD_COMPLQ_QID_M MAKEMASK(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) +#define IDPF_TXD_COMPLQ_QID_M IDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) /* For base mode TX descriptors */ @@ -100,29 +100,29 @@ enum idpf_rss_hash { #define IDPF_TXD_CTX_QW1_MSS_S 50 #define IDPF_TXD_CTX_QW1_MSS_M \ - MAKEMASK(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) + IDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) #define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 #define IDPF_TXD_CTX_QW1_TSO_LEN_M \ - MAKEMASK(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) + IDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) #define IDPF_TXD_CTX_QW1_CMD_S 4 #define IDPF_TXD_CTX_QW1_CMD_M \ - MAKEMASK(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) + IDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) #define IDPF_TXD_CTX_QW1_DTYPE_S 0 #define IDPF_TXD_CTX_QW1_DTYPE_M \ - MAKEMASK(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) + IDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) #define IDPF_TXD_QW1_L2TAG1_S 48 #define IDPF_TXD_QW1_L2TAG1_M \ - MAKEMASK(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) + IDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) #define IDPF_TXD_QW1_TX_BUF_SZ_S 34 #define IDPF_TXD_QW1_TX_BUF_SZ_M \ - MAKEMASK(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) + IDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) #define IDPF_TXD_QW1_OFFSET_S 16 #define IDPF_TXD_QW1_OFFSET_M \ - MAKEMASK(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) + IDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) #define IDPF_TXD_QW1_CMD_S 4 -#define IDPF_TXD_QW1_CMD_M MAKEMASK(0xFFFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_TXD_QW1_CMD_M IDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S) #define IDPF_TXD_QW1_DTYPE_S 0 -#define IDPF_TXD_QW1_DTYPE_M MAKEMASK(0xFUL, IDPF_TXD_QW1_DTYPE_S) +#define IDPF_TXD_QW1_DTYPE_M IDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S) /* TX Completion Descriptor Completion Types */ #define IDPF_TXD_COMPLT_ITR_FLUSH 0 @@ -173,10 +173,10 @@ enum idpf_tx_desc_len_fields { IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ }; -#define IDPF_TXD_QW1_MACLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) -#define IDPF_TXD_QW1_IPLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) -#define IDPF_TXD_QW1_L4LEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) -#define IDPF_TXD_QW1_FCLEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) +#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) +#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) enum idpf_tx_base_desc_cmd_bits { IDPF_TX_DESC_CMD_EOP = 0x0001, @@ -244,9 +244,9 @@ struct idpf_flex_tx_desc { __le16 cmd_dtype; #define IDPF_FLEX_TXD_QW1_DTYPE_S 0 #define IDPF_FLEX_TXD_QW1_DTYPE_M \ - MAKEMASK(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) + IDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) #define IDPF_FLEX_TXD_QW1_CMD_S 5 -#define IDPF_FLEX_TXD_QW1_CMD_M MAKEMASK(0x7FFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_FLEX_TXD_QW1_CMD_M IDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S) union { /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */ u8 raw[4]; @@ -388,9 +388,9 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_MSS_RT_0 0 #define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF #define IDPF_TXD_FLEX_CTX_FTYPE_S 14 -#define IDPF_TXD_FLEX_CTX_FTYPE_VF MAKEMASK(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_PF MAKEMASK(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VF IDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV IDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_PF IDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) u8 hdr_len; u8 ptag; } tso; @@ -407,10 +407,10 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \ - MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) + IDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) #define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37 #define IDPF_TXD_FLEX_CTX_QW1_TPH \ - MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_TPH_S) + IDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S) #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */ @@ -418,7 +418,7 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \ - MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) + IDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */ #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 13c5c5a7da..c8739fae7a 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -9,7 +9,7 @@ /* Reset */ #define VFGEN_RSTAT 0x00008800 #define VFGEN_RSTAT_VFR_STATE_S 0 -#define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, VFGEN_RSTAT_VFR_STATE_S) +#define VFGEN_RSTAT_VFR_STATE_M IDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S) /* Control(VF Mailbox) Queue */ #define VF_BASE 0x00006000 @@ -18,7 +18,7 @@ #define VF_ATQBAH (VF_BASE + 0x1800) #define VF_ATQLEN (VF_BASE + 0x0800) #define VF_ATQLEN_ATQLEN_S 0 -#define VF_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, VF_ATQLEN_ATQLEN_S) +#define VF_ATQLEN_ATQLEN_M IDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S) #define VF_ATQLEN_ATQVFE_S 28 #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) #define VF_ATQLEN_ATQOVFL_S 29 @@ -29,14 +29,14 @@ #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) #define VF_ATQH (VF_BASE + 0x0400) #define VF_ATQH_ATQH_S 0 -#define VF_ATQH_ATQH_M MAKEMASK(0x3FF, VF_ATQH_ATQH_S) +#define VF_ATQH_ATQH_M IDPF_M(0x3FF, VF_ATQH_ATQH_S) #define VF_ATQT (VF_BASE + 0x2400) #define VF_ARQBAL (VF_BASE + 0x0C00) #define VF_ARQBAH (VF_BASE) #define VF_ARQLEN (VF_BASE + 0x2000) #define VF_ARQLEN_ARQLEN_S 0 -#define VF_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, VF_ARQLEN_ARQLEN_S) +#define VF_ARQLEN_ARQLEN_M IDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S) #define VF_ARQLEN_ARQVFE_S 28 #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) #define VF_ARQLEN_ARQOVFL_S 29 @@ -47,7 +47,7 @@ #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) #define VF_ARQH (VF_BASE + 0x1400) #define VF_ARQH_ARQH_S 0 -#define VF_ARQH_ARQH_M MAKEMASK(0x1FFF, VF_ARQH_ARQH_S) +#define VF_ARQH_ARQH_M IDPF_M(0x1FFF, VF_ARQH_ARQH_S) #define VF_ARQT (VF_BASE + 0x1000) /* Transmit queues */ @@ -69,7 +69,7 @@ #define VF_INT_DYN_CTL0_INTENA_S 0 #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) #define VF_INT_DYN_CTL0_ITR_INDX_S 3 -#define VF_INT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) +#define VF_INT_DYN_CTL0_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_INTENA_S 0 @@ -79,7 +79,7 @@ #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) #define VF_INT_DYN_CTLN_ITR_INDX_S 3 -#define VF_INT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) +#define VF_INT_DYN_CTLN_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) #define VF_INT_DYN_CTLN_INTERVAL_S 5 #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 @@ -104,7 +104,7 @@ #define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 -#define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S) +#define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) #define VF_INT_PBA_CLEAR 0x00008900 #define VF_INT_ICR0_ENA1 0x00005000 diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 99ae9cf60a..abcf68f1a2 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -45,6 +45,8 @@ typedef struct idpf_lock idpf_lock; #define low_16_bits(x) ((x) & 0xFFFF) #define high_16_bits(x) (((x) & 0xFFFF0000) >> 16) +#define IDPF_M(m, s) ((m) << (s)) + #ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 #endif diff --git a/drivers/common/idpf/base/idpf_type.h b/drivers/common/idpf/base/idpf_type.h index 3b46536287..2a97d32a8b 100644 --- a/drivers/common/idpf/base/idpf_type.h +++ b/drivers/common/idpf/base/idpf_type.h @@ -14,8 +14,6 @@ #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) -#define MAKEMASK(m, s) ((m) << (s)) - struct idpf_eth_stats { u64 rx_bytes; /* gorc */ u64 rx_unicast; /* uprc */ diff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h index b8cb22e474..0992cefc6c 100644 --- a/drivers/common/idpf/base/virtchnl2_lan_desc.h +++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h @@ -80,19 +80,19 @@ /* For splitq virtchnl2_rx_flex_desc_adv desc members */ #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M \ - MAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S) + IDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M \ - MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S) + IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S 10 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M \ - MAKEMASK(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S) + IDPF_M(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S 12 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M \ - MAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S) + IDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M \ - MAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S) + IDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S 14 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M \ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S) @@ -101,7 +101,7 @@ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M \ - MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S) + IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S 10 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M \ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S) @@ -110,7 +110,7 @@ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S 12 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M \ - MAKEMASK(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M) + IDPF_M(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M) #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S 15 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M \ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S) @@ -159,12 +159,12 @@ /* for virtchnl2_rx_flex_desc.ptype_flex_flags0 member */ #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S 0 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M \ - MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */ + IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */ /* for virtchnl2_rx_flex_desc.pkt_length member */ #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S 0 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M \ - MAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */ + IDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */ /* VIRTCHNL2_RX_FLEX_DESC_STATUS_ERROR_0_BITS * for singleq (flex) virtchnl2_rx_flex_desc @@ -212,19 +212,19 @@ BIT_ULL(VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S 52 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M \ - MAKEMASK(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S) + IDPF_M(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S 38 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M \ - MAKEMASK(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S) + IDPF_M(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S 30 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M \ - MAKEMASK(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S) + IDPF_M(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S 19 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M \ - MAKEMASK(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S) + IDPF_M(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S 0 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M \ - MAKEMASK(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S) + IDPF_M(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S) /* VIRTCHNL2_RX_BASE_DESC_STATUS_BITS * for singleq (base) virtchnl2_rx_base_desc From patchwork Wed Apr 26 10:22:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126546 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA80242A02; Wed, 26 Apr 2023 12:29:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ACBF442D31; Wed, 26 Apr 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([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552771" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552771" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:17 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Nizan Zorea Subject: [PATCH v3 13/15] common/idpf/base: add/delete queue groups commands Date: Wed, 26 Apr 2023 06:22:57 -0400 Message-Id: <20230426102259.205992-14-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add types for new two virtchnl commands: add & delete queue group Signed-off-by: Nizan Zorea Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 189 +++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 415e90358e..1eaa436485 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -95,6 +95,8 @@ #define VIRTCHNL2_OP_ADD_MAC_ADDR 535 #define VIRTCHNL2_OP_DEL_MAC_ADDR 536 #define VIRTCHNL2_OP_CONFIG_PROMISCUOUS_MODE 537 +#define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 +#define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -345,6 +347,14 @@ #define VIRTCHNL2_UNICAST_PROMISC BIT(0) #define VIRTCHNL2_MULTICAST_PROMISC BIT(1) +/* VIRTCHNL2_QUEUE_GROUP_TYPE + * Type of queue groups + * 0 till 0xFF is for general use + */ +#define VIRTCHNL2_QUEUE_GROUP_DATA 1 +#define VIRTCHNL2_QUEUE_GROUP_MBX 2 +#define VIRTCHNL2_QUEUE_GROUP_CONFIG 3 + /* VIRTCHNL2_PROTO_HDR_TYPE * Protocol header type within a packet segment. A segment consists of one or * more protocol headers that make up a logical group of protocol headers. Each @@ -794,6 +804,133 @@ struct virtchnl2_add_queues { VIRTCHNL2_CHECK_STRUCT_LEN(56, virtchnl2_add_queues); +/* Queue Groups Extension */ + +struct virtchnl2_rx_queue_group_info { + /* IN/OUT, user can ask to update rss_lut size originally allocated + * by CreateVport command. New size will be returned if allocation + * succeeded, otherwise original rss_size from CreateVport will + * be returned. + */ + __le16 rss_lut_size; + /* Future extension purpose */ + u8 pad[6]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_rx_queue_group_info); + +struct virtchnl2_tx_queue_group_info { /* IN */ + /* TX TC queue group will be connected to */ + u8 tx_tc; + /* Each group can have its own priority, value 0-7, while each group + * with unique priority is strict priority. + * It can be single set of queue groups which configured with + * same priority, then they are assumed part of WFQ arbitration + * group and are expected to be assigned with weight. + */ + u8 priority; + /* Determines if queue group is expected to be Strict Priority + * according to its priority + */ + u8 is_sp; + u8 pad; + + /* Peak Info Rate Weight in case Queue Group is part of WFQ + * arbitration set. + * The weights of the groups are independent of each other. + * Possible values: 1-200 + */ + __le16 pir_weight; + /* Future extension purpose for CIR only */ + u8 cir_pad[2]; + /* Future extension purpose*/ + u8 pad2[8]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_tx_queue_group_info); + +struct virtchnl2_queue_group_id { + /* Queue group ID - depended on it's type + * Data: is an ID which is relative to Vport + * Config & Mailbox: is an ID which is relative to func. + * This ID is use in future calls, i.e. delete. + * Requested by host and assigned by Control plane. + */ + __le16 queue_group_id; + /* Functional type: see VIRTCHNL2_QUEUE_GROUP_TYPE definitions */ + __le16 queue_group_type; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_queue_group_id); + +struct virtchnl2_queue_group_info { + /* IN */ + struct virtchnl2_queue_group_id qg_id; + /* IN, Number of queue of different types in the group. */ + __le16 num_tx_q; + __le16 num_tx_complq; + __le16 num_rx_q; + __le16 num_rx_bufq; + + struct virtchnl2_tx_queue_group_info tx_q_grp_info; + struct virtchnl2_rx_queue_group_info rx_q_grp_info; + /* Future extension purpose */ + u8 pad[40]; + struct virtchnl2_queue_reg_chunks chunks; /* OUT */ +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(120, virtchnl2_queue_group_info); + +struct virtchnl2_queue_groups { + __le16 num_queue_groups; + u8 pad[6]; + struct virtchnl2_queue_group_info groups[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(128, virtchnl2_queue_groups); + +/* VIRTCHNL2_OP_ADD_QUEUE_GROUPS + * PF sends this message to request additional transmit/receive queue groups + * beyond the ones that were assigned via CREATE_VPORT request. + * virtchnl2_add_queue_groups structure is used to specify the number of each + * type of queues. CP responds with the same structure with the actual number of + * groups and queues assigned followed by num_queue_groups and num_chunks of + * virtchnl2_queue_groups and virtchnl2_queue_chunk structures. + */ +struct virtchnl2_add_queue_groups { + /* IN, vport_id to add queue group to, same as allocated by CreateVport. + * NA for mailbox and other types not assigned to vport + */ + __le32 vport_id; + u8 pad[4]; + /* IN/OUT */ + struct virtchnl2_queue_groups qg_info; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(136, virtchnl2_add_queue_groups); + +/* VIRTCHNL2_OP_DEL_QUEUE_GROUPS + * PF sends this message to delete queue groups. + * PF sends virtchnl2_delete_queue_groups struct to specify the queue groups + * to be deleted. CP performs requested action and returns status and update + * num_queue_groups with number of successfully deleted queue groups. + */ +struct virtchnl2_delete_queue_groups { + /* IN, vport_id to delete queue group from, same as + * allocated by CreateVport. + */ + __le32 vport_id; + /* IN/OUT, Defines number of groups provided below */ + __le16 num_queue_groups; + u8 pad[2]; + + /* IN, IDs & types of Queue Groups to delete */ + struct virtchnl2_queue_group_id qg_ids[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_delete_queue_groups); + /* Structure to specify a chunk of contiguous interrupt vectors */ struct virtchnl2_vector_chunk { __le16 start_vector_id; @@ -1243,6 +1380,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_CREATE_ADI"; case VIRTCHNL2_OP_DESTROY_ADI: return "VIRTCHNL2_OP_DESTROY_ADI"; + case VIRTCHNL2_OP_ADD_QUEUE_GROUPS: + return "VIRTCHNL2_OP_ADD_QUEUE_GROUPS"; + case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: + return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1373,6 +1514,54 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 sizeof(struct virtchnl2_queue_chunk); } break; + case VIRTCHNL2_OP_ADD_QUEUE_GROUPS: + valid_len = sizeof(struct virtchnl2_add_queue_groups); + if (msglen != valid_len) { + __le32 i = 0, offset = 0; + struct virtchnl2_add_queue_groups *add_queue_grp = + (struct virtchnl2_add_queue_groups *)msg; + struct virtchnl2_queue_groups *groups = &(add_queue_grp->qg_info); + struct virtchnl2_queue_group_info *grp_info; + __le32 chunk_size = sizeof(struct virtchnl2_queue_reg_chunk); + __le32 group_size = sizeof(struct virtchnl2_queue_group_info); + __le32 total_chunks_size; + + if (groups->num_queue_groups == 0) { + err_msg_format = true; + break; + } + valid_len += (groups->num_queue_groups - 1) * + sizeof(struct virtchnl2_queue_group_info); + offset = (u8 *)(&groups->groups[0]) - (u8 *)groups; + + for (i = 0; i < groups->num_queue_groups; i++) { + grp_info = (struct virtchnl2_queue_group_info *) + ((u8 *)groups + offset); + if (grp_info->chunks.num_chunks == 0) { + offset += group_size; + continue; + } + total_chunks_size = (grp_info->chunks.num_chunks - 1) * chunk_size; + offset += group_size + total_chunks_size; + valid_len += total_chunks_size; + } + } + break; + case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: + valid_len = sizeof(struct virtchnl2_delete_queue_groups); + if (msglen != valid_len) { + struct virtchnl2_delete_queue_groups *del_queue_grp = + (struct virtchnl2_delete_queue_groups *)msg; + + if (del_queue_grp->num_queue_groups == 0) { + err_msg_format = true; + break; + } + + valid_len += (del_queue_grp->num_queue_groups - 1) * + sizeof(struct virtchnl2_queue_group_id); + } + break; case VIRTCHNL2_OP_MAP_QUEUE_VECTOR: case VIRTCHNL2_OP_UNMAP_QUEUE_VECTOR: valid_len = sizeof(struct virtchnl2_queue_vector_maps); From patchwork Wed Apr 26 10:22:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126547 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4417F42A02; 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a="327391587" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391587" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552778" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552778" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:19 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , NorbertX Ciosek Subject: [PATCH v3 14/15] common/idpf/base: add func to clean all DESCs on controlq Date: Wed, 26 Apr 2023 06:22:58 -0400 Message-Id: <20230426102259.205992-15-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add 'idpf_ctlq_clean_sq_force' which will clean all descriptors on given control queue. It is needed in case control plane is not running and we need to do proper driver cleanup. Signed-off-by: NorbertX Ciosek Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 56 ++++++++++++++++++-- drivers/common/idpf/base/idpf_controlq_api.h | 4 ++ 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 8381e4000f..9374fce71e 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -386,13 +386,15 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, } /** - * idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the - * requested queue + * __idpf_ctlq_clean_sq - helper function to reclaim descriptors on HW write + * back for the requested queue * @cq: pointer to the specific Control queue * @clean_count: (input|output) number of descriptors to clean as input, and * number of descriptors actually cleaned as output * @msg_status: (output) pointer to msg pointer array to be populated; needs * to be allocated by caller + * @force: (input) clean descriptors which were not done yet. Use with caution + * in kernel mode only * * Returns an array of message pointers associated with the cleaned * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned @@ -400,8 +402,8 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, * to send will have a non-zero status. The caller is expected to free original * ctlq_msgs and free or reuse the DMA buffers. */ -int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, - struct idpf_ctlq_msg *msg_status[]) +static int __idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[], bool force) { struct idpf_ctlq_desc *desc; u16 i = 0, num_to_clean; @@ -425,7 +427,7 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, for (i = 0; i < num_to_clean; i++) { /* Fetch next descriptor and check if marked as done */ desc = IDPF_CTLQ_DESC(cq, ntc); - if (!(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD)) + if (!force && !(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD)) break; desc_err = LE16_TO_CPU(desc->ret_val); @@ -435,6 +437,8 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, } msg_status[i] = cq->bi.tx_msg[ntc]; + if (!msg_status[i]) + break; msg_status[i]->status = desc_err; cq->bi.tx_msg[ntc] = NULL; @@ -457,6 +461,48 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, return ret; } +/** + * idpf_ctlq_clean_sq_force - reclaim all descriptors on HW write back for the + * requested queue. Use only in kernel mode. + * @cq: pointer to the specific Control queue + * @clean_count: (input|output) number of descriptors to clean as input, and + * number of descriptors actually cleaned as output + * @msg_status: (output) pointer to msg pointer array to be populated; needs + * to be allocated by caller + * + * Returns an array of message pointers associated with the cleaned + * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned + * descriptors. The status will be returned for each; any messages that failed + * to send will have a non-zero status. The caller is expected to free original + * ctlq_msgs and free or reuse the DMA buffers. + */ +int idpf_ctlq_clean_sq_force(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[]) +{ + return __idpf_ctlq_clean_sq(cq, clean_count, msg_status, true); +} + +/** + * idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the + * requested queue + * @cq: pointer to the specific Control queue + * @clean_count: (input|output) number of descriptors to clean as input, and + * number of descriptors actually cleaned as output + * @msg_status: (output) pointer to msg pointer array to be populated; needs + * to be allocated by caller + * + * Returns an array of message pointers associated with the cleaned + * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned + * descriptors. The status will be returned for each; any messages that failed + * to send will have a non-zero status. The caller is expected to free original + * ctlq_msgs and free or reuse the DMA buffers. + */ +int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[]) +{ + return __idpf_ctlq_clean_sq(cq, clean_count, msg_status, false); +} + /** * idpf_ctlq_post_rx_buffs - post buffers to descriptor ring * @hw: pointer to hw struct diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 80be282b42..a00faac05f 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -191,6 +191,10 @@ int idpf_ctlq_send(struct idpf_hw *hw, int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, struct idpf_ctlq_msg *q_msg); +/* Reclaims all descriptors on HW write back */ +int idpf_ctlq_clean_sq_force(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[]); + /* Reclaims send descriptors on HW write back */ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, struct idpf_ctlq_msg *msg_status[]); From patchwork Wed Apr 26 10:22:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126548 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 145F942A02; Wed, 26 Apr 2023 12:29:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 400A842D30; Wed, 26 Apr 2023 12:28:27 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id BBE2A42D88 for ; Wed, 26 Apr 2023 12:28:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504903; x=1714040903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lwipq/u+HkZ4PAEJ3zK6p34Kp3az5BMm+Xkh0ZAJolM=; b=av59Cg2/3de1IaqedYQeiO8929ETtEqGa7O89x9VKcX1swaafieBGlbP EOwnpScmIlN6YDH52hu0HncDTvR0RMXPW9Tu5VmFIQb+Bw5COZ5YizsGv lQ73ebANXxTkcXGR4gCreR9HQsSDxv80dF7sETzkFu94fhDwnQOzfKd9h 5L+OyAPk0SKj4mgAaWx5ZSxV6rAMVSbjshTnR5OcSSz8fisOmRoWVITc6 lAYIMuJ0AdQOSm4cuqS0OL4QcW9NrcjA680kQPHy0qgtYeT9A758mf5By +FPlAZCNY/pdlavCCeuNR1fNJan0590TLTj9IRM5HiQ8QE5w9PG59E7Vh g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391595" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391595" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552786" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552786" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:21 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao Subject: [PATCH v3 15/15] common/idpf/base: update license and README Date: Wed, 26 Apr 2023 06:22:59 -0400 Message-Id: <20230426102259.205992-16-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update license and README Signed-off-by: Wenjing Qiao --- .mailmap | 8 ++++++++ drivers/common/idpf/base/README | 4 ++-- drivers/common/idpf/base/idpf_alloc.h | 2 +- drivers/common/idpf/base/idpf_common.c | 2 +- drivers/common/idpf/base/idpf_controlq.c | 2 +- drivers/common/idpf/base/idpf_controlq.h | 2 +- drivers/common/idpf/base/idpf_controlq_api.h | 2 +- drivers/common/idpf/base/idpf_controlq_setup.c | 2 +- drivers/common/idpf/base/idpf_devids.h | 2 +- drivers/common/idpf/base/idpf_lan_pf_regs.h | 2 +- drivers/common/idpf/base/idpf_lan_txrx.h | 2 +- drivers/common/idpf/base/idpf_lan_vf_regs.h | 2 +- drivers/common/idpf/base/idpf_osdep.h | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- drivers/common/idpf/base/idpf_type.h | 2 +- drivers/common/idpf/base/meson.build | 2 +- drivers/common/idpf/base/siov_regs.h | 2 +- drivers/common/idpf/base/virtchnl2.h | 2 +- drivers/common/idpf/base/virtchnl2_lan_desc.h | 2 +- 19 files changed, 27 insertions(+), 19 deletions(-) diff --git a/.mailmap b/.mailmap index 0859104404..309b1bc69e 100644 --- a/.mailmap +++ b/.mailmap @@ -1603,3 +1603,11 @@ Ziye Yang Zoltan Kiss Zorik Machulsky Zyta Szpak +Charles Stoll +Nizan Zorea +Vinoth Kumar Chandra Mohan +NorbertX Ciosek +Pavan Kumar Linga +Jun Zhang +Priyalee Kushwaha +Kazatsker Kirill diff --git a/drivers/common/idpf/base/README b/drivers/common/idpf/base/README index 257ad6c4b1..693049c057 100644 --- a/drivers/common/idpf/base/README +++ b/drivers/common/idpf/base/README @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2022 Intel Corporation + * Copyright(c) 2021-2023 Intel Corporation */ Intel® IDPF driver ================== This directory contains source code of BSD-3-Clause idpf driver of version -2022.09.13 released by the team which develops basic drivers for Intel IPU. +2023.02.23 released by the team which develops basic drivers for Intel IPU. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below diff --git a/drivers/common/idpf/base/idpf_alloc.h b/drivers/common/idpf/base/idpf_alloc.h index bc054851b3..5cc4beb5cf 100644 --- a/drivers/common/idpf/base/idpf_alloc.h +++ b/drivers/common/idpf/base/idpf_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_ALLOC_H_ diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 17b2221624..6abe74afda 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "idpf_type.h" diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 9374fce71e..68aae6f321 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "idpf_controlq.h" diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h index 47bffcf79f..0fe0e94a37 100644 --- a/drivers/common/idpf/base/idpf_controlq.h +++ b/drivers/common/idpf/base/idpf_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_CONTROLQ_H_ diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index a00faac05f..ad649ab356 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_CONTROLQ_API_H_ diff --git a/drivers/common/idpf/base/idpf_controlq_setup.c b/drivers/common/idpf/base/idpf_controlq_setup.c index 3a272b1f8d..0f1b52a7e9 100644 --- a/drivers/common/idpf/base/idpf_controlq_setup.c +++ b/drivers/common/idpf/base/idpf_controlq_setup.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ diff --git a/drivers/common/idpf/base/idpf_devids.h b/drivers/common/idpf/base/idpf_devids.h index a91eb4e02a..c47762d5b7 100644 --- a/drivers/common/idpf/base/idpf_devids.h +++ b/drivers/common/idpf/base/idpf_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_DEVIDS_H_ diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 1c665d1f3b..8542620e01 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_LAN_PF_REGS_H_ diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 82742857be..ac925736d7 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_LAN_TXRX_H_ diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index c8739fae7a..b5ff9b2cc9 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_LAN_VF_REGS_H_ diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index abcf68f1a2..8a49a966ea 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_OSDEP_H_ diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index c9812a7f94..988ff00506 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_PROTOTYPE_H_ diff --git a/drivers/common/idpf/base/idpf_type.h b/drivers/common/idpf/base/idpf_type.h index 2a97d32a8b..a22d28f448 100644 --- a/drivers/common/idpf/base/idpf_type.h +++ b/drivers/common/idpf/base/idpf_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_TYPE_H_ diff --git a/drivers/common/idpf/base/meson.build b/drivers/common/idpf/base/meson.build index dc4b93c198..96d7642209 100644 --- a/drivers/common/idpf/base/meson.build +++ b/drivers/common/idpf/base/meson.build @@ -1,5 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2022 Intel Corporation +# Copyright(c) 2023 Intel Corporation sources += files( 'idpf_common.c', diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index 3ac4f8f177..fad329601a 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 1eaa436485..594bc26b8c 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _VIRTCHNL2_H_ diff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h index 0992cefc6c..e6e782a219 100644 --- a/drivers/common/idpf/base/virtchnl2_lan_desc.h +++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ /* * Copyright (C) 2019 Intel Corporation