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GET /api/patches/111995/?format=api
{ "id": 111995, "url": "http://patches.dpdk.org/api/patches/111995/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220528093311.123946-4-zhoumin@loongson.cn/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220528093311.123946-4-zhoumin@loongson.cn>", "list_archive_url": "https://inbox.dpdk.org/dev/20220528093311.123946-4-zhoumin@loongson.cn", "date": "2022-05-28T09:32:50", "name": "[v1,03/24] eal/loongarch: add cpu cycle operations for LoongArch", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6bc2cd2c4a8d072cf067d60b322dabac73921a04", "submitter": { "id": 2394, "url": "http://patches.dpdk.org/api/people/2394/?format=api", "name": "zhoumin", "email": "zhoumin@loongson.cn" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220528093311.123946-4-zhoumin@loongson.cn/mbox/", "series": [ { "id": 23222, "url": "http://patches.dpdk.org/api/series/23222/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23222", "date": "2022-05-28T09:32:50", "name": "Support LoongArch architecture", "version": 1, "mbox": "http://patches.dpdk.org/series/23222/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111995/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/111995/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B9158A0543;\n\tSat, 28 May 2022 11:33:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5624D4114A;\n\tSat, 28 May 2022 11:33:21 +0200 (CEST)", "from loongson.cn (mail.loongson.cn [114.242.206.163])\n by mails.dpdk.org (Postfix) with ESMTP id 3719A40E50\n for <dev@dpdk.org>; Sat, 28 May 2022 11:33:19 +0200 (CEST)", "from localhost.localdomain (unknown [10.2.5.185])\n by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S5;\n Sat, 28 May 2022 17:33:17 +0800 (CST)" ], "From": "Min Zhou <zhoumin@loongson.cn>", "To": "thomas@monjalon.net, david.marchand@redhat.com,\n bruce.richardson@intel.com,\n anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com,\n jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru", "Cc": "dev@dpdk.org,\n\tmaobibo@loongson.cn", "Subject": "[v1 03/24] eal/loongarch: add cpu cycle operations for LoongArch", "Date": "Sat, 28 May 2022 17:32:50 +0800", "Message-Id": "<20220528093311.123946-4-zhoumin@loongson.cn>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220528093311.123946-1-zhoumin@loongson.cn>", "References": "<20220528093311.123946-1-zhoumin@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf9Ax_+ZX7JFiWWUFAA--.26269S5", "X-Coremail-Antispam": "1UD129KBjvJXoWxGw1DXw47trWrXFWrXw1UJrb_yoW5ZrW8pr\n WUCFs3uw48Kr4xKrZ3X3s8WF1rJF4xCF9rGFyxAr40kr9rX34kua18KFW3AFyfXw4UuFyx\n XF4kWayY9FnrXw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU==", "X-CM-SenderInfo": "52kr3ztlq6z05rqj20fqof0/", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds architecture specific cpu cycle operations for\nLoongArch. The RDTIME.D instruction is used to read constant\nfrequency timer information including counter value. The CPUCFG\ninstruction is used to dynamically identify which features of\nLoongArch are implemented in the running processor during the\nexecution of the software. We can use this instruction to calculate\nthe frequency used by the timer.\n\nSigned-off-by: Min Zhou <zhoumin@loongson.cn>\n---\n lib/eal/loongarch/include/rte_cycles.h | 53 ++++++++++++++++++++++++++\n lib/eal/loongarch/rte_cycles.c | 45 ++++++++++++++++++++++\n 2 files changed, 98 insertions(+)\n create mode 100644 lib/eal/loongarch/include/rte_cycles.h\n create mode 100644 lib/eal/loongarch/rte_cycles.c", "diff": "diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h\nnew file mode 100644\nindex 0000000000..1f8f957faf\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_cycles.h\n@@ -0,0 +1,53 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef _RTE_CYCLES_LOONGARCH_H_\n+#define _RTE_CYCLES_LOONGARCH_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_cycles.h\"\n+\n+static inline uint64_t\n+get_cycle_count(void)\n+{\n+\tuint64_t count;\n+\n+\t__asm__ __volatile__ (\n+\t\t\"rdtime.d %[cycles], $zero\\n\"\n+\t\t: [cycles] \"=r\" (count)\n+\t\t::\n+\t\t);\n+\treturn count;\n+}\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\treturn get_cycle_count();\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\trte_mb();\n+\treturn rte_rdtsc();\n+}\n+\n+static inline uint64_t\n+rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CYCLES_LOONGARCH_H_ */\ndiff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c\nnew file mode 100644\nindex 0000000000..582601d335\n--- /dev/null\n+++ b/lib/eal/loongarch/rte_cycles.c\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#include \"eal_private.h\"\n+\n+#define LOONGARCH_CPUCFG4\t0x4\n+#define CPUCFG4_CCFREQ_MASK\t0xFFFFFFFF\n+#define CPUCFG4_CCFREQ_SHIFT\t0\n+\n+#define LOONGARCH_CPUCFG5\t0x5\n+#define CPUCFG5_CCMUL_MASK\t0xFFFF\n+#define CPUCFG5_CCMUL_SHIFT\t0\n+\n+#define CPUCFG5_CCDIV_MASK\t0xFFFF0000\n+#define CPUCFG5_CCDIV_SHIFT\t16\n+\n+static __rte_noinline uint32_t\n+read_cpucfg(int arg)\n+{\n+\tint ret = 0;\n+\n+\t__asm__ __volatile__ (\n+\t\t\"cpucfg %[var], %[index]\\n\"\n+\t\t: [var]\"=r\"(ret)\n+\t\t: [index]\"r\"(arg)\n+\t\t:\n+\t\t);\n+\n+\treturn ret;\n+}\n+\n+uint64_t\n+get_tsc_freq_arch(void)\n+{\n+\tuint32_t base_freq, mul_factor, div_factor;\n+\n+\tbase_freq = read_cpucfg(LOONGARCH_CPUCFG4);\n+\tmul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >>\n+\t\tCPUCFG5_CCMUL_SHIFT;\n+\tdiv_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >>\n+\t\tCPUCFG5_CCDIV_SHIFT;\n+\n+\treturn base_freq * mul_factor / div_factor;\n+}\n", "prefixes": [ "v1", "03/24" ] }