From patchwork Sat May 28 09:32:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 111998 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1303CA0543; Sat, 28 May 2022 11:33:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2E9FB42B70; Sat, 28 May 2022 11:33:25 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 6CA48410FA for ; Sat, 28 May 2022 11:33:19 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S3; Sat, 28 May 2022 17:33:16 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 01/24] eal/loongarch: add atomic operations for LoongArch Date: Sat, 28 May 2022 17:32:48 +0800 Message-Id: <20220528093311.123946-2-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S3 X-Coremail-Antispam: 1UD129KBjvJXoWxKFy8tr18ZF1rJF4DKFW7urg_yoWfZFy3pr WfCFnFqanaqF43Ga97Jr45Gw1rZw1I934UtrWYkry8ZFyIkw1kAa4xJryrtryUGaykurs8 GFs0kFWUGF17GaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds architecture specific atomic operations for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_atomic.h | 401 +++++++++++++++++++++++++ 1 file changed, 401 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_atomic.h diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h new file mode 100644 index 0000000000..4c7526b85d --- /dev/null +++ b/lib/eal/loongarch/include/rte_atomic.h @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_ATOMIC_LOONGARCH_H_ +#define _RTE_ATOMIC_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_atomic.h" + +/** + * LoongArch Synchronize + */ +static inline void synchronize(void) +{ + __asm__ __volatile__("dbar 0":::"memory"); +} + +/** + * General memory barrier. + * + * Guarantees that the LOAD and STORE operations generated before the + * barrier occur before the LOAD and STORE operations generated after. + * This function is architecture dependent. + */ +#define rte_mb() synchronize() + +/** + * Write memory barrier. + * + * Guarantees that the STORE operations generated before the barrier + * occur before the STORE operations generated after. + * This function is architecture dependent. + */ +#define rte_wmb() synchronize() + +/** + * Read memory barrier. + * + * Guarantees that the LOAD operations generated before the barrier + * occur before the LOAD operations generated after. + * This function is architecture dependent. + */ +#define rte_rmb() synchronize() + +#define rte_smp_mb() rte_mb() + +#define rte_smp_wmb() rte_mb() + +#define rte_smp_rmb() rte_mb() + +#define rte_io_mb() rte_mb() + +#define rte_io_wmb() rte_mb() + +#define rte_io_rmb() rte_mb() + +#define rte_io_mb() rte_mb() + +#define rte_cio_wmb() rte_wmb() + +#define rte_cio_rmb() rte_rmb() + +#define smp_mb__before_llsc() + +#define smp_llsc_mb() + +static __rte_always_inline void +rte_atomic_thread_fence(int memorder) +{ + __atomic_thread_fence(memorder); +} + +/* + * Helper Functions + */ +#define ATOMIC32_OP(op, I, asm_op) \ +static inline void la_atomic32_##op(rte_atomic32_t *v, int32_t i) \ +{ \ + __asm__ __volatile__( \ + "am"#asm_op"_db.w $zero, %[i], %[cnt]\n" \ + : [cnt] "+ZB" (v->cnt) \ + : [i] "r" (I) \ + : "memory" \ + ); \ +} + +#define ATOMIC32_OP_RETURN(op, I, asm_op) \ +static inline int32_t la_atomic32_##op##_and_return(rte_atomic32_t *v, int32_t i) \ +{ \ + int32_t result; \ + \ + __asm__ __volatile__( \ + "am"#asm_op"_db.w %1, %2, %0\n" \ + : "+ZB" (v->cnt), "=&r" (result) \ + : "r" (I) \ + : "memory" \ + ); \ + \ + return result + I; \ +} +ATOMIC32_OP(add, i, add) +ATOMIC32_OP(sub, -i, add) +ATOMIC32_OP_RETURN(add, i, add) +ATOMIC32_OP_RETURN(sub, -i, add) + +#define ATOMIC64_OP(op, I, asm_op) \ +static inline void la_atomic64_##op(rte_atomic64_t *v, int64_t i) \ +{ \ + __asm__ __volatile__( \ + "am"#asm_op"_db.d $zero, %[i], %[cnt]\n" \ + : [cnt] "+ZB" (v->cnt) \ + : [i] "r" (I) \ + : "memory" \ + ); \ +} +#define ATOMIC64_OP_RETURN(op, I, asm_op) \ +static inline int64_t la_atomic64_##op##_and_return(rte_atomic64_t *v, int64_t i) \ +{ \ + int64_t result; \ + \ + __asm__ __volatile__( \ + "am"#asm_op"_db.d %1, %2, %0\n" \ + : "+ZB" (v->cnt), "=&r" (result) \ + : "r" (I) \ + : "memory" \ + ); \ + \ + return result + I; \ +} +ATOMIC64_OP(add, i, add) +ATOMIC64_OP(sub, -i, add) +ATOMIC64_OP_RETURN(add, i, add) +ATOMIC64_OP_RETURN(sub, -i, add) + +static inline int +loongarch_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) +{ + uint32_t res = 0, temp = 0; + __asm__ __volatile__( + "1: ll.w %[tmp], %[dst]\n" + " li.w %[res], 0\n" + " bne %[tmp], %[exp], 2f\n" + " move %[tmp], %[src]\n" + " sc.w %[tmp], %[dst]\n" + " li.w %[res], 1\n" + " beqz %[tmp], 1b\n" + "2:\n" + : [res] "=&r"(res), + [tmp] "+&r"(temp), + [dst] "+m"(*dst) + : [src] "r"(src), + [exp] "r"(exp), + "m"(*dst) + : "memory" + ); + + return res; +} + +static inline int +loongarch_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) +{ + uint32_t res = 0; + uint64_t temp = 0; + __asm__ __volatile__( + "1: ll.d %[tmp], %[dst]\n" + " li.d %[res], 0\n" + " bne %[tmp], %[exp], 2f\n" + " move %[tmp], %[src]\n" + " sc.d %[tmp], %[dst]\n" + " li.d %[res], 1\n" + " beqz %[tmp], 1b\n" + "2:\n" + : [res] "=&r"(res), + [tmp] "+&r"(temp), + [dst] "+m"(*dst) + : [src] "r"(src), + [exp] "r"(exp), + "m"(*dst) + : "memory" + ); + + return res; +} + +#ifndef RTE_FORCE_INTRINSICS +static inline int +rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src) +{ + return __sync_bool_compare_and_swap(dst, exp, src); +} + +static inline int rte_atomic16_test_and_set(rte_atomic16_t *v) +{ + return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1); +} + +static inline void +rte_atomic16_inc(rte_atomic16_t *v) +{ + rte_atomic16_add(v, 1); +} + +static inline void +rte_atomic16_dec(rte_atomic16_t *v) +{ + rte_atomic16_sub(v, 1); +} + +static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v) +{ + return __sync_add_and_fetch(&v->cnt, 1) == 0; +} + +static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v) +{ + return __sync_sub_and_fetch(&v->cnt, 1) == 0; +} + +static inline uint16_t +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val) +{ + return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST); +} + +/*------------------------- 32 bit atomic operations -------------------------*/ + +static inline int +rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) +{ + return loongarch_atomic32_cmpset(dst, exp, src); +} + +static inline int rte_atomic32_test_and_set(rte_atomic32_t *v) +{ + return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1); +} + +static inline void +rte_atomic32_inc(rte_atomic32_t *v) +{ + la_atomic32_add(v, 1); +} + +static inline void +rte_atomic32_dec(rte_atomic32_t *v) +{ + la_atomic32_sub(v, 1); +} + +static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v) +{ + return la_atomic32_add_and_return(v, 1) == 0; +} + +static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v) +{ + return la_atomic32_sub_and_return(v, 1) == 0; +} + +static inline uint32_t +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val) +{ + uint32_t retval; + + __asm__ __volatile__ ( + "amswap_db.w %1, %z2, %0\n" + : "+ZB" (*dst), "=&r" (retval) + : "Jr" (val) + : "memory" + ); + + return retval; + +} +/*------------------------- 64 bit atomic operations -------------------------*/ +static inline int +rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) +{ + return loongarch_atomic64_cmpset(dst, exp, src); +} + +static inline void +rte_atomic64_init(rte_atomic64_t *v) +{ + __asm__ __volatile__( + "amand_db.d $zero, $zero, %[rj]\n" + : [rj]"+ZB"(v->cnt) + ); +} + +static inline int64_t +rte_atomic64_read(rte_atomic64_t *v) +{ + int64_t res = 0; + + __asm__ __volatile__( + "amadd_db.d %[res], $zero, %[cnt]\n" + : [res]"=&r"(res), [cnt]"+ZB"(v->cnt) + : + ); + return res; + +} + +static inline void +rte_atomic64_set(rte_atomic64_t *v, int64_t new_value) +{ + __asm__ __volatile__( + "amswap_db.d $zero, %[nv], %[cnt]\n" + : [cnt]"+ZB"(v->cnt) + : [nv]"r"(new_value) + ); +} + +static inline void +rte_atomic64_add(rte_atomic64_t *v, int64_t inc) +{ + la_atomic64_add(v, inc); +} + +static inline void +rte_atomic64_sub(rte_atomic64_t *v, int64_t dec) +{ + la_atomic64_sub(v, dec); +} + +static inline void +rte_atomic64_inc(rte_atomic64_t *v) +{ + la_atomic64_add(v, 1); +} + +static inline void +rte_atomic64_dec(rte_atomic64_t *v) +{ + la_atomic64_sub(v, 1); +} + +static inline int64_t +rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc) +{ + return la_atomic64_add_and_return(v, inc); +} + +static inline int64_t +rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec) +{ + return la_atomic64_sub_and_return(v, dec); +} + +static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v) +{ + return la_atomic64_add_and_return(v, 1) == 0; +} + +static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v) +{ + return la_atomic64_sub_and_return(v, 1) == 0; +} + +static inline int rte_atomic64_test_and_set(rte_atomic64_t *v) +{ + return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1); +} + +static inline void rte_atomic64_clear(rte_atomic64_t *v) +{ + rte_atomic64_set(v, 0); +} + +static inline uint64_t __xchg_u64(volatile uint64_t *m, uint64_t val) +{ + uint64_t retval; + __asm__ __volatile__ ( + "amswap_db.d %1, %z2, %0\n" + : "+ZB" (*m), "=&r" (retval) + : "Jr" (val) + : "memory" + ); + + return retval; +} + +static inline uint64_t +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val) +{ + return __xchg_u64(dst, val); +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 111996 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0880A0543; Sat, 28 May 2022 11:33:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3B84D427F3; Sat, 28 May 2022 11:33:23 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 397E940F35 for ; Sat, 28 May 2022 11:33:19 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S4; Sat, 28 May 2022 17:33:17 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 02/24] eal/loongarch: add byte order operations for LoongArch Date: Sat, 28 May 2022 17:32:49 +0800 Message-Id: <20220528093311.123946-3-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S4 X-Coremail-Antispam: 1UD129KBjvJXoW7AF43Jr4fur45tr45CrW3Wrg_yoW8CF47pF 15CFZxKr1rXr47t34Sy3W3Wrn8Zw1S9r1xK39rZrW3uF9rX3yfZr1qgrW7AryUuwn5urZ7 Xw4q9w4jga43Cw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds architecture specific byte order operations for LoongArch architecture. LoongArch bit designations are always little-endian. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_byteorder.h | 46 +++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_byteorder.h diff --git a/lib/eal/loongarch/include/rte_byteorder.h b/lib/eal/loongarch/include/rte_byteorder.h new file mode 100644 index 0000000000..2cda010256 --- /dev/null +++ b/lib/eal/loongarch/include/rte_byteorder.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_BYTEORDER_LOONGARCH_H_ +#define _RTE_BYTEORDER_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_byteorder.h" + +#ifndef RTE_FORCE_INTRINSICS +#define rte_bswap16(x) rte_constant_bswap16(x) +#define rte_bswap32(x) rte_constant_bswap32(x) +#define rte_bswap64(x) rte_constant_bswap64(x) +#endif + +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + +#define rte_cpu_to_le_16(x) (x) +#define rte_cpu_to_le_32(x) (x) +#define rte_cpu_to_le_64(x) (x) + +#define rte_cpu_to_be_16(x) rte_bswap16(x) +#define rte_cpu_to_be_32(x) rte_bswap32(x) +#define rte_cpu_to_be_64(x) rte_bswap64(x) + +#define rte_le_to_cpu_16(x) (x) +#define rte_le_to_cpu_32(x) (x) +#define rte_le_to_cpu_64(x) (x) + +#define rte_be_to_cpu_16(x) rte_bswap16(x) +#define rte_be_to_cpu_32(x) rte_bswap32(x) +#define rte_be_to_cpu_64(x) rte_bswap64(x) + +#else /* RTE_BIG_ENDIAN */ +#error "LoongArch not support big endian!" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_BYTEORDER_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 111995 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9158A0543; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5624D4114A; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 3719A40E50 for ; Sat, 28 May 2022 11:33:19 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S5; Sat, 28 May 2022 17:33:17 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 03/24] eal/loongarch: add cpu cycle operations for LoongArch Date: Sat, 28 May 2022 17:32:50 +0800 Message-Id: <20220528093311.123946-4-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S5 X-Coremail-Antispam: 1UD129KBjvJXoWxGw1DXw47trWrXFWrXw1UJrb_yoW5ZrW8pr WUCFs3uw48Kr4xKrZ3X3s8WF1rJF4xCF9rGFyxAr40kr9rX34kua18KFW3AFyfXw4UuFyx XF4kWayY9FnrXw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds architecture specific cpu cycle operations for LoongArch. The RDTIME.D instruction is used to read constant frequency timer information including counter value. The CPUCFG instruction is used to dynamically identify which features of LoongArch are implemented in the running processor during the execution of the software. We can use this instruction to calculate the frequency used by the timer. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_cycles.h | 53 ++++++++++++++++++++++++++ lib/eal/loongarch/rte_cycles.c | 45 ++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_cycles.h create mode 100644 lib/eal/loongarch/rte_cycles.c diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h new file mode 100644 index 0000000000..1f8f957faf --- /dev/null +++ b/lib/eal/loongarch/include/rte_cycles.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_CYCLES_LOONGARCH_H_ +#define _RTE_CYCLES_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_cycles.h" + +static inline uint64_t +get_cycle_count(void) +{ + uint64_t count; + + __asm__ __volatile__ ( + "rdtime.d %[cycles], $zero\n" + : [cycles] "=r" (count) + :: + ); + return count; +} + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static inline uint64_t +rte_rdtsc(void) +{ + return get_cycle_count(); +} + +static inline uint64_t +rte_rdtsc_precise(void) +{ + rte_mb(); + return rte_rdtsc(); +} + +static inline uint64_t +rte_get_tsc_cycles(void) { return rte_rdtsc(); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CYCLES_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c new file mode 100644 index 0000000000..582601d335 --- /dev/null +++ b/lib/eal/loongarch/rte_cycles.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "eal_private.h" + +#define LOONGARCH_CPUCFG4 0x4 +#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF +#define CPUCFG4_CCFREQ_SHIFT 0 + +#define LOONGARCH_CPUCFG5 0x5 +#define CPUCFG5_CCMUL_MASK 0xFFFF +#define CPUCFG5_CCMUL_SHIFT 0 + +#define CPUCFG5_CCDIV_MASK 0xFFFF0000 +#define CPUCFG5_CCDIV_SHIFT 16 + +static __rte_noinline uint32_t +read_cpucfg(int arg) +{ + int ret = 0; + + __asm__ __volatile__ ( + "cpucfg %[var], %[index]\n" + : [var]"=r"(ret) + : [index]"r"(arg) + : + ); + + return ret; +} + +uint64_t +get_tsc_freq_arch(void) +{ + uint32_t base_freq, mul_factor, div_factor; + + base_freq = read_cpucfg(LOONGARCH_CPUCFG4); + mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >> + CPUCFG5_CCMUL_SHIFT; + div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >> + CPUCFG5_CCDIV_SHIFT; + + return base_freq * mul_factor / div_factor; +} From patchwork Sat May 28 09:32:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 111999 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF5BDA0543; Sat, 28 May 2022 11:33:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1604442847; Sat, 28 May 2022 11:33:26 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id A871E41101 for ; Sat, 28 May 2022 11:33:19 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S6; Sat, 28 May 2022 17:33:17 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 04/24] eal/loongarch: add prefetch operations for LoongArch Date: Sat, 28 May 2022 17:32:51 +0800 Message-Id: <20220528093311.123946-5-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S6 X-Coremail-Antispam: 1UD129KBjvJXoW7Ar4kAry8WF4rurWxuw4xXrb_yoW8WFyDpF WDCr45Wa17Gry2ka9xJr4Fgw13Jwna9a42qrZ7Gw18JFnFq34xtrn7Kr9FyFW3G348GryY 9rsxua95WF1Uu3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds architecture specific prefetch operations for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_prefetch.h diff --git a/lib/eal/loongarch/include/rte_prefetch.h b/lib/eal/loongarch/include/rte_prefetch.h new file mode 100644 index 0000000000..0fd9262ea8 --- /dev/null +++ b/lib/eal/loongarch/include/rte_prefetch.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_PREFETCH_LOONGARCH_H_ +#define _RTE_PREFETCH_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_prefetch.h" + +static inline void rte_prefetch0(const volatile void *p) +{ + __builtin_prefetch((const void *)(uintptr_t)p, 0, 3); +} + +static inline void rte_prefetch1(const volatile void *p) +{ + __builtin_prefetch((const void *)(uintptr_t)p, 0, 2); +} + +static inline void rte_prefetch2(const volatile void *p) +{ + __builtin_prefetch((const void *)(uintptr_t)p, 0, 1); +} + +static inline void rte_prefetch_non_temporal(const volatile void *p) +{ + /* non-temporal version not available, fallback to rte_prefetch0 */ + rte_prefetch0(p); +} + +__rte_experimental +static inline void +rte_cldemote(const volatile void *p) +{ + RTE_SET_USED(p); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PREFETCH_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112000 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD16FA0543; Sat, 28 May 2022 11:33:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1BF6442B75; Sat, 28 May 2022 11:33:27 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id D4CBF4114A for ; Sat, 28 May 2022 11:33:19 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S7; Sat, 28 May 2022 17:33:18 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 05/24] eal/loongarch: add spinlock operations for LoongArch Date: Sat, 28 May 2022 17:32:52 +0800 Message-Id: <20220528093311.123946-6-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S7 X-Coremail-Antispam: 1UD129KBjvJXoWxArWDAr45trWxGrW8WFWkXrb_yoW5Gw4Upr W3CrnxJa1xWF1I9FWfAF1qqr15Jws29r17JrZxWw18trZrW3sxK3ykJr90v3WFqa47tFyD XFs0vr45GrW7G3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds spinlock operations for LoongArch architecture. These implementations refer to GLIBC pthread_spin_xxlock(). The underlying implementation is based on LoongArch atomic instructions (ie, AMSWAP_DB.W). Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_spinlock.h | 93 ++++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_spinlock.h diff --git a/lib/eal/loongarch/include/rte_spinlock.h b/lib/eal/loongarch/include/rte_spinlock.h new file mode 100644 index 0000000000..6b565dc4d9 --- /dev/null +++ b/lib/eal/loongarch/include/rte_spinlock.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_SPINLOCK_LOONGARCH_H_ +#define _RTE_SPINLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_spinlock.h" + +#ifndef RTE_FORCE_INTRINSICS +/* + * These implementations refer to GLIBC pthread_spin_xxlock(). + */ +static inline void +rte_spinlock_lock(rte_spinlock_t *sl) +{ + int val = 0; + + if (rte_atomic32_exchange((volatile uint32_t *)&sl->locked, 1) == 0) + return; + + do { + do { + val = sl->locked; + } while (val != 0); + + } while (rte_atomic32_exchange((volatile uint32_t *)&sl->locked, 1) == 1); +} + +static inline void +rte_spinlock_unlock(rte_spinlock_t *sl) +{ + sl->locked = 0; +} + +static inline int +rte_spinlock_trylock(rte_spinlock_t *sl) +{ + return rte_atomic32_exchange((volatile uint32_t *)&sl->locked, 1) == 0; +} +#endif + +static inline int rte_tm_supported(void) +{ + return 0; +} + +static inline void +rte_spinlock_lock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_lock(sl); /* fall-back */ +} + +static inline int +rte_spinlock_trylock_tm(rte_spinlock_t *sl) +{ + return rte_spinlock_trylock(sl); +} + +static inline void +rte_spinlock_unlock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_unlock(sl); +} + +static inline void +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_lock(slr); /* fall-back */ +} + +static inline void +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_unlock(slr); +} + +static inline int +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr) +{ + return rte_spinlock_recursive_trylock(slr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_SPINLOCK_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112001 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 63D33A0543; Sat, 28 May 2022 11:33:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0343A42B7B; Sat, 28 May 2022 11:33:28 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 9293840E50 for ; Sat, 28 May 2022 11:33:20 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S8; Sat, 28 May 2022 17:33:18 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 06/24] eal/loongarch: add cpu flag checks for LoongArch Date: Sat, 28 May 2022 17:32:53 +0800 Message-Id: <20220528093311.123946-7-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S8 X-Coremail-Antispam: 1UD129KBjvJXoWxAF4rur1kKryUCr47WFy5twb_yoWrWrWUpa yfCFy5Xw48Xr12k3yxXayjgF1rCF1xGF47AasxCw4Yva9rG34UZwsYkF93WF45A3yUXrnI gayY93y29FyUZw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch uses aux vector software register to get CPU flags and add CPU flag checking support for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++++ lib/eal/loongarch/rte_cpuflags.c | 94 ++++++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h create mode 100644 lib/eal/loongarch/rte_cpuflags.c diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h new file mode 100644 index 0000000000..d9121a00a8 --- /dev/null +++ b/lib/eal/loongarch/include/rte_cpuflags.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_CPUFLAGS_LOONGARCH_H_ +#define _RTE_CPUFLAGS_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enumeration of all CPU features supported + */ +enum rte_cpu_flag_t { + RTE_CPUFLAG_CPUCFG = 0, + RTE_CPUFLAG_LAM, + RTE_CPUFLAG_UAL, + RTE_CPUFLAG_FPU, + RTE_CPUFLAG_LSX, + RTE_CPUFLAG_LASX, + RTE_CPUFLAG_CRC32, + RTE_CPUFLAG_COMPLEX, + RTE_CPUFLAG_CRYPTO, + RTE_CPUFLAG_LVZ, + RTE_CPUFLAG_LBT_X86, + RTE_CPUFLAG_LBT_ARM, + RTE_CPUFLAG_LBT_MIPS, + /* The last item */ + RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */ +}; + +#include "generic/rte_cpuflags.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c new file mode 100644 index 0000000000..4abcd0fdb3 --- /dev/null +++ b/lib/eal/loongarch/rte_cpuflags.c @@ -0,0 +1,94 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "rte_cpuflags.h" + +#include +#include +#include +#include +#include + +/* Symbolic values for the entries in the auxiliary table */ +#define AT_HWCAP 16 +#define AT_HWCAP2 26 + +/* software based registers */ +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(CPUCFG, REG_HWCAP, 0) + FEAT_DEF(LAM, REG_HWCAP, 1) + FEAT_DEF(UAL, REG_HWCAP, 2) + FEAT_DEF(FPU, REG_HWCAP, 3) + FEAT_DEF(LSX, REG_HWCAP, 4) + FEAT_DEF(LASX, REG_HWCAP, 5) + FEAT_DEF(CRC32, REG_HWCAP, 6) + FEAT_DEF(COMPLEX, REG_HWCAP, 7) + FEAT_DEF(CRYPTO, REG_HWCAP, 8) + FEAT_DEF(LVZ, REG_HWCAP, 9) + FEAT_DEF(LBT_X86, REG_HWCAP, 10) + FEAT_DEF(LBT_ARM, REG_HWCAP, 11) + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12) +}; + +/* + * Read AUXV software register and get cpu features for LoongArch + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} + +void +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) +{ + memset(intrinsics, 0, sizeof(*intrinsics)); +} From patchwork Sat May 28 09:32:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112004 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DF3E1A0543; Sat, 28 May 2022 11:34:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E946142B8B; Sat, 28 May 2022 11:33:30 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 2E6DB410DC for ; Sat, 28 May 2022 11:33:20 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S9; Sat, 28 May 2022 17:33:18 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 07/24] eal/loongarch: add dummy vector memcpy for LoongArch Date: Sat, 28 May 2022 17:32:54 +0800 Message-Id: <20220528093311.123946-8-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S9 X-Coremail-Antispam: 1UD129KBjvJXoWxKFy8uw47CFykuw18CFWDXFb_yoW3JrWfpa s8Cr4rXr1kGa1fXFn3Xw1UJ3W3tFn7Zr1UKr4UZF1fAFs7A340grZrKrWrAFs5ua4xArW7 Xr48Wan8WayUW3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The hardware instructions based vector implementation for memcpy will come later. At present, this dummy implementation can also work. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_memcpy.h | 193 +++++++++++++++++++++++++ lib/eal/loongarch/include/rte_vect.h | 47 ++++++ 2 files changed, 240 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_memcpy.h create mode 100644 lib/eal/loongarch/include/rte_vect.h diff --git a/lib/eal/loongarch/include/rte_memcpy.h b/lib/eal/loongarch/include/rte_memcpy.h new file mode 100644 index 0000000000..98dc3dfc3b --- /dev/null +++ b/lib/eal/loongarch/include/rte_memcpy.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_MEMCPY_LOONGARCH_H_ +#define _RTE_MEMCPY_LOONGARCH_H_ + +#include +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_memcpy.h" + +static inline void +rte_mov16(uint8_t *dst, const uint8_t *src) +{ + *(xmm_t *)dst = *(const xmm_t *)src; +} + +static inline void +rte_mov32(uint8_t *dst, const uint8_t *src) +{ + rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16); + rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16); +} + +static inline void +rte_mov48(uint8_t *dst, const uint8_t *src) +{ + rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16); + rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16); + rte_mov16((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32); +} + +static inline void +rte_mov64(uint8_t *dst, const uint8_t *src) +{ + rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16); + rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16); + rte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16); + rte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16); +} + +static inline void +rte_mov128(uint8_t *dst, const uint8_t *src) +{ + rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16); + rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16); + rte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16); + rte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16); + rte_mov16((uint8_t *)dst + 4 * 16, (const uint8_t *)src + 4 * 16); + rte_mov16((uint8_t *)dst + 5 * 16, (const uint8_t *)src + 5 * 16); + rte_mov16((uint8_t *)dst + 6 * 16, (const uint8_t *)src + 6 * 16); + rte_mov16((uint8_t *)dst + 7 * 16, (const uint8_t *)src + 7 * 16); +} + +static inline void +rte_mov256(uint8_t *dst, const uint8_t *src) +{ + rte_mov128(dst, src); + rte_mov128(dst + 128, src + 128); +} + +#define rte_memcpy(dst, src, n) \ + rte_memcpy_func((dst), (src), (n)) + +static inline void * +rte_memcpy_func(void *dst, const void *src, size_t n) +{ + void *ret = dst; + + /* We can't copy < 16 bytes using XMM registers so do it manually. */ + if (n < 16) { + if (n & 0x01) { + *(uint8_t *)dst = *(const uint8_t *)src; + dst = (uint8_t *)dst + 1; + src = (const uint8_t *)src + 1; + } + if (n & 0x02) { + *(uint16_t *)dst = *(const uint16_t *)src; + dst = (uint16_t *)dst + 1; + src = (const uint16_t *)src + 1; + } + if (n & 0x04) { + *(uint32_t *)dst = *(const uint32_t *)src; + dst = (uint32_t *)dst + 1; + src = (const uint32_t *)src + 1; + } + if (n & 0x08) + *(uint64_t *)dst = *(const uint64_t *)src; + return ret; + } + + /* Special fast cases for <= 128 bytes */ + if (n <= 32) { + rte_mov16((uint8_t *)dst, (const uint8_t *)src); + rte_mov16((uint8_t *)dst - 16 + n, + (const uint8_t *)src - 16 + n); + return ret; + } + + if (n <= 64) { + rte_mov32((uint8_t *)dst, (const uint8_t *)src); + rte_mov32((uint8_t *)dst - 32 + n, + (const uint8_t *)src - 32 + n); + return ret; + } + + if (n <= 128) { + rte_mov64((uint8_t *)dst, (const uint8_t *)src); + rte_mov64((uint8_t *)dst - 64 + n, + (const uint8_t *)src - 64 + n); + return ret; + } + + /* + * For large copies > 128 bytes. This combination of 256, 64 and 16 byte + * copies was found to be faster than doing 128 and 32 byte copies as + * well. + */ + for ( ; n >= 256; n -= 256) { + rte_mov256((uint8_t *)dst, (const uint8_t *)src); + dst = (uint8_t *)dst + 256; + src = (const uint8_t *)src + 256; + } + + /* + * We split the remaining bytes (which will be less than 256) into + * 64byte (2^6) chunks. + * Using incrementing integers in the case labels of a switch statement + * encourages the compiler to use a jump table. To get incrementing + * integers, we shift the 2 relevant bits to the LSB position to first + * get decrementing integers, and then subtract. + */ + switch (3 - (n >> 6)) { + case 0x00: + rte_mov64((uint8_t *)dst, (const uint8_t *)src); + n -= 64; + dst = (uint8_t *)dst + 64; + src = (const uint8_t *)src + 64; /* fallthrough */ + case 0x01: + rte_mov64((uint8_t *)dst, (const uint8_t *)src); + n -= 64; + dst = (uint8_t *)dst + 64; + src = (const uint8_t *)src + 64; /* fallthrough */ + case 0x02: + rte_mov64((uint8_t *)dst, (const uint8_t *)src); + n -= 64; + dst = (uint8_t *)dst + 64; + src = (const uint8_t *)src + 64; /* fallthrough */ + default: + break; + } + + /* + * We split the remaining bytes (which will be less than 64) into + * 16byte (2^4) chunks, using the same switch structure as above. + */ + switch (3 - (n >> 4)) { + case 0x00: + rte_mov16((uint8_t *)dst, (const uint8_t *)src); + n -= 16; + dst = (uint8_t *)dst + 16; + src = (const uint8_t *)src + 16; /* fallthrough */ + case 0x01: + rte_mov16((uint8_t *)dst, (const uint8_t *)src); + n -= 16; + dst = (uint8_t *)dst + 16; + src = (const uint8_t *)src + 16; /* fallthrough */ + case 0x02: + rte_mov16((uint8_t *)dst, (const uint8_t *)src); + n -= 16; + dst = (uint8_t *)dst + 16; + src = (const uint8_t *)src + 16; /* fallthrough */ + default: + break; + } + + /* Copy any remaining bytes, without going beyond end of buffers */ + if (n != 0) + rte_mov16((uint8_t *)dst - 16 + n, + (const uint8_t *)src - 16 + n); + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MEMCPY_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h new file mode 100644 index 0000000000..f13a5931ef --- /dev/null +++ b/lib/eal/loongarch/include/rte_vect.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_VECT_LOONGARCH_H_ +#define _RTE_VECT_LOONGARCH_H_ + +#include +#include +#include "rte_common.h" +#include "generic/rte_vect.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_256 + +typedef union xmm { + int8_t i8[16]; + int16_t i16[8]; + int32_t i32[4]; + int64_t i64[2]; + uint8_t u8[16]; + uint16_t u16[8]; + uint32_t u32[4]; + uint64_t u64[2]; + double pd[2]; +} __rte_aligned(16) xmm_t; + +#define XMM_SIZE (sizeof(xmm_t)) +#define XMM_MASK (XMM_SIZE - 1) + +typedef union rte_xmm { + xmm_t x; + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; + double pd[XMM_SIZE / sizeof(double)]; +} __rte_aligned(16) rte_xmm_t; + +#ifdef __cplusplus +} +#endif + +#endif From patchwork Sat May 28 09:32:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112002 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58FAFA0543; Sat, 28 May 2022 11:34:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00BDC42B82; Sat, 28 May 2022 11:33:29 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 2E68040F35 for ; Sat, 28 May 2022 11:33:20 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S10; Sat, 28 May 2022 17:33:19 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 08/24] eal/loongarch: add io operations for LoongArch Date: Sat, 28 May 2022 17:32:55 +0800 Message-Id: <20220528093311.123946-9-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S10 X-Coremail-Antispam: 1UD129KBjvdXoW7Xry7Kw43AFykJr18JF45GFg_yoWfWFX_u3 4fGrWkCF48XFs2vFyYvFn5J345CF4fJF1kuF1rKrnrX3WYgr13Gws7XasFvFW2gw1xXFs3 ta9agwn5Zr4rKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds io operations for LoongArch architecture. Let it uses generic I/O implementation. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_io.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_io.h diff --git a/lib/eal/loongarch/include/rte_io.h b/lib/eal/loongarch/include/rte_io.h new file mode 100644 index 0000000000..af152a727a --- /dev/null +++ b/lib/eal/loongarch/include/rte_io.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_IO_LOONGARCH_H_ +#define _RTE_IO_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_io.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_IO_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112008 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A381EA0543; Sat, 28 May 2022 11:34:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C3CE042BA6; Sat, 28 May 2022 11:33:34 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 2EA8F4280B for ; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S11; Sat, 28 May 2022 17:33:19 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 09/24] eal/loongarch: add mcslock operations for LoongArch Date: Sat, 28 May 2022 17:32:56 +0800 Message-Id: <20220528093311.123946-10-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S11 X-Coremail-Antispam: 1UD129KBjvdXoWrtFyfKw4DCFyruF43Jw1rXrb_yoWfKrcE93 sayrW8Ca1rJFs8ZFWrArn3trWjkF4xXF1kuF1Fgrn3X3W5trn3Gwn5X347ZF43Kw4xXF4F yana9rn5Ar9YgjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds mcslock operations for LoongArch architecture. Let it uses generic mcslock implementation. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_mcslock.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_mcslock.h diff --git a/lib/eal/loongarch/include/rte_mcslock.h b/lib/eal/loongarch/include/rte_mcslock.h new file mode 100644 index 0000000000..c4484b66fa --- /dev/null +++ b/lib/eal/loongarch/include/rte_mcslock.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_MCSLOCK_LOONGARCH_H_ +#define _RTE_MCSLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_mcslock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MCSLOCK_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112003 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77C93A0543; Sat, 28 May 2022 11:34:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF71A42B84; Sat, 28 May 2022 11:33:29 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 54B3441101 for ; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S12; Sat, 28 May 2022 17:33:19 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 10/24] eal/loongarch: add pause operations for LoongArch Date: Sat, 28 May 2022 17:32:57 +0800 Message-Id: <20220528093311.123946-11-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S12 X-Coremail-Antispam: 1UD129KBjvdXoW7GF13tw17Jw4UGw48GFWxZwb_yoWDXrb_uw 1fJrWkGF48tFs7Za4YyFn5Jry0kFs7J3W7uF4fGrsrX3Z0qr17K3WxZwn7ZF4Igr18XFs3 G3ySgrn5Ar1rKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds architecture specific pause operations for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_pause.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_pause.h diff --git a/lib/eal/loongarch/include/rte_pause.h b/lib/eal/loongarch/include/rte_pause.h new file mode 100644 index 0000000000..438de23128 --- /dev/null +++ b/lib/eal/loongarch/include/rte_pause.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_PAUSE_LOONGARCH_H_ +#define _RTE_PAUSE_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rte_atomic.h" + +#include "generic/rte_pause.h" + +static inline void rte_pause(void) +{ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PAUSE_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112007 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3821A0543; Sat, 28 May 2022 11:34:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9C86942B99; Sat, 28 May 2022 11:33:33 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id ACA77427F3 for ; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S13; Sat, 28 May 2022 17:33:19 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 11/24] eal/loongarch: add pflock operations for LoongArch Date: Sat, 28 May 2022 17:32:58 +0800 Message-Id: <20220528093311.123946-12-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S13 X-Coremail-Antispam: 1UD129KBjvdXoWrtr4fXFWxCF45Kr4UWw47twb_yoWfuwb_u3 4fG3ykCa18JFZ5ZF95Ars5J3y0kF4fZF1kuF18Kr13W3WYqr1fCwn5Xw17ZF47Kwn7XFsx XF4fKrn5Ar4rKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds pflock operations for LoongArch architecture. Let it uses generic pflock implementation. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_pflock.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_pflock.h diff --git a/lib/eal/loongarch/include/rte_pflock.h b/lib/eal/loongarch/include/rte_pflock.h new file mode 100644 index 0000000000..39cc066f65 --- /dev/null +++ b/lib/eal/loongarch/include/rte_pflock.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ +#ifndef _RTE_PFLOCK_LOONGARCH_H_ +#define _RTE_PFLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_pflock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PFLOCK_LOONGARCH_H_ */ From patchwork Sat May 28 09:32:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112005 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B323FA0543; Sat, 28 May 2022 11:34:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C1D9742B90; Sat, 28 May 2022 11:33:31 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 9E41240E50 for ; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S14; Sat, 28 May 2022 17:33:20 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 12/24] eal/loongarch: add rwlock operations for LoongArch Date: Sat, 28 May 2022 17:32:59 +0800 Message-Id: <20220528093311.123946-13-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S14 X-Coremail-Antispam: 1UD129KBjvJXoW7Ww48tw1kCF43JFW3AF47Arb_yoW8Gw13pF Z7ur95Gw1xGr42qasIva1jvr1rA3Wxur1SqrWfGw40yr4avw4UuFs7XF98JFyUW3y7ArWD Xa1UuF4DCF1UGaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds rwlock operations for LoongArch architecture. The implementation is based on lib/eal/ppc/include/rte_rwlock.h. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_rwlock.h | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_rwlock.h diff --git a/lib/eal/loongarch/include/rte_rwlock.h b/lib/eal/loongarch/include/rte_rwlock.h new file mode 100644 index 0000000000..aac6f60120 --- /dev/null +++ b/lib/eal/loongarch/include/rte_rwlock.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_RWLOCK_LOONGARCH_H_ +#define _RTE_RWLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_rwlock.h" + +static inline void +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_lock(rwl); +} + +static inline void +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_unlock(rwl); +} + +static inline void +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_lock(rwl); +} + +static inline void +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_unlock(rwl); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_RWLOCK_LOONGARCH_H_ */ From patchwork Sat May 28 09:33:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112006 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79CD4A0543; Sat, 28 May 2022 11:34:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B356F42B93; Sat, 28 May 2022 11:33:32 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id D3024427FF for ; Sat, 28 May 2022 11:33:21 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S15; Sat, 28 May 2022 17:33:20 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 13/24] eal/loongarch: add ticketlock operations for LoongArch Date: Sat, 28 May 2022 17:33:00 +0800 Message-Id: <20220528093311.123946-14-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S15 X-Coremail-Antispam: 1UD129KBjvdXoWrurWDWF43Wr1rur13uF1kAFb_yoWDXFb_u3 4fCrWkKF48Ja95ZasYvwn5trWjkFWfX3W8uF48Kr17X3W5Kr13Gwn3J347ZF1SgryxWFWf XayfKr95ArWrKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds ticketlock operations for LoongArch architecture. Let it uses generic ticketlock implementation. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_ticketlock.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_ticketlock.h diff --git a/lib/eal/loongarch/include/rte_ticketlock.h b/lib/eal/loongarch/include/rte_ticketlock.h new file mode 100644 index 0000000000..3959bcae7b --- /dev/null +++ b/lib/eal/loongarch/include/rte_ticketlock.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_TICKETLOCK_LOONGARCH_H_ +#define _RTE_TICKETLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_ticketlock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_TICKETLOCK_LOONGARCH_H_ */ From patchwork Sat May 28 09:33:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112009 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EA70AA0543; Sat, 28 May 2022 11:34:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B4A9D42BAD; Sat, 28 May 2022 11:33:35 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 6550240E50 for ; Sat, 28 May 2022 11:33:22 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S16; Sat, 28 May 2022 17:33:20 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 14/24] eal/loongarch: add power operations for LoongArch Date: Sat, 28 May 2022 17:33:01 +0800 Message-Id: <20220528093311.123946-15-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S16 X-Coremail-Antispam: 1UD129KBjvJXoW7Zr1kXryrXw1DuF4rJr13Jwb_yoW5JF4fpF s8Crn8Kw4xCw13Xa17Xa4v9r4rWF48Cry7KFWIk34jkrZrXw4DZrsxtrn0yF1rAw1UJryI vw1UurWjgFy5WaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds power operations for LoongArch architecture. In fact, these operations are temporarily not supported on LoongArch. Signed-off-by: Min Zhou --- .../loongarch/include/rte_power_intrinsics.h | 20 ++++++++ lib/eal/loongarch/rte_power_intrinsics.c | 51 +++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c diff --git a/lib/eal/loongarch/include/rte_power_intrinsics.h b/lib/eal/loongarch/include/rte_power_intrinsics.h new file mode 100644 index 0000000000..b6a2c0d82e --- /dev/null +++ b/lib/eal/loongarch/include/rte_power_intrinsics.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_POWER_INTRINSIC_LOONGARCH_H_ +#define _RTE_POWER_INTRINSIC_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include "generic/rte_power_intrinsics.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_POWER_INTRINSIC_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/rte_power_intrinsics.c b/lib/eal/loongarch/rte_power_intrinsics.c new file mode 100644 index 0000000000..3dd1375ce4 --- /dev/null +++ b/lib/eal/loongarch/rte_power_intrinsics.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "rte_power_intrinsics.h" + +/** + * This function is not supported on LOONGARCH. + */ +int +rte_power_monitor(const struct rte_power_monitor_cond *pmc, + const uint64_t tsc_timestamp) +{ + RTE_SET_USED(pmc); + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} + +/** + * This function is not supported on LOONGARCH. + */ +int +rte_power_pause(const uint64_t tsc_timestamp) +{ + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} + +/** + * This function is not supported on LOONGARCH. + */ +int +rte_power_monitor_wakeup(const unsigned int lcore_id) +{ + RTE_SET_USED(lcore_id); + + return -ENOTSUP; +} + +int +rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[], + const uint32_t num, const uint64_t tsc_timestamp) +{ + RTE_SET_USED(pmc); + RTE_SET_USED(num); + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} From patchwork Sat May 28 09:33:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112011 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DA5CA0543; Sat, 28 May 2022 11:34:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6784642BB5; Sat, 28 May 2022 11:33:37 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id D7EF741101 for ; Sat, 28 May 2022 11:33:22 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S17; Sat, 28 May 2022 17:33:21 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 15/24] eal/loongarch: add hypervisor operations for LoongArch Date: Sat, 28 May 2022 17:33:02 +0800 Message-Id: <20220528093311.123946-16-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S17 X-Coremail-Antispam: 1UD129KBjvdXoW7GFW8Zr1UXF1UKw45trW7CFg_yoW3tFX_ur WxJ348KF4xJFZFga4F9r95JryxZ3Z2qF1rua4UXr47W3WUtrnxKrs8ZFnFv3y7tr17trsx G343ur1Fyr10gjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds hypervisor operations for LoongArch architecture. In fact, these operations are currently not supported on LoongArch. Signed-off-by: Min Zhou --- lib/eal/loongarch/rte_hypervisor.c | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 lib/eal/loongarch/rte_hypervisor.c diff --git a/lib/eal/loongarch/rte_hypervisor.c b/lib/eal/loongarch/rte_hypervisor.c new file mode 100644 index 0000000000..d044906f71 --- /dev/null +++ b/lib/eal/loongarch/rte_hypervisor.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "rte_hypervisor.h" + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + return RTE_HYPERVISOR_UNKNOWN; +} From patchwork Sat May 28 09:33:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112010 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 133B2A0543; Sat, 28 May 2022 11:34:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 901B342BB1; Sat, 28 May 2022 11:33:36 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id B57F3410DC for ; Sat, 28 May 2022 11:33:22 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S18; Sat, 28 May 2022 17:33:21 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 16/24] mem: add huge page size definition for LoongArch Date: Sat, 28 May 2022 17:33:03 +0800 Message-Id: <20220528093311.123946-17-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S18 X-Coremail-Antispam: 1UD129KBjvJXoW7Ar13uFW8GrykWF1kZrW5Jrb_yoW8XF1kpF yDuFy0kr409r4IyryI9rna93ZayayjkF4kGryjvw4UCF47Ka4xJr4jqrWUCFyxurWFgryU GFn8W3yj9rWjq3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LoongArch architecture has a different huge page size (32MB) than other architectures. This patch adds a new huge page size for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/include/rte_memory.h | 1 + lib/eal/include/rte_memzone.h | 1 + 2 files changed, 2 insertions(+) diff --git a/lib/eal/include/rte_memory.h b/lib/eal/include/rte_memory.h index 68b069fd04..dd9e6c0b89 100644 --- a/lib/eal/include/rte_memory.h +++ b/lib/eal/include/rte_memory.h @@ -30,6 +30,7 @@ extern "C" { #define RTE_PGSIZE_256K (1ULL << 18) #define RTE_PGSIZE_2M (1ULL << 21) #define RTE_PGSIZE_16M (1ULL << 24) +#define RTE_PGSIZE_32M (1ULL << 25) #define RTE_PGSIZE_256M (1ULL << 28) #define RTE_PGSIZE_512M (1ULL << 29) #define RTE_PGSIZE_1G (1ULL << 30) diff --git a/lib/eal/include/rte_memzone.h b/lib/eal/include/rte_memzone.h index 5db1210831..8129ba363b 100644 --- a/lib/eal/include/rte_memzone.h +++ b/lib/eal/include/rte_memzone.h @@ -35,6 +35,7 @@ extern "C" { #define RTE_MEMZONE_1GB 0x00000002 /**< Use 1GB pages. */ #define RTE_MEMZONE_16MB 0x00000100 /**< Use 16MB pages. */ #define RTE_MEMZONE_16GB 0x00000200 /**< Use 16GB pages. */ +#define RTE_MEMZONE_32MB 0x00000400 /**< Use 32MB pages. */ #define RTE_MEMZONE_256KB 0x00010000 /**< Use 256KB pages. */ #define RTE_MEMZONE_256MB 0x00020000 /**< Use 256MB pages. */ #define RTE_MEMZONE_512MB 0x00040000 /**< Use 512MB pages. */ From patchwork Sat May 28 09:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112013 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FE39A0543; Sat, 28 May 2022 11:35:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3E01942BBF; Sat, 28 May 2022 11:33:39 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 5205B4280B for ; Sat, 28 May 2022 11:33:23 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S19; Sat, 28 May 2022 17:33:21 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 17/24] eal/linux: set eal base address for LoongArch Date: Sat, 28 May 2022 17:33:04 +0800 Message-Id: <20220528093311.123946-18-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S19 X-Coremail-Antispam: 1UD129KBjvdXoWrAw4xJFWDAFyrWF1rJw48Xrb_yoWxWwc_W3 WxZry8WrsxtasxZan5KrsIyry5W3yxAw18ZF1xW3WfWa4DKw45J3yv9FZ5GFy3Cr12kFyr Aw4jg3savF1jgjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch sets a different eal base address for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/linux/eal_memory.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c index c890c42106..60fc8cc6ca 100644 --- a/lib/eal/linux/eal_memory.c +++ b/lib/eal/linux/eal_memory.c @@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void) * rte_mem_check_dma_mask for ensuring all memory is within supported * range. */ +#if defined(RTE_ARCH_LOONGARCH) + return 0x7000000000ULL; +#else return 0x100000000ULL; +#endif } /* From patchwork Sat May 28 09:33:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112012 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 269BCA0543; Sat, 28 May 2022 11:35:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 50E7342BB8; Sat, 28 May 2022 11:33:38 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 7BD81410DC for ; Sat, 28 May 2022 11:33:23 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S20; Sat, 28 May 2022 17:33:21 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 18/24] meson: introduce LoongArch architecture Date: Sat, 28 May 2022 17:33:05 +0800 Message-Id: <20220528093311.123946-19-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S20 X-Coremail-Antispam: 1UD129KBjvJXoWxAF45Zry3XF4kGFy5KFW5GFg_yoWrZw4rpF ZrZF15Kr48Wr1ftrsxX34jqw4rJwnrCa47Wa1SgrySkFZrKrykZ34kK3s8Xa4xAw18trWF qrs3Ga4YgF4UJw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds some meson.build files for building DPDK on LoongArch architecture. Signed-off-by: Min Zhou --- .../loongarch/loongarch_loongarch64_linux_gcc | 16 +++++++ config/loongarch/meson.build | 46 +++++++++++++++++++ lib/eal/loongarch/include/meson.build | 21 +++++++++ lib/eal/loongarch/meson.build | 11 +++++ meson.build | 2 + 5 files changed, 96 insertions(+) create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc create mode 100644 config/loongarch/meson.build create mode 100644 lib/eal/loongarch/include/meson.build create mode 100644 lib/eal/loongarch/meson.build diff --git a/config/loongarch/loongarch_loongarch64_linux_gcc b/config/loongarch/loongarch_loongarch64_linux_gcc new file mode 100644 index 0000000000..ca94dab705 --- /dev/null +++ b/config/loongarch/loongarch_loongarch64_linux_gcc @@ -0,0 +1,16 @@ +[binaries] +c = 'loongarch64-linux-gnu-gcc' +cpp = 'loongarch64-linux-gnu-cpp' +ar = 'loongarch64-linux-gnu-gcc-ar' +strip = 'loongarch64-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'loongarch64' +cpu = '3a5000' +endian = 'little' + +[properties] +implementor_id = 'generic' +implementor_pn = 'default' diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build new file mode 100644 index 0000000000..8d76ae1a19 --- /dev/null +++ b/config/loongarch/meson.build @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 Loongson Technology Corporation Limited + +if not dpdk_conf.get('RTE_ARCH_64') + error('Only 64-bit compiles are supported for this platform type') +endif +dpdk_conf.set('RTE_ARCH', 'loongarch') +dpdk_conf.set('RTE_ARCH_LOONGARCH', 1) +dpdk_conf.set('RTE_ARCH_NO_VECTOR', 1) + +# for checking defines we need to use the correct compiler flags +march_opt = '-march=@0@'.format(machine) + +machine_args_generic = [ + ['default', ['-march=loongarch64']], +] + +flags_generic = [ + ['RTE_MACHINE', '"loongarch64"'], + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 16], + ['RTE_CACHE_LINE_SIZE', 64]] + +impl_generic = ['Generic loongarch', flags_generic, machine_args_generic] + +machine = [] +machine_args = [] + +machine = impl_generic +impl_pn = 'default' + +message('Implementer : ' + machine[0]) +foreach flag: machine[1] + if flag.length() > 0 +dpdk_conf.set(flag[0], flag[1]) + endif +endforeach + +foreach marg: machine[2] + if marg[0] == impl_pn + foreach f: marg[1] + machine_args += f + endforeach + endif +endforeach +message(machine_args) diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build new file mode 100644 index 0000000000..d5699c5373 --- /dev/null +++ b/lib/eal/loongarch/include/meson.build @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 Loongson Technology Corporation Limited + +arch_headers = files( + 'rte_atomic.h', + 'rte_byteorder.h', + 'rte_cpuflags.h', + 'rte_cycles.h', + 'rte_io.h', + 'rte_mcslock.h', + 'rte_memcpy.h', + 'rte_pause.h', + 'rte_pflock.h', + 'rte_power_intrinsics.h', + 'rte_prefetch.h', + 'rte_rwlock.h', + 'rte_spinlock.h', + 'rte_ticketlock.h', + 'rte_vect.h', +) +install_headers(arch_headers, subdir: get_option('include_subdir_arch')) diff --git a/lib/eal/loongarch/meson.build b/lib/eal/loongarch/meson.build new file mode 100644 index 0000000000..e14b1ed431 --- /dev/null +++ b/lib/eal/loongarch/meson.build @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 Loongson Technology Corporation Limited + +subdir('include') + +sources += files( + 'rte_cpuflags.c', + 'rte_cycles.c', + 'rte_hypervisor.c', + 'rte_power_intrinsics.c', +) diff --git a/meson.build b/meson.build index 937f6110c0..573844dd2e 100644 --- a/meson.build +++ b/meson.build @@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st arch_subdir = 'arm' elif host_machine.cpu_family().startswith('ppc') arch_subdir = 'ppc' +elif host_machine.cpu_family().startswith('loongarch') + arch_subdir = 'loongarch' endif # configure the build, and make sure configs here and in config folder are From patchwork Sat May 28 09:33:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112016 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6DB5FA0543; Sat, 28 May 2022 11:35:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8B4142BCA; Sat, 28 May 2022 11:33:41 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 8D6C24280B for ; Sat, 28 May 2022 11:33:24 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S21; Sat, 28 May 2022 17:33:22 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 19/24] lpm: add dummy vector implementation for LoongArch Date: Sat, 28 May 2022 17:33:06 +0800 Message-Id: <20220528093311.123946-20-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S21 X-Coremail-Antispam: 1UD129KBjvJXoW3GF13Wry5Kr1fCFyDXFWkJFb_yoW7tryUp3 Z8GFyrKF40qw4fK39Yqr1qgF1S9F1vyr47tFZrGrnavFZxJw17ZFZ2yw1qv343XrW2va93 GF4xXr4UWF17ZaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The hardware instructions based vector implementation will come in a future patch. This dummy implementation can also work. Signed-off-by: Min Zhou --- app/test/test_xmmt_ops.h | 17 ++++++ lib/lpm/meson.build | 1 + lib/lpm/rte_lpm.h | 2 + lib/lpm/rte_lpm_lsx.h | 129 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 lib/lpm/rte_lpm_lsx.h diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h index 3a82d5ecac..7b2c3c37dd 100644 --- a/app/test/test_xmmt_ops.h +++ b/app/test/test_xmmt_ops.h @@ -49,6 +49,23 @@ vect_set_epi32(int i3, int i2, int i1, int i0) return data; } +#elif defined(RTE_ARCH_LOONGARCH) +/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/ +static __rte_always_inline xmm_t +vect_loadu_sil128(void *p) +{ + xmm_t data; + data = *(const xmm_t *)p; + return data; +} + +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ +static __rte_always_inline xmm_t +vect_set_epi32(int i3, int i2, int i1, int i0) +{ + xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3} }; + return data; +} #endif #endif /* _TEST_XMMT_OPS_H_ */ diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build index 78d91d3421..66df44b9b4 100644 --- a/lib/lpm/meson.build +++ b/lib/lpm/meson.build @@ -16,6 +16,7 @@ indirect_headers += files( 'rte_lpm_neon.h', 'rte_lpm_sse.h', 'rte_lpm_sve.h', + 'rte_lpm_lsx.h', ) deps += ['hash'] deps += ['rcu'] diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h index eb91960e81..7e94821212 100644 --- a/lib/lpm/rte_lpm.h +++ b/lib/lpm/rte_lpm.h @@ -405,6 +405,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], #endif #elif defined(RTE_ARCH_PPC_64) #include "rte_lpm_altivec.h" +#elif defined(RTE_ARCH_LOONGARCH) +#include "rte_lpm_lsx.h" #else #include "rte_lpm_sse.h" #endif diff --git a/lib/lpm/rte_lpm_lsx.h b/lib/lpm/rte_lpm_lsx.h new file mode 100644 index 0000000000..07942571e7 --- /dev/null +++ b/lib/lpm/rte_lpm_lsx.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_LPM_LSX_H_ +#define _RTE_LPM_LSX_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef RTE_ARCH_NO_VECTOR +static inline void +rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + xmm_t i24; + rte_xmm_t i8; + uint32_t tbl[4]; + uint64_t idx, pt, pt2; + const uint32_t *ptbl; + int i; + + const uint32_t mask = UINT8_MAX; + xmm_t mask8_tmp = (xmm_t){.u32 = {mask, mask, mask, mask} }; + + const xmm_t mask8 = mask8_tmp; + + /* + * RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries + * as one 64-bit value (0x0300000003000000). + */ + const uint64_t mask_xv = + ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK | + (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32); + + /* + * RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries + * as one 64-bit value (0x0100000001000000). + */ + const uint64_t mask_v = + ((uint64_t)RTE_LPM_LOOKUP_SUCCESS | + (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32); + + /* get 4 indexes for tbl24[]. */ + for (i = 0; i < 4; i++) + i24.u32[i] = ip.u32[i] >> CHAR_BIT; + + /* extract values from tbl24[] */ + idx = i24.i64[0]; + + ptbl = (const uint32_t *)&lpm->tbl24[(uint32_t)idx]; + tbl[0] = *ptbl; + ptbl = (const uint32_t *)&lpm->tbl24[idx >> 32]; + tbl[1] = *ptbl; + + idx = i24.i64[1]; + + ptbl = (const uint32_t *)&lpm->tbl24[(uint32_t)idx]; + tbl[2] = *ptbl; + ptbl = (const uint32_t *)&lpm->tbl24[idx >> 32]; + tbl[3] = *ptbl; + + /* get 4 indexes for tbl8[]. */ + for (i = 0; i < 2; i++) + i8.x.u64[i] = ip.u64[i] & mask8.u64[i]; + + pt = (uint64_t)tbl[0] | + (uint64_t)tbl[1] << 32; + pt2 = (uint64_t)tbl[2] | + (uint64_t)tbl[3] << 32; + + /* search successfully finished for all 4 IP addresses. */ + if (likely((pt & mask_xv) == mask_v) && + likely((pt2 & mask_xv) == mask_v)) { + *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES; + *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES; + return; + } + + if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[0] = i8.u32[0] + + (tbl[0] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]]; + tbl[0] = *ptbl; + } + if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[1] = i8.u32[1] + + (tbl[1] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[1]]; + tbl[1] = *ptbl; + } + if (unlikely((pt2 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[2] = i8.u32[2] + + (tbl[2] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[2]]; + tbl[2] = *ptbl; + } + if (unlikely((pt2 >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[3] = i8.u32[3] + + (tbl[3] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[3]]; + tbl[3] = *ptbl; + } + + hop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[0] & 0x00FFFFFF : defv; + hop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[1] & 0x00FFFFFF : defv; + hop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[2] & 0x00FFFFFF : defv; + hop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[3] & 0x00FFFFFF : defv; +} +#else +#error "The current version of LoongArch does not support vector!" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_LPM_LSX_H_ */ From patchwork Sat May 28 09:33:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112017 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 756C2A0543; Sat, 28 May 2022 11:35:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D826942BCE; Sat, 28 May 2022 11:33:42 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id B8CFD42847 for ; Sat, 28 May 2022 11:33:24 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S22; Sat, 28 May 2022 17:33:22 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 20/24] ixgbe: add dummy vector implementation for LoongArch Date: Sat, 28 May 2022 17:33:07 +0800 Message-Id: <20220528093311.123946-21-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S22 X-Coremail-Antispam: 1UD129KBjvJXoW7CFyftF13Gr43Cr1xtw4kCrg_yoW5Jr4kpF s7Gr4Svr1UXF47uwn3Xw13XrySga1vgFy7WF97C3s8ArZ3GrW8Cr9IqF1qvr95JrW8uF4x ur4DGrWUGa13G37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The purpose of this patch is used to fix building issues for LoongArch architecture. The hardware instructions based vector implementation will come in a future patch. Signed-off-by: Min Zhou --- drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c | 60 ++++++++++++++++++++++++++ drivers/net/ixgbe/meson.build | 2 + 2 files changed, 62 insertions(+) create mode 100644 drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c new file mode 100644 index 0000000000..412c8f937a --- /dev/null +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c @@ -0,0 +1,60 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "base/ixgbe_common.h" +#include "ixgbe_ethdev.h" +#include "ixgbe_rxtx.h" + +/* The vector support will come later */ +#ifdef RTE_ARCH_NO_VECTOR +int +ixgbe_rx_vec_dev_conf_condition_check(__rte_unused struct rte_eth_dev *dev) +{ + return -1; +} + +uint16_t +ixgbe_recv_pkts_vec(__rte_unused void *rx_queue, + __rte_unused struct rte_mbuf **rx_pkts, + __rte_unused uint16_t nb_pkts) +{ + return 0; +} + +uint16_t +ixgbe_recv_scattered_pkts_vec(__rte_unused void *rx_queue, + __rte_unused struct rte_mbuf **rx_pkts, + __rte_unused uint16_t nb_pkts) +{ + return 0; +} + +int +ixgbe_rxq_vec_setup(__rte_unused struct ixgbe_rx_queue *rxq) +{ + return -1; +} + +uint16_t +ixgbe_xmit_fixed_burst_vec(__rte_unused void *tx_queue, + __rte_unused struct rte_mbuf **tx_pkts, + __rte_unused uint16_t nb_pkts) +{ + return 0; +} + +int +ixgbe_txq_vec_setup(__rte_unused struct ixgbe_tx_queue *txq) +{ + return -1; +} + +void +ixgbe_rx_queue_release_mbufs_vec(__rte_unused struct ixgbe_rx_queue *rxq) +{ +} +#else +#error "The current version of LoongArch does not support vector!" +#endif diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build index 162f8d5f46..33c9a58ac8 100644 --- a/drivers/net/ixgbe/meson.build +++ b/drivers/net/ixgbe/meson.build @@ -29,6 +29,8 @@ if arch_subdir == 'x86' endif elif arch_subdir == 'arm' sources += files('ixgbe_rxtx_vec_neon.c') +elif arch_subdir == 'loongarch' + sources += files('ixgbe_rxtx_vec_lsx.c') endif includes += include_directories('base') From patchwork Sat May 28 09:33:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112015 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 33B41A0543; Sat, 28 May 2022 11:35:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 08D8842BC6; Sat, 28 May 2022 11:33:41 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id B34F04282A for ; Sat, 28 May 2022 11:33:24 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S23; Sat, 28 May 2022 17:33:23 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 21/24] i40e: add dummy vector implementation for LoongArch Date: Sat, 28 May 2022 17:33:08 +0800 Message-Id: <20220528093311.123946-22-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S23 X-Coremail-Antispam: 1UD129KBjvJXoW7CFyftF47tw18Jw43Wry5CFg_yoW5JrWUpF sxGF4aqr4UJF47Kwn3GF13urySqwn5tFy7GFZ3C3s09rZ3KFy8ZFy3JF1UX3s8ArykCrs2 9r4DCFy7Way3G37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The purpose of this patch is used to fix building issues for LoongArch architecture. The hardware instructions based vector implementation will come in a future patch. Signed-off-by: Min Zhou --- drivers/net/i40e/i40e_rxtx_vec_lsx.c | 54 ++++++++++++++++++++++++++++ drivers/net/i40e/meson.build | 2 ++ 2 files changed, 56 insertions(+) create mode 100644 drivers/net/i40e/i40e_rxtx_vec_lsx.c diff --git a/drivers/net/i40e/i40e_rxtx_vec_lsx.c b/drivers/net/i40e/i40e_rxtx_vec_lsx.c new file mode 100644 index 0000000000..727dc178f2 --- /dev/null +++ b/drivers/net/i40e/i40e_rxtx_vec_lsx.c @@ -0,0 +1,54 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "i40e_ethdev.h" +#include "i40e_rxtx.h" + +/* The vector support will come later */ +#ifdef RTE_ARCH_NO_VECTOR +uint16_t +i40e_recv_scattered_pkts_vec(__rte_unused void *rx_queue, + __rte_unused struct rte_mbuf **rx_pkts, + __rte_unused uint16_t nb_pkts) +{ + return 0; +} + +uint16_t +i40e_recv_pkts_vec(__rte_unused void *rx_queue, + __rte_unused struct rte_mbuf **rx_pkts, + __rte_unused uint16_t nb_pkts) +{ + return 0; +} +uint16_t +i40e_xmit_fixed_burst_vec(__rte_unused void *tx_queue, + __rte_unused struct rte_mbuf **tx_pkts, + __rte_unused uint16_t nb_pkts) +{ + return 0; +} +void __rte_cold +i40e_rx_queue_release_mbufs_vec(__rte_unused struct i40e_rx_queue *rxq) +{ +} +int __rte_cold +i40e_rxq_vec_setup(__rte_unused struct i40e_rx_queue *rxq) +{ + return -1; +} +int __rte_cold +i40e_txq_vec_setup(__rte_unused struct i40e_tx_queue *txq) +{ + return -1; +} +int __rte_cold +i40e_rx_vec_dev_conf_condition_check(__rte_unused struct rte_eth_dev *dev) +{ + return -1; +} +#else +#error "The current version of LoongArch does not support vector!" +#endif diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build index efc5f93e35..9775f05da1 100644 --- a/drivers/net/i40e/meson.build +++ b/drivers/net/i40e/meson.build @@ -75,6 +75,8 @@ elif arch_subdir == 'ppc' sources += files('i40e_rxtx_vec_altivec.c') elif arch_subdir == 'arm' sources += files('i40e_rxtx_vec_neon.c') +elif arch_subdir == 'loongarch' + sources += files('i40e_rxtx_vec_lsx.c') endif headers = files('rte_pmd_i40e.h') From patchwork Sat May 28 09:33:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112014 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D912EA0543; Sat, 28 May 2022 11:35:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 23F4842BC3; Sat, 28 May 2022 11:33:40 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id C3E7B42B6C for ; Sat, 28 May 2022 11:33:24 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S24; Sat, 28 May 2022 17:33:23 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 22/24] tap: add system call number for LoongArch Date: Sat, 28 May 2022 17:33:09 +0800 Message-Id: <20220528093311.123946-23-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S24 X-Coremail-Antispam: 1UD129KBjvdXoWruw43tF1xAw18Wr4rAFWkZwb_yoWxCFg_CF 47ZFs3JryUCF17tr4DuFZ5AFyFqr1UuF1kur97trWxuw4Dtr48Jryfu3yxZ3s8WrsxJan8 J34jqr1Yv347KjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds system call number of bpf for LoongArch architecture. Signed-off-by: Min Zhou --- drivers/net/tap/tap_bpf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h index f0b9fc7a2c..b1c9600ed8 100644 --- a/drivers/net/tap/tap_bpf.h +++ b/drivers/net/tap/tap_bpf.h @@ -93,7 +93,7 @@ union bpf_attr { # define __NR_bpf 321 # elif defined(__arm__) # define __NR_bpf 386 -# elif defined(__aarch64__) +# elif defined(__aarch64__) || defined(__loongarch__) # define __NR_bpf 280 # elif defined(__sparc__) # define __NR_bpf 349 From patchwork Sat May 28 09:33:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112018 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 971BEA0543; Sat, 28 May 2022 11:35:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B543A42BD3; Sat, 28 May 2022 11:33:43 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 5A36642B72 for ; Sat, 28 May 2022 11:33:25 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S25; Sat, 28 May 2022 17:33:23 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 23/24] memif: add system call number for LoongArch Date: Sat, 28 May 2022 17:33:10 +0800 Message-Id: <20220528093311.123946-24-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S25 X-Coremail-Antispam: 1UD129KBjvdXoWrKr4Dtw1kWF47ZF4DJF1DJrb_yoW3Cwb_W3 W7Xrsayr15CF1SgayxCrWSkFW8Jan8WF4kurySvry3AwnIqaykJr4fCry8tr90gr4vqw15 Grs2qr15urykKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds system call number of memfd_create for LoongArch architecture. Signed-off-by: Min Zhou --- drivers/net/memif/rte_eth_memif.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..b751037b79 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -174,7 +174,7 @@ const char *memif_version(void); #define __NR_memfd_create 1073742143 #elif defined __arm__ #define __NR_memfd_create 385 -#elif defined __aarch64__ +#elif defined __aarch64__ || defined __loongarch__ #define __NR_memfd_create 279 #elif defined __powerpc__ #define __NR_memfd_create 360 From patchwork Sat May 28 09:33:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhoumin X-Patchwork-Id: 112019 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E498A0543; Sat, 28 May 2022 11:35:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 90F9342BD8; Sat, 28 May 2022 11:33:44 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id BBB5840E50 for ; Sat, 28 May 2022 11:33:25 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax_+ZX7JFiWWUFAA--.26269S26; Sat, 28 May 2022 17:33:23 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v1 24/24] maintainers: claim responsibility for LoongArch Date: Sat, 28 May 2022 17:33:11 +0800 Message-Id: <20220528093311.123946-25-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn> References: <20220528093311.123946-1-zhoumin@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax_+ZX7JFiWWUFAA--.26269S26 X-Coremail-Antispam: 1UD129KBjvdXoW7XryUJFyfCw47tw4fAw45Awb_yoWxKwb_Za yxt3ySgryxGFn8Ga4FqF95A398Z3yIqF1UuFnrXwnrAayDt3s8Jr1vywna9w1akrWfGrZI qa1UXrySkr1aqjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds claim responsibility for LoongArch architecture. Signed-off-by: Min Zhou --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 17a0559ee7..69ea00cddf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -269,6 +269,15 @@ F: lib/eal/include/rte_random.h F: lib/eal/common/rte_random.c F: app/test/test_rand_perf.c +LoongArch +M: Min Zhou +F: config/loongarch/ +F: lib/eal/loongarch/ +F: lib/*/*_lsx.* +F: drivers/*/*/*_lsx.* +F: app/*/*_lsx.* +F: examples/*/*_lsx.* + ARM v7 M: Jan Viktorin M: Ruifeng Wang