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GET /api/patches/108203/?format=api
{ "id": 108203, "url": "http://patches.dpdk.org/api/patches/108203/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-3-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224031029.14049-3-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224031029.14049-3-suanmingm@nvidia.com", "date": "2022-02-24T03:10:17", "name": "[v3,02/14] net/mlx5: add HW steering low-level abstract code", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "74394a48b0c60a14a7114bfa3e9ea78eda8c3ae7", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-3-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21839, "url": "http://patches.dpdk.org/api/series/21839/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21839", "date": "2022-02-24T03:10:16", "name": "net/mlx5: add hardware steering", "version": 3, "mbox": "http://patches.dpdk.org/series/21839/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108203/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/108203/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F1FD5A0353;\n\tThu, 24 Feb 2022 04:10:57 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BF18141155;\n\tThu, 24 Feb 2022 04:10:55 +0100 (CET)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam07on2049.outbound.protection.outlook.com [40.107.95.49])\n by mails.dpdk.org (Postfix) with ESMTP id 84D784114D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 02/14] net/mlx5: add HW steering low-level abstract code", "Date": "Thu, 24 Feb 2022 05:10:17 +0200", "Message-ID": "<20220224031029.14049-3-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220224031029.14049-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>\n <20220224031029.14049-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "60c6af8a-dc8d-464d-edb3-08d9f74342a1", "X-MS-TrafficTypeDiagnostic": "DM4PR12MB5118:EE_", "X-Microsoft-Antispam-PRVS": "\n <DM4PR12MB51184C40C695CA04791F1C4AC13D9@DM4PR12MB5118.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n bHAmlm/sjxusUmp1kW83IxpgkcO6at39oMEV9Jvx0o4F2YDZY1EbcqgbXsHsQb+5RVx5BBTKQyclHJXrR1shV2v8PmBoPsZayP7aY6jb8A0rK07qUBQxc85QcPLCs1kbPIKBAPz/bwtiLyofk0Auin9oIs2ZsZwc16CE2PYnjU0/YO6IpBFxFtayspv2IdqfOCCEvF3TXS325tj2YrHtpML1te9jYUT1z3btTXe7MVh4KmTfVefKPUT3WlzqP8CmqZ4CE9T5G2g41l4JQlCZF8edEQvtnmgkds7sjoSgBezcOh4wM/io+vKd6yG6aof7wQd2gO8keXP8EGtbMXbLmugdjaSOsOTAF+AAXNacHfSMXYYLs6ERbEiJWbob7nnRiByvIyrjl+WIwtiv4YO22yeWakfj/gLeenYR5/iRcwMWW4Gwav0hMYmLJbypdbANHBJTn1NUT2cEUmeP58OGRrSpAIzTkU8JwQ4+qYBUBZ9piSW3BXMoqoSYUmM+jg5VPWTymJ37cQ7tbQwtTEhJA1vb1B7Z8j3BzIRcx3a6Au74LQFmzfPFm+ZRa4dIuJUUyezz+ZIQ/XXH+PrIijUBzdJrEm0IDS2tPExGqdU26Zg/ETjlXMAUT4sVB/CJvR/Z5F/bZDvN86HgqCO1sWxMflqh3NWfizSKF27r3Wejc1Q60NvX2HXB18aW0iCqOsDYUGUK9vWn3gXT8rJWqaqVhA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(426003)(336012)(36756003)(5660300002)(508600001)(6286002)(2616005)(47076005)(40460700003)(26005)(186003)(36860700001)(16526019)(55016003)(6636002)(1076003)(4326008)(8676002)(70206006)(70586007)(316002)(6666004)(81166007)(82310400004)(7696005)(30864003)(2906002)(110136005)(356005)(54906003)(8936002)(83380400001)(86362001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Feb 2022 03:10:50.0851 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 60c6af8a-dc8d-464d-edb3-08d9f74342a1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT068.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5118", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The HW steering low-level implementation will be added later in another\npatch series. To avoid the linkage issues the abstract stub replacement\nis provided currently.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/meson.build | 1 +\n drivers/net/mlx5/mlx5_dr.c | 383 +++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_dr.h | 456 +++++++++++++++++++++++++++++++++++\n 3 files changed, 840 insertions(+)\n create mode 100644 drivers/net/mlx5/mlx5_dr.c\n create mode 100644 drivers/net/mlx5/mlx5_dr.h", "diff": "diff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex 39a2b8c523..393b2c97ac 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -14,6 +14,7 @@ sources = files(\n 'mlx5.c',\n 'mlx5_ethdev.c',\n 'mlx5_flow.c',\n+\t'mlx5_dr.c',\n 'mlx5_flow_meter.c',\n 'mlx5_flow_dv.c',\n 'mlx5_flow_hw.c',\ndiff --git a/drivers/net/mlx5/mlx5_dr.c b/drivers/net/mlx5/mlx5_dr.c\nnew file mode 100644\nindex 0000000000..7218708986\n--- /dev/null\n+++ b/drivers/net/mlx5/mlx5_dr.c\n@@ -0,0 +1,383 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.\n+ */\n+#include <rte_flow.h>\n+\n+#include \"mlx5_defs.h\"\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n+#include \"mlx5_dr.h\"\n+\n+/*\n+ * The following null stubs are prepared in order not to break the linkage\n+ * before the HW steering low-level implementation is added.\n+ */\n+\n+/* Open a context used for direct rule insertion using hardware steering.\n+ * Each context can contain multiple tables of different types.\n+ *\n+ * @param[in] ibv_ctx\n+ *\tThe ibv context to used for HWS.\n+ * @param[in] attr\n+ *\tAttributes used for context open.\n+ * @return pointer to mlx5dr_context on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_context *\n+mlx5dr_context_open(void *ibv_ctx,\n+\t\t struct mlx5dr_context_attr *attr)\n+{\n+\t(void)ibv_ctx;\n+\t(void)attr;\n+\treturn NULL;\n+}\n+\n+/* Close a context used for direct hardware steering.\n+ *\n+ * @param[in] ctx\n+ *\tmlx5dr context to close.\n+ * @return zero on success non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_context_close(struct mlx5dr_context *ctx)\n+{\n+\t(void)ctx;\n+\treturn 0;\n+}\n+\n+/* Create a new direct rule table. Each table can contain multiple matchers.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new table will be opened.\n+ * @param[in] attr\n+ *\tAttributes used for table creation.\n+ * @return pointer to mlx5dr_table on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_table *\n+mlx5dr_table_create(struct mlx5dr_context *ctx,\n+\t\t struct mlx5dr_table_attr *attr)\n+{\n+\t(void)ctx;\n+\t(void)attr;\n+\treturn NULL;\n+}\n+\n+/* Destroy direct rule table.\n+ *\n+ * @param[in] tbl\n+ *\tmlx5dr table to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+__rte_weak int mlx5dr_table_destroy(struct mlx5dr_table *tbl)\n+{\n+\t(void)tbl;\n+\treturn 0;\n+}\n+\n+/* Create new match template based on items mask, the match template\n+ * will be used for matcher creation.\n+ *\n+ * @param[in] items\n+ *\tDescribe the mask for template creation\n+ * @param[in] flags\n+ *\tTemplate creation flags\n+ * @return pointer to mlx5dr_match_template on success NULL otherwise\n+ */\n+__rte_weak struct mlx5dr_match_template *\n+mlx5dr_match_template_create(const struct rte_flow_item items[],\n+\t\t\t enum mlx5dr_match_template_flags flags)\n+{\n+\t(void)items;\n+\t(void)flags;\n+\treturn NULL;\n+}\n+\n+/* Destroy match template.\n+ *\n+ * @param[in] mt\n+ *\tMatch template to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt)\n+{\n+\t(void)mt;\n+\treturn 0;\n+}\n+\n+/* Create a new direct rule matcher. Each matcher can contain multiple rules.\n+ * Matchers on the table will be processed by priority. Matching fields and\n+ * mask are described by the match template. In some cases multiple match\n+ * templates can be used on the same matcher.\n+ *\n+ * @param[in] table\n+ *\tThe table in which the new matcher will be opened.\n+ * @param[in] mt\n+ *\tArray of match templates to be used on matcher.\n+ * @param[in] num_of_mt\n+ *\tNumber of match templates in mt array.\n+ * @param[in] attr\n+ *\tAttributes used for matcher creation.\n+ * @return pointer to mlx5dr_matcher on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_matcher *\n+mlx5dr_matcher_create(struct mlx5dr_table *table __rte_unused,\n+\t\t struct mlx5dr_match_template *mt[] __rte_unused,\n+\t\t uint8_t num_of_mt __rte_unused,\n+\t\t struct mlx5dr_matcher_attr *attr __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Destroy direct rule matcher.\n+ *\n+ * @param[in] matcher\n+ *\tMatcher to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_matcher_destroy(struct mlx5dr_matcher *matcher __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+/* Enqueue create rule operation.\n+ *\n+ * @param[in] matcher\n+ *\tThe matcher in which the new rule will be created.\n+ * @param[in] mt_idx\n+ *\tMatch template index to create the rule with.\n+ * @param[in] items\n+ *\tThe items used for the value matching.\n+ * @param[in] rule_actions\n+ *\tRule action to be executed on match.\n+ * @param[in] num_of_actions\n+ *\tNumber of rule actions.\n+ * @param[in] attr\n+ *\tRule creation attributes.\n+ * @param[in, out] rule_handle\n+ *\tA valid rule handle. The handle doesn't require any initialization.\n+ * @return zero on successful enqueue non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_rule_create(struct mlx5dr_matcher *matcher __rte_unused,\n+\t\t uint8_t mt_idx __rte_unused,\n+\t\t const struct rte_flow_item items[] __rte_unused,\n+\t\t struct mlx5dr_rule_action rule_actions[] __rte_unused,\n+\t\t uint8_t num_of_actions __rte_unused,\n+\t\t struct mlx5dr_rule_attr *attr __rte_unused,\n+\t\t struct mlx5dr_rule *rule_handle __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+/* Enqueue destroy rule operation.\n+ *\n+ * @param[in] rule\n+ *\tThe rule destruction to enqueue.\n+ * @param[in] attr\n+ *\tRule destruction attributes.\n+ * @return zero on successful enqueue non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_rule_destroy(struct mlx5dr_rule *rule __rte_unused,\n+\t\t struct mlx5dr_rule_attr *attr __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+/* Create direct rule drop action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_dest_drop(struct mlx5dr_context *ctx __rte_unused,\n+\t\t\t uint32_t flags __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Create direct rule default miss action.\n+ * Defaults are RX: Drop TX: Wire.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_default_miss(struct mlx5dr_context *ctx __rte_unused,\n+\t\t\t\t uint32_t flags __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Create direct rule goto table action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] tbl\n+ *\tDestination table.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_dest_table(struct mlx5dr_context *ctx __rte_unused,\n+\t\t\t\tstruct mlx5dr_table *tbl __rte_unused,\n+\t\t\t\tuint32_t flags __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Create direct rule goto TIR action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] obj\n+ *\tDirect rule TIR devx object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx __rte_unused,\n+\t\t\t struct mlx5dr_devx_obj *obj __rte_unused,\n+\t\t\t uint32_t flags __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Create direct rule TAG action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_tag(struct mlx5dr_context *ctx __rte_unused,\n+\t\t\t uint32_t flags __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Create direct rule counter action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] obj\n+ *\tDirect rule counter devx object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_counter(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *obj,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule reformat action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] reformat_type\n+ *\tType of reformat.\n+ * @param[in] data_sz\n+ *\tSize in bytes of data.\n+ * @param[in] inline_data\n+ *\tHeader data array in case of inline action.\n+ * @param[in] log_bulk_size\n+ *\tNumber of unique values used with this pattern.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_reformat(struct mlx5dr_context *ctx __rte_unused,\n+\t enum mlx5dr_action_reformat_type reformat_type __rte_unused,\n+\t\t\t size_t data_sz __rte_unused,\n+\t\t\t void *inline_data __rte_unused,\n+\t\t\t uint32_t log_bulk_size __rte_unused,\n+\t\t\t uint32_t flags __rte_unused)\n+{\n+\treturn NULL;\n+}\n+\n+/* Create direct rule modify header action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] pattern_sz\n+ *\tByte size of the pattern array.\n+ * @param[in] pattern\n+ *\tPRM format modify pattern action array.\n+ * @param[in] log_bulk_size\n+ *\tNumber of unique values used with this pattern.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+__rte_weak struct mlx5dr_action *\n+mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n+\t\t\t\t size_t pattern_sz,\n+\t\t\t\t rte_be64_t pattern[],\n+\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t uint32_t flags);\n+\n+/* Destroy direct rule action.\n+ *\n+ * @param[in] action\n+ *\tThe action to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_action_destroy(struct mlx5dr_action *action __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+/* Poll queue for rule creation and deletions completions.\n+ *\n+ * @param[in] ctx\n+ *\tThe context to which the queue belong to.\n+ * @param[in] queue_id\n+ *\tThe id of the queue to poll.\n+ * @param[in, out] res\n+ *\tCompletion array.\n+ * @param[in] res_nb\n+ *\tMaximum number of results to return.\n+ * @return negative number on failure, the number of completions otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_send_queue_poll(struct mlx5dr_context *ctx __rte_unused,\n+\t\t uint16_t queue_id __rte_unused,\n+\t\t struct rte_flow_op_result res[] __rte_unused,\n+\t\t uint32_t res_nb __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+/* Perform an action on the queue\n+ *\n+ * @param[in] ctx\n+ *\tThe context to which the queue belong to.\n+ * @param[in] queue_id\n+ *\tThe id of the queue to perform the action on.\n+ * @param[in] actions\n+ *\tActions to perform on the queue. (enum mlx5dr_send_queue_actions)\n+ * @return zero on success non zero otherwise.\n+ */\n+__rte_weak int\n+mlx5dr_send_queue_action(struct mlx5dr_context *ctx __rte_unused,\n+\t\t\t uint16_t queue_id __rte_unused,\n+\t\t\t uint32_t actions __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+#endif\ndiff --git a/drivers/net/mlx5/mlx5_dr.h b/drivers/net/mlx5/mlx5_dr.h\nnew file mode 100644\nindex 0000000000..d0b2c15652\n--- /dev/null\n+++ b/drivers/net/mlx5/mlx5_dr.h\n@@ -0,0 +1,456 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.\n+ */\n+\n+#ifndef MLX5_DR_H_\n+#define MLX5_DR_H_\n+\n+#include <rte_flow.h>\n+\n+struct mlx5dr_context;\n+struct mlx5dr_table;\n+struct mlx5dr_matcher;\n+struct mlx5dr_rule;\n+\n+enum mlx5dr_table_type {\n+\tMLX5DR_TABLE_TYPE_NIC_RX,\n+\tMLX5DR_TABLE_TYPE_NIC_TX,\n+\tMLX5DR_TABLE_TYPE_FDB,\n+\tMLX5DR_TABLE_TYPE_MAX,\n+};\n+\n+enum mlx5dr_matcher_resource_mode {\n+\t/* Allocate resources based on number of rules with minimal failure probability */\n+\tMLX5DR_MATCHER_RESOURCE_MODE_RULE,\n+\t/* Allocate fixed size hash table based on given column and rows */\n+\tMLX5DR_MATCHER_RESOURCE_MODE_HTABLE,\n+};\n+\n+enum mlx5dr_action_flags {\n+\tMLX5DR_ACTION_FLAG_ROOT_RX = 1 << 0,\n+\tMLX5DR_ACTION_FLAG_ROOT_TX = 1 << 1,\n+\tMLX5DR_ACTION_FLAG_ROOT_FDB = 1 << 2,\n+\tMLX5DR_ACTION_FLAG_HWS_RX = 1 << 3,\n+\tMLX5DR_ACTION_FLAG_HWS_TX = 1 << 4,\n+\tMLX5DR_ACTION_FLAG_HWS_FDB = 1 << 5,\n+\tMLX5DR_ACTION_FLAG_INLINE = 1 << 6,\n+};\n+\n+enum mlx5dr_action_reformat_type {\n+\tMLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2,\n+\tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2,\n+\tMLX5DR_ACTION_REFORMAT_TYPE_TNL_L3_TO_L2,\n+\tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3,\n+};\n+\n+enum mlx5dr_match_template_flags {\n+\t/* Allow relaxed matching by skipping derived dependent match fields. */\n+\tMLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH = 1,\n+};\n+\n+enum mlx5dr_send_queue_actions {\n+\t/* Start executing all pending queued rules and write to HW */\n+\tMLX5DR_SEND_QUEUE_ACTION_DRAIN = 1 << 0,\n+};\n+\n+struct mlx5dr_context_attr {\n+\tuint16_t queues;\n+\tuint16_t queue_size;\n+\tsize_t initial_log_ste_memory;\n+\t/* Optional PD used for allocating res ources */\n+\tstruct ibv_pd *pd;\n+};\n+\n+struct mlx5dr_table_attr {\n+\tenum mlx5dr_table_type type;\n+\tuint32_t level;\n+};\n+\n+struct mlx5dr_matcher_attr {\n+\tuint32_t priority;\n+\tenum mlx5dr_matcher_resource_mode mode;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint8_t sz_row_log;\n+\t\t\tuint8_t sz_col_log;\n+\t\t} table;\n+\n+\t\tstruct {\n+\t\t\tuint8_t num_log;\n+\t\t} rule;\n+\t};\n+};\n+\n+struct mlx5dr_rule_attr {\n+\tuint16_t queue_id;\n+\tvoid *user_data;\n+\tuint32_t burst:1;\n+};\n+\n+struct mlx5dr_devx_obj {\n+\tstruct mlx5dv_devx_obj *obj;\n+\tuint32_t id;\n+};\n+\n+struct mlx5dr_rule_action {\n+\tstruct mlx5dr_action *action;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t value;\n+\t\t} tag;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t} counter;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tuint8_t *data;\n+\t\t} modify_header;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tuint8_t *data;\n+\t\t} reformat;\n+\n+\t\tstruct {\n+\t\t\trte_be32_t vlan_hdr;\n+\t\t} push_vlan;\n+\t};\n+};\n+\n+enum {\n+\tMLX5DR_MATCH_TAG_SZ = 32,\n+\tMLX5DR_JAMBO_TAG_SZ = 44,\n+};\n+\n+enum mlx5dr_rule_status {\n+\tMLX5DR_RULE_STATUS_UNKNOWN,\n+\tMLX5DR_RULE_STATUS_CREATING,\n+\tMLX5DR_RULE_STATUS_CREATED,\n+\tMLX5DR_RULE_STATUS_DELETING,\n+\tMLX5DR_RULE_STATUS_DELETED,\n+\tMLX5DR_RULE_STATUS_FAILED,\n+};\n+\n+struct mlx5dr_rule {\n+\tstruct mlx5dr_matcher *matcher;\n+\tunion {\n+\t\tuint8_t match_tag[MLX5DR_MATCH_TAG_SZ];\n+\t\tstruct ibv_flow *flow;\n+\t};\n+\tenum mlx5dr_rule_status status;\n+\tuint32_t rtc_used; /* The RTC into which the STE was inserted */\n+};\n+\n+/* Open a context used for direct rule insertion using hardware steering.\n+ * Each context can contain multiple tables of different types.\n+ *\n+ * @param[in] ibv_ctx\n+ *\tThe ibv context to used for HWS.\n+ * @param[in] attr\n+ *\tAttributes used for context open.\n+ * @return pointer to mlx5dr_context on success NULL otherwise.\n+ */\n+struct mlx5dr_context *\n+mlx5dr_context_open(void *ibv_ctx,\n+\t\t struct mlx5dr_context_attr *attr);\n+\n+/* Close a context used for direct hardware steering.\n+ *\n+ * @param[in] ctx\n+ *\tmlx5dr context to close.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_context_close(struct mlx5dr_context *ctx);\n+\n+/* Create a new direct rule table. Each table can contain multiple matchers.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new table will be opened.\n+ * @param[in] attr\n+ *\tAttributes used for table creation.\n+ * @return pointer to mlx5dr_table on success NULL otherwise.\n+ */\n+struct mlx5dr_table *\n+mlx5dr_table_create(struct mlx5dr_context *ctx,\n+\t\t struct mlx5dr_table_attr *attr);\n+\n+/* Destroy direct rule table.\n+ *\n+ * @param[in] tbl\n+ *\tmlx5dr table to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_table_destroy(struct mlx5dr_table *tbl);\n+\n+/* Create new match template based on items mask, the match template\n+ * will be used for matcher creation.\n+ *\n+ * @param[in] items\n+ *\tDescribe the mask for template creation\n+ * @param[in] flags\n+ *\tTemplate creation flags\n+ * @return pointer to mlx5dr_match_template on success NULL otherwise\n+ */\n+struct mlx5dr_match_template *\n+mlx5dr_match_template_create(const struct rte_flow_item items[],\n+\t\t\t enum mlx5dr_match_template_flags flags);\n+\n+/* Destroy match template.\n+ *\n+ * @param[in] mt\n+ *\tMatch template to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt);\n+\n+/* Create a new direct rule matcher. Each matcher can contain multiple rules.\n+ * Matchers on the table will be processed by priority. Matching fields and\n+ * mask are described by the match template. In some cases multiple match\n+ * templates can be used on the same matcher.\n+ *\n+ * @param[in] table\n+ *\tThe table in which the new matcher will be opened.\n+ * @param[in] mt\n+ *\tArray of match templates to be used on matcher.\n+ * @param[in] num_of_mt\n+ *\tNumber of match templates in mt array.\n+ * @param[in] attr\n+ *\tAttributes used for matcher creation.\n+ * @return pointer to mlx5dr_matcher on success NULL otherwise.\n+ */\n+struct mlx5dr_matcher *\n+mlx5dr_matcher_create(struct mlx5dr_table *table,\n+\t\t struct mlx5dr_match_template *mt[],\n+\t\t uint8_t num_of_mt,\n+\t\t struct mlx5dr_matcher_attr *attr);\n+\n+/* Destroy direct rule matcher.\n+ *\n+ * @param[in] matcher\n+ *\tMatcher to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_matcher_destroy(struct mlx5dr_matcher *matcher);\n+\n+/* Get the size of the rule handle (mlx5dr_rule) to be used on rule creation.\n+ *\n+ * @return size in bytes of rule handle struct.\n+ */\n+size_t mlx5dr_rule_get_handle_size(void);\n+\n+/* Enqueue create rule operation.\n+ *\n+ * @param[in] matcher\n+ *\tThe matcher in which the new rule will be created.\n+ * @param[in] mt_idx\n+ *\tMatch template index to create the rule with.\n+ * @param[in] items\n+ *\tThe items used for the value matching.\n+ * @param[in] rule_actions\n+ *\tRule action to be executed on match.\n+ * @param[in] num_of_actions\n+ *\tNumber of rule actions.\n+ * @param[in] attr\n+ *\tRule creation attributes.\n+ * @param[in, out] rule_handle\n+ *\tA valid rule handle. The handle doesn't require any initialization.\n+ * @return zero on successful enqueue non zero otherwise.\n+ */\n+int mlx5dr_rule_create(struct mlx5dr_matcher *matcher,\n+\t\t uint8_t mt_idx,\n+\t\t const struct rte_flow_item items[],\n+\t\t struct mlx5dr_rule_action rule_actions[],\n+\t\t uint8_t num_of_actions,\n+\t\t struct mlx5dr_rule_attr *attr,\n+\t\t struct mlx5dr_rule *rule_handle);\n+\n+/* Enqueue destroy rule operation.\n+ *\n+ * @param[in] rule\n+ *\tThe rule destruction to enqueue.\n+ * @param[in] attr\n+ *\tRule destruction attributes.\n+ * @return zero on successful enqueue non zero otherwise.\n+ */\n+int mlx5dr_rule_destroy(struct mlx5dr_rule *rule,\n+\t\t\tstruct mlx5dr_rule_attr *attr);\n+\n+/* Create direct rule drop action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_drop(struct mlx5dr_context *ctx,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule default miss action.\n+ * Defaults are RX: Drop TX: Wire.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_default_miss(struct mlx5dr_context *ctx,\n+\t\t\t\t uint32_t flags);\n+\n+/* Create direct rule goto table action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] tbl\n+ *\tDestination table.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_table(struct mlx5dr_context *ctx,\n+\t\t\t\tstruct mlx5dr_table *tbl,\n+\t\t\t\tuint32_t flags);\n+\n+/* Create direct rule goto TIR action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] obj\n+ *\tDirect rule TIR devx object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *obj,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule TAG action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_tag(struct mlx5dr_context *ctx,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule counter action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] obj\n+ *\tDirect rule counter devx object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_counter(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *obj,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule reformat action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] reformat_type\n+ *\tType of reformat.\n+ * @param[in] data_sz\n+ *\tSize in bytes of data.\n+ * @param[in] inline_data\n+ *\tHeader data array in case of inline action.\n+ * @param[in] log_bulk_size\n+ *\tNumber of unique values used with this pattern.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_reformat(struct mlx5dr_context *ctx,\n+\t\t\t enum mlx5dr_action_reformat_type reformat_type,\n+\t\t\t size_t data_sz,\n+\t\t\t void *inline_data,\n+\t\t\t uint32_t log_bulk_size,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule modify header action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] pattern_sz\n+ *\tByte size of the pattern array.\n+ * @param[in] pattern\n+ *\tPRM format modify pattern action array.\n+ * @param[in] log_bulk_size\n+ *\tNumber of unique values used with this pattern.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n+\t\t\t\t size_t pattern_sz,\n+\t\t\t\t rte_be64_t pattern[],\n+\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t uint32_t flags);\n+\n+/* Destroy direct rule action.\n+ *\n+ * @param[in] action\n+ *\tThe action to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_action_destroy(struct mlx5dr_action *action);\n+\n+/* Poll queue for rule creation and deletions completions.\n+ *\n+ * @param[in] ctx\n+ *\tThe context to which the queue belong to.\n+ * @param[in] queue_id\n+ *\tThe id of the queue to poll.\n+ * @param[in, out] res\n+ *\tCompletion array.\n+ * @param[in] res_nb\n+ *\tMaximum number of results to return.\n+ * @return negative number on failure, the number of completions otherwise.\n+ */\n+int mlx5dr_send_queue_poll(struct mlx5dr_context *ctx,\n+\t\t\t uint16_t queue_id,\n+\t\t\t struct rte_flow_op_result res[],\n+\t\t\t uint32_t res_nb);\n+\n+/* Perform an action on the queue\n+ *\n+ * @param[in] ctx\n+ *\tThe context to which the queue belong to.\n+ * @param[in] queue_id\n+ *\tThe id of the queue to perform the action on.\n+ * @param[in] actions\n+ *\tActions to perform on the queue. (enum mlx5dr_send_queue_actions)\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_send_queue_action(struct mlx5dr_context *ctx,\n+\t\t\t uint16_t queue_id,\n+\t\t\t uint32_t actions);\n+\n+/* Dump HWS info\n+ *\n+ * @param[in] ctx\n+ *\tThe context which to dump the info from.\n+ * @param[in] f\n+ *\tThe file to write the dump to.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f);\n+\n+#endif\n", "prefixes": [ "v3", "02/14" ] }