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GET /api/patches/105107/?format=api
{ "id": 105107, "url": "http://patches.dpdk.org/api/patches/105107/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213111345.5046-1-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213111345.5046-1-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213111345.5046-1-pbhagavatula@marvell.com", "date": "2021-12-13T11:13:43", "name": "[v5,1/2] event/cnxk: update min interval calculation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b78c60278d8daa1ded266ee80b325782bdb2aaed", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213111345.5046-1-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 20928, "url": "http://patches.dpdk.org/api/series/20928/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20928", "date": "2021-12-13T11:13:43", "name": "[v5,1/2] event/cnxk: update min interval calculation", "version": 5, "mbox": "http://patches.dpdk.org/series/20928/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105107/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105107/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A670FA0032;\n\tMon, 13 Dec 2021 12:13:57 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 247D7406A2;\n\tMon, 13 Dec 2021 12:13:57 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 7E71940042\n for <dev@dpdk.org>; Mon, 13 Dec 2021 12:13:56 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BD7ivsC027548;\n Mon, 13 Dec 2021 03:13:53 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cx21kgp28-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Dec 2021 03:13:53 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Dec 2021 03:13:51 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 13 Dec 2021 03:13:51 -0800", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id D16B43F7068;\n Mon, 13 Dec 2021 03:13:48 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=cl9u1nlvNP7SLsP6UvPP76VQSLVEwuCh1ioMQ3xJvFM=;\n b=Spq45e6ZxpzaaLNjARLfbnMn76GpsW1gxIvapgSuohq3K7i8/XMR3iWPI/GO1sTnH4z1\n 2ztpPSiXcNGBTy+jP5NhMd4WYhCITWqYhE+NiQn/xKrJG4zl0LZMF04aKDsAjIMLMZ0x\n v4MLnj0SIOrGhjnAsZPfDdPTd5GeuXy6uRJbeAGKW/hhQveExYLGDicgkL5wedOx+y73\n giJSenv7pKj8qJcAAwhiALVGS4NKGoQrPyLygA7zd/7YelAU50CMlCDf4yJnaBdogx48\n /KHudVxy3r0Y+Lalb2B+CE58LZoFbdk7jh9pWrOufk4oEuxyXexJU0ynmxtCIzMJYnJf Vg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, \"Pavan\n Nikhilesh\" <pbhagavatula@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v5 1/2] event/cnxk: update min interval calculation", "Date": "Mon, 13 Dec 2021 16:43:43 +0530", "Message-ID": "<20211213111345.5046-1-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211009080426.18482-1-pbhagavatula@marvell.com>", "References": "<20211009080426.18482-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "-8ngeY_fbDhq4j5p_o5roMYx_7DZ-Hqx", "X-Proofpoint-ORIG-GUID": "-8ngeY_fbDhq4j5p_o5roMYx_7DZ-Hqx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_04,2021-12-13_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nMinimum supported interval should now be retrieved from\nmailbox based on the clock source and clock frequency.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\nv5:\n- Rebase on master.\nv4:\n- Rebase on master, fix NULL checks.\nv3:\n- Add new mbox interface.\nv2:\n- Fixed devargs parsing and rebased.\n\n drivers/common/cnxk/roc_tim.c | 32 +++++++++++-\n drivers/common/cnxk/roc_tim.h | 9 +++-\n drivers/common/cnxk/version.map | 1 +\n drivers/event/cnxk/cnxk_tim_evdev.c | 69 +++++++++++++++++-------\n drivers/event/cnxk/cnxk_tim_evdev.h | 81 +++++++++++++++++------------\n 5 files changed, 138 insertions(+), 54 deletions(-)\n\n--\n2.17.1", "diff": "diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c\nindex 534b697bee..cefd9bc89d 100644\n--- a/drivers/common/cnxk/roc_tim.c\n+++ b/drivers/common/cnxk/roc_tim.c\n@@ -145,7 +145,7 @@ int\n roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \t\t enum roc_tim_clk_src clk_src, uint8_t ena_periodic,\n \t\t uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz,\n-\t\t uint32_t interval)\n+\t\t uint32_t interval, uint64_t intervalns, uint64_t clockfreq)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n \tstruct tim_config_req *req;\n@@ -162,6 +162,8 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \treq->enableperiodic = ena_periodic;\n \treq->enabledontfreebuffer = ena_dfb;\n \treq->interval = interval;\n+\treq->intervalns = intervalns;\n+\treq->clockfreq = clockfreq;\n \treq->gpioedge = TIM_GPIO_LTOH_TRANS;\n\n \trc = mbox_process(dev->mbox);\n@@ -173,6 +175,34 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \treturn 0;\n }\n\n+int\n+roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src,\n+\t\t uint64_t clockfreq, uint64_t *intervalns,\n+\t\t uint64_t *interval)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct tim_intvl_req *req;\n+\tstruct tim_intvl_rsp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_tim_get_min_intvl(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\n+\treq->clockfreq = clockfreq;\n+\treq->clocksource = clk_src;\n+\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn rc;\n+\t}\n+\n+\t*intervalns = rsp->intvl_ns;\n+\t*interval = rsp->intvl_cyc;\n+\n+\treturn 0;\n+}\n+\n int\n roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n {\ndiff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h\nindex 159b021a31..392732eae2 100644\n--- a/drivers/common/cnxk/roc_tim.h\n+++ b/drivers/common/cnxk/roc_tim.h\n@@ -10,6 +10,8 @@ enum roc_tim_clk_src {\n \tROC_TIM_CLK_SRC_GPIO,\n \tROC_TIM_CLK_SRC_GTI,\n \tROC_TIM_CLK_SRC_PTP,\n+\tROC_TIM_CLK_SRC_SYNCE,\n+\tROC_TIM_CLK_SRC_BTS,\n \tROC_TIM_CLK_SRC_INVALID,\n };\n\n@@ -33,7 +35,12 @@ int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \t\t\t\tenum roc_tim_clk_src clk_src,\n \t\t\t\tuint8_t ena_periodic, uint8_t ena_dfb,\n \t\t\t\tuint32_t bucket_sz, uint32_t chunk_sz,\n-\t\t\t\tuint32_t interval);\n+\t\t\t\tuint32_t interval, uint64_t intervalns,\n+\t\t\t\tuint64_t clockfreq);\n+int __roc_api roc_tim_lf_interval(struct roc_tim *roc_tim,\n+\t\t\t\t enum roc_tim_clk_src clk_src,\n+\t\t\t\t uint64_t clockfreq, uint64_t *intervalns,\n+\t\t\t\t uint64_t *interval);\n int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id,\n \t\t\t uint64_t *clk);\n int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id);\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 07c6720f0c..5379ed2d39 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -346,6 +346,7 @@ INTERNAL {\n \troc_tim_lf_disable;\n \troc_tim_lf_enable;\n \troc_tim_lf_free;\n+\troc_tim_lf_interval;\n \troc_se_ctx_swap;\n\n \tlocal: *;\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex 99b3acee7c..becab1d1b1 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -2,6 +2,8 @@\n * Copyright(C) 2021 Marvell.\n */\n\n+#include <math.h>\n+\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_tim_evdev.h\"\n\n@@ -120,7 +122,10 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n {\n \tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n \tstruct cnxk_tim_evdev *dev = cnxk_tim_priv_get();\n+\tuint64_t min_intvl_ns, min_intvl_cyc;\n \tstruct cnxk_tim_ring *tim_ring;\n+\tenum roc_tim_clk_src clk_src;\n+\tuint64_t clk_freq = 0;\n \tint i, rc;\n\n \tif (dev == NULL)\n@@ -139,25 +144,52 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \t\tgoto tim_ring_free;\n \t}\n\n-\tif (NSEC2TICK(RTE_ALIGN_MUL_CEIL(\n-\t\t\t rcfg->timer_tick_ns,\n-\t\t\t cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),\n-\t\t cnxk_tim_cntfrq()) <\n-\t cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {\n-\t\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)\n-\t\t\trcfg->timer_tick_ns = TICK2NSEC(\n-\t\t\t\tcnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),\n-\t\t\t\tcnxk_tim_cntfrq());\n-\t\telse {\n+\tclk_src = cnxk_tim_convert_clk_src(rcfg->clk_src);\n+\tif (clk_src == ROC_TIM_CLK_SRC_INVALID) {\n+\t\tplt_err(\"Invalid clock source\");\n+\t\tgoto tim_hw_free;\n+\t}\n+\n+\trc = cnxk_tim_get_clk_freq(dev, clk_src, &clk_freq);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to get clock frequency\");\n+\t\tgoto tim_hw_free;\n+\t}\n+\n+\trc = roc_tim_lf_interval(&dev->tim, clk_src, clk_freq, &min_intvl_ns,\n+\t\t\t\t &min_intvl_cyc);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to get min interval details\");\n+\t\tgoto tim_hw_free;\n+\t}\n+\n+\tif (rcfg->timer_tick_ns < min_intvl_ns) {\n+\t\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) {\n+\t\t\trcfg->timer_tick_ns = min_intvl_ns;\n+\t\t} else {\n \t\t\trc = -ERANGE;\n \t\t\tgoto tim_hw_free;\n \t\t}\n \t}\n+\n+\tif (rcfg->timer_tick_ns > rcfg->max_tmo_ns) {\n+\t\tplt_err(\"Max timeout to too high\");\n+\t\trc = -ERANGE;\n+\t\tgoto tim_hw_free;\n+\t}\n+\n+\t/* Round */\n+\ttim_ring->tck_nsec =\n+\t\tround(RTE_ALIGN_MUL_NEAR((long double)rcfg->timer_tick_ns,\n+\t\t\t\t\t cnxk_tim_ns_per_tck(clk_freq)));\n+\n+\ttim_ring->tck_int = round((long double)tim_ring->tck_nsec /\n+\t\t\t\t cnxk_tim_ns_per_tck(clk_freq));\n+\ttim_ring->tck_nsec =\n+\t\tceil(tim_ring->tck_int * cnxk_tim_ns_per_tck(clk_freq));\n+\n \ttim_ring->ring_id = adptr->data->id;\n-\ttim_ring->clk_src = (int)rcfg->clk_src;\n-\ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(\n-\t\trcfg->timer_tick_ns,\n-\t\tcnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));\n+\ttim_ring->clk_src = clk_src;\n \ttim_ring->max_tout = rcfg->max_tmo_ns;\n \ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n \ttim_ring->nb_timers = rcfg->nb_timers;\n@@ -201,11 +233,9 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \tif (rc < 0)\n \t\tgoto tim_bkt_free;\n\n-\trc = roc_tim_lf_config(\n-\t\t&dev->tim, tim_ring->ring_id,\n-\t\tcnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,\n-\t\ttim_ring->nb_bkts, tim_ring->chunk_sz,\n-\t\tNSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));\n+\trc = roc_tim_lf_config(&dev->tim, tim_ring->ring_id, clk_src, 0, 0,\n+\t\t\t tim_ring->nb_bkts, tim_ring->chunk_sz,\n+\t\t\t tim_ring->tck_int, tim_ring->tck_nsec, clk_freq);\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to configure timer ring\");\n \t\tgoto tim_chnk_free;\n@@ -300,7 +330,6 @@ cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr)\n \tif (rc < 0)\n \t\treturn rc;\n\n-\ttim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq());\n \ttim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts;\n \ttim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int);\n \ttim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts);\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 2478a5c1df..1fb17f571d 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -98,13 +98,6 @@ struct cnxk_tim_evdev {\n \tstruct cnxk_tim_ctl *ring_ctl_data;\n };\n\n-enum cnxk_tim_clk_src {\n-\tCNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,\n-\tCNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,\n-\tCNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,\n-\tCNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,\n-};\n-\n struct cnxk_tim_bkt {\n \tuint64_t first_chunk;\n \tunion {\n@@ -147,7 +140,7 @@ struct cnxk_tim_ring {\n \tuint64_t max_tout;\n \tuint64_t nb_chunks;\n \tuint64_t chunk_sz;\n-\tenum cnxk_tim_clk_src clk_src;\n+\tenum roc_tim_clk_src clk_src;\n } __rte_cache_aligned;\n\n struct cnxk_tim_ent {\n@@ -167,31 +160,10 @@ cnxk_tim_priv_get(void)\n \treturn mz->addr;\n }\n\n-static inline uint64_t\n-cnxk_tim_min_tmo_ticks(uint64_t freq)\n+static inline long double\n+cnxk_tim_ns_per_tck(uint64_t freq)\n {\n-\tif (roc_model_runtime_is_cn9k())\n-\t\treturn CN9K_TIM_MIN_TMO_TKS;\n-\telse /* CN10K min tick is of 1us */\n-\t\treturn freq / USECPERSEC;\n-}\n-\n-static inline uint64_t\n-cnxk_tim_min_resolution_ns(uint64_t freq)\n-{\n-\treturn NSECPERSEC / freq;\n-}\n-\n-static inline enum roc_tim_clk_src\n-cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)\n-{\n-\tswitch (clk_src) {\n-\tcase RTE_EVENT_TIMER_ADAPTER_CPU_CLK:\n-\t\treturn roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :\n-\t\t\t\t\t\t\t ROC_TIM_CLK_SRC_GTI;\n-\tdefault:\n-\t\treturn ROC_TIM_CLK_SRC_INVALID;\n-\t}\n+\treturn (long double)NSECPERSEC / freq;\n }\n\n #ifdef RTE_ARCH_ARM64\n@@ -226,6 +198,51 @@ cnxk_tim_cntfrq(void)\n }\n #endif\n\n+static inline enum roc_tim_clk_src\n+cnxk_tim_convert_clk_src(enum rte_event_timer_adapter_clk_src clk_src)\n+{\n+\tswitch (clk_src) {\n+\tcase RTE_EVENT_TIMER_ADAPTER_CPU_CLK:\n+\t\treturn ROC_TIM_CLK_SRC_GTI;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK0:\n+\t\treturn ROC_TIM_CLK_SRC_10NS;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK1:\n+\t\treturn ROC_TIM_CLK_SRC_GPIO;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK2:\n+\t\treturn ROC_TIM_CLK_SRC_PTP;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK3:\n+\t\treturn roc_model_constant_is_cn9k() ? ROC_TIM_CLK_SRC_INVALID :\n+\t\t\t\t\t\t ROC_TIM_CLK_SRC_SYNCE;\n+\tdefault:\n+\t\treturn ROC_TIM_CLK_SRC_INVALID;\n+\t}\n+}\n+\n+static inline int\n+cnxk_tim_get_clk_freq(struct cnxk_tim_evdev *dev, enum roc_tim_clk_src clk_src,\n+\t\t uint64_t *freq)\n+{\n+\tif (freq == NULL)\n+\t\treturn -EINVAL;\n+\n+\tPLT_SET_USED(dev);\n+\tswitch (clk_src) {\n+\tcase ROC_TIM_CLK_SRC_GTI:\n+\t\t*freq = cnxk_tim_cntfrq();\n+\t\tbreak;\n+\tcase ROC_TIM_CLK_SRC_10NS:\n+\t\t*freq = 1E8;\n+\t\tbreak;\n+\tcase ROC_TIM_CLK_SRC_GPIO:\n+\tcase ROC_TIM_CLK_SRC_PTP:\n+\tcase ROC_TIM_CLK_SRC_SYNCE:\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n #define TIM_ARM_FASTPATH_MODES \\\n \tFP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \\\n \tFP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \\\n", "prefixes": [ "v5", "1/2" ] }