From patchwork Mon Dec 13 11:13:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 105107 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A670FA0032; Mon, 13 Dec 2021 12:13:57 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 247D7406A2; Mon, 13 Dec 2021 12:13:57 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7E71940042 for ; Mon, 13 Dec 2021 12:13:56 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BD7ivsC027548; Mon, 13 Dec 2021 03:13:53 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=cl9u1nlvNP7SLsP6UvPP76VQSLVEwuCh1ioMQ3xJvFM=; b=Spq45e6ZxpzaaLNjARLfbnMn76GpsW1gxIvapgSuohq3K7i8/XMR3iWPI/GO1sTnH4z1 2ztpPSiXcNGBTy+jP5NhMd4WYhCITWqYhE+NiQn/xKrJG4zl0LZMF04aKDsAjIMLMZ0x v4MLnj0SIOrGhjnAsZPfDdPTd5GeuXy6uRJbeAGKW/hhQveExYLGDicgkL5wedOx+y73 giJSenv7pKj8qJcAAwhiALVGS4NKGoQrPyLygA7zd/7YelAU50CMlCDf4yJnaBdogx48 /KHudVxy3r0Y+Lalb2B+CE58LZoFbdk7jh9pWrOufk4oEuxyXexJU0ynmxtCIzMJYnJf Vg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cx21kgp28-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Dec 2021 03:13:53 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Dec 2021 03:13:51 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 13 Dec 2021 03:13:51 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id D16B43F7068; Mon, 13 Dec 2021 03:13:48 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , "Pavan Nikhilesh" , Shijith Thotton CC: Subject: [PATCH v5 1/2] event/cnxk: update min interval calculation Date: Mon, 13 Dec 2021 16:43:43 +0530 Message-ID: <20211213111345.5046-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211009080426.18482-1-pbhagavatula@marvell.com> References: <20211009080426.18482-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -8ngeY_fbDhq4j5p_o5roMYx_7DZ-Hqx X-Proofpoint-ORIG-GUID: -8ngeY_fbDhq4j5p_o5roMYx_7DZ-Hqx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_04,2021-12-13_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Minimum supported interval should now be retrieved from mailbox based on the clock source and clock frequency. Signed-off-by: Pavan Nikhilesh Acked-by: Ray Kinsella --- v5: - Rebase on master. v4: - Rebase on master, fix NULL checks. v3: - Add new mbox interface. v2: - Fixed devargs parsing and rebased. drivers/common/cnxk/roc_tim.c | 32 +++++++++++- drivers/common/cnxk/roc_tim.h | 9 +++- drivers/common/cnxk/version.map | 1 + drivers/event/cnxk/cnxk_tim_evdev.c | 69 +++++++++++++++++------- drivers/event/cnxk/cnxk_tim_evdev.h | 81 +++++++++++++++++------------ 5 files changed, 138 insertions(+), 54 deletions(-) -- 2.17.1 diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c index 534b697bee..cefd9bc89d 100644 --- a/drivers/common/cnxk/roc_tim.c +++ b/drivers/common/cnxk/roc_tim.c @@ -145,7 +145,7 @@ int roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, enum roc_tim_clk_src clk_src, uint8_t ena_periodic, uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz, - uint32_t interval) + uint32_t interval, uint64_t intervalns, uint64_t clockfreq) { struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev; struct tim_config_req *req; @@ -162,6 +162,8 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, req->enableperiodic = ena_periodic; req->enabledontfreebuffer = ena_dfb; req->interval = interval; + req->intervalns = intervalns; + req->clockfreq = clockfreq; req->gpioedge = TIM_GPIO_LTOH_TRANS; rc = mbox_process(dev->mbox); @@ -173,6 +175,34 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, return 0; } +int +roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src, + uint64_t clockfreq, uint64_t *intervalns, + uint64_t *interval) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev; + struct tim_intvl_req *req; + struct tim_intvl_rsp *rsp; + int rc = -ENOSPC; + + req = mbox_alloc_msg_tim_get_min_intvl(dev->mbox); + if (req == NULL) + return rc; + + req->clockfreq = clockfreq; + req->clocksource = clk_src; + rc = mbox_process_msg(dev->mbox, (void **)&rsp); + if (rc < 0) { + tim_err_desc(rc); + return rc; + } + + *intervalns = rsp->intvl_ns; + *interval = rsp->intvl_cyc; + + return 0; +} + int roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk) { diff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h index 159b021a31..392732eae2 100644 --- a/drivers/common/cnxk/roc_tim.h +++ b/drivers/common/cnxk/roc_tim.h @@ -10,6 +10,8 @@ enum roc_tim_clk_src { ROC_TIM_CLK_SRC_GPIO, ROC_TIM_CLK_SRC_GTI, ROC_TIM_CLK_SRC_PTP, + ROC_TIM_CLK_SRC_SYNCE, + ROC_TIM_CLK_SRC_BTS, ROC_TIM_CLK_SRC_INVALID, }; @@ -33,7 +35,12 @@ int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, enum roc_tim_clk_src clk_src, uint8_t ena_periodic, uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz, - uint32_t interval); + uint32_t interval, uint64_t intervalns, + uint64_t clockfreq); +int __roc_api roc_tim_lf_interval(struct roc_tim *roc_tim, + enum roc_tim_clk_src clk_src, + uint64_t clockfreq, uint64_t *intervalns, + uint64_t *interval); int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk); int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 07c6720f0c..5379ed2d39 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -346,6 +346,7 @@ INTERNAL { roc_tim_lf_disable; roc_tim_lf_enable; roc_tim_lf_free; + roc_tim_lf_interval; roc_se_ctx_swap; local: *; diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 99b3acee7c..becab1d1b1 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -2,6 +2,8 @@ * Copyright(C) 2021 Marvell. */ +#include + #include "cnxk_eventdev.h" #include "cnxk_tim_evdev.h" @@ -120,7 +122,10 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) { struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + uint64_t min_intvl_ns, min_intvl_cyc; struct cnxk_tim_ring *tim_ring; + enum roc_tim_clk_src clk_src; + uint64_t clk_freq = 0; int i, rc; if (dev == NULL) @@ -139,25 +144,52 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) goto tim_ring_free; } - if (NSEC2TICK(RTE_ALIGN_MUL_CEIL( - rcfg->timer_tick_ns, - cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())), - cnxk_tim_cntfrq()) < - cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) { - if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) - rcfg->timer_tick_ns = TICK2NSEC( - cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()), - cnxk_tim_cntfrq()); - else { + clk_src = cnxk_tim_convert_clk_src(rcfg->clk_src); + if (clk_src == ROC_TIM_CLK_SRC_INVALID) { + plt_err("Invalid clock source"); + goto tim_hw_free; + } + + rc = cnxk_tim_get_clk_freq(dev, clk_src, &clk_freq); + if (rc < 0) { + plt_err("Failed to get clock frequency"); + goto tim_hw_free; + } + + rc = roc_tim_lf_interval(&dev->tim, clk_src, clk_freq, &min_intvl_ns, + &min_intvl_cyc); + if (rc < 0) { + plt_err("Failed to get min interval details"); + goto tim_hw_free; + } + + if (rcfg->timer_tick_ns < min_intvl_ns) { + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) { + rcfg->timer_tick_ns = min_intvl_ns; + } else { rc = -ERANGE; goto tim_hw_free; } } + + if (rcfg->timer_tick_ns > rcfg->max_tmo_ns) { + plt_err("Max timeout to too high"); + rc = -ERANGE; + goto tim_hw_free; + } + + /* Round */ + tim_ring->tck_nsec = + round(RTE_ALIGN_MUL_NEAR((long double)rcfg->timer_tick_ns, + cnxk_tim_ns_per_tck(clk_freq))); + + tim_ring->tck_int = round((long double)tim_ring->tck_nsec / + cnxk_tim_ns_per_tck(clk_freq)); + tim_ring->tck_nsec = + ceil(tim_ring->tck_int * cnxk_tim_ns_per_tck(clk_freq)); + tim_ring->ring_id = adptr->data->id; - tim_ring->clk_src = (int)rcfg->clk_src; - tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL( - rcfg->timer_tick_ns, - cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())); + tim_ring->clk_src = clk_src; tim_ring->max_tout = rcfg->max_tmo_ns; tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); tim_ring->nb_timers = rcfg->nb_timers; @@ -201,11 +233,9 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) if (rc < 0) goto tim_bkt_free; - rc = roc_tim_lf_config( - &dev->tim, tim_ring->ring_id, - cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0, - tim_ring->nb_bkts, tim_ring->chunk_sz, - NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq())); + rc = roc_tim_lf_config(&dev->tim, tim_ring->ring_id, clk_src, 0, 0, + tim_ring->nb_bkts, tim_ring->chunk_sz, + tim_ring->tck_int, tim_ring->tck_nsec, clk_freq); if (rc < 0) { plt_err("Failed to configure timer ring"); goto tim_chnk_free; @@ -300,7 +330,6 @@ cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr) if (rc < 0) return rc; - tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()); tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts; tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int); tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 2478a5c1df..1fb17f571d 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -98,13 +98,6 @@ struct cnxk_tim_evdev { struct cnxk_tim_ctl *ring_ctl_data; }; -enum cnxk_tim_clk_src { - CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK, - CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0, - CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1, - CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2, -}; - struct cnxk_tim_bkt { uint64_t first_chunk; union { @@ -147,7 +140,7 @@ struct cnxk_tim_ring { uint64_t max_tout; uint64_t nb_chunks; uint64_t chunk_sz; - enum cnxk_tim_clk_src clk_src; + enum roc_tim_clk_src clk_src; } __rte_cache_aligned; struct cnxk_tim_ent { @@ -167,31 +160,10 @@ cnxk_tim_priv_get(void) return mz->addr; } -static inline uint64_t -cnxk_tim_min_tmo_ticks(uint64_t freq) +static inline long double +cnxk_tim_ns_per_tck(uint64_t freq) { - if (roc_model_runtime_is_cn9k()) - return CN9K_TIM_MIN_TMO_TKS; - else /* CN10K min tick is of 1us */ - return freq / USECPERSEC; -} - -static inline uint64_t -cnxk_tim_min_resolution_ns(uint64_t freq) -{ - return NSECPERSEC / freq; -} - -static inline enum roc_tim_clk_src -cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src) -{ - switch (clk_src) { - case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: - return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS : - ROC_TIM_CLK_SRC_GTI; - default: - return ROC_TIM_CLK_SRC_INVALID; - } + return (long double)NSECPERSEC / freq; } #ifdef RTE_ARCH_ARM64 @@ -226,6 +198,51 @@ cnxk_tim_cntfrq(void) } #endif +static inline enum roc_tim_clk_src +cnxk_tim_convert_clk_src(enum rte_event_timer_adapter_clk_src clk_src) +{ + switch (clk_src) { + case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: + return ROC_TIM_CLK_SRC_GTI; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0: + return ROC_TIM_CLK_SRC_10NS; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1: + return ROC_TIM_CLK_SRC_GPIO; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2: + return ROC_TIM_CLK_SRC_PTP; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK3: + return roc_model_constant_is_cn9k() ? ROC_TIM_CLK_SRC_INVALID : + ROC_TIM_CLK_SRC_SYNCE; + default: + return ROC_TIM_CLK_SRC_INVALID; + } +} + +static inline int +cnxk_tim_get_clk_freq(struct cnxk_tim_evdev *dev, enum roc_tim_clk_src clk_src, + uint64_t *freq) +{ + if (freq == NULL) + return -EINVAL; + + PLT_SET_USED(dev); + switch (clk_src) { + case ROC_TIM_CLK_SRC_GTI: + *freq = cnxk_tim_cntfrq(); + break; + case ROC_TIM_CLK_SRC_10NS: + *freq = 1E8; + break; + case ROC_TIM_CLK_SRC_GPIO: + case ROC_TIM_CLK_SRC_PTP: + case ROC_TIM_CLK_SRC_SYNCE: + default: + return -EINVAL; + } + + return 0; +} + #define TIM_ARM_FASTPATH_MODES \ FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \