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GET /api/patches/103401/?format=api
{ "id": 103401, "url": "http://patches.dpdk.org/api/patches/103401/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211102040556.7840-3-venkatkumar.duvvuru@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211102040556.7840-3-venkatkumar.duvvuru@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211102040556.7840-3-venkatkumar.duvvuru@broadcom.com", "date": "2021-11-02T04:05:38", "name": "[v3,02/20] net/bnxt: add support for multi root capability", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a158a908bfaa624d2a830c1056d1b4f6855c145b", "submitter": { "id": 1635, "url": "http://patches.dpdk.org/api/people/1635/?format=api", "name": "Venkat Duvvuru", "email": "venkatkumar.duvvuru@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211102040556.7840-3-venkatkumar.duvvuru@broadcom.com/mbox/", "series": [ { "id": 20191, "url": "http://patches.dpdk.org/api/series/20191/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20191", "date": "2021-11-02T04:05:36", "name": "fixes and enhancements to Truflow", "version": 3, "mbox": "http://patches.dpdk.org/series/20191/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103401/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103401/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C416DA0C4D;\n\tTue, 2 Nov 2021 05:06:18 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EF8E14111B;\n\tTue, 2 Nov 2021 05:06:08 +0100 (CET)", "from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com\n [192.19.166.228])\n by mails.dpdk.org (Postfix) with ESMTP id 5314941109\n for <dev@dpdk.org>; Tue, 2 Nov 2021 05:06:07 +0100 (CET)", "from S60.dhcp.broadcom.net (unknown [10.123.66.170])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 51D9E7FF6;\n Mon, 1 Nov 2021 21:06:05 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 51D9E7FF6", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1635825966;\n bh=qt+bJGmmQsHcajLn6Bsl9+dhltRHfUiQHo00Lc9CkgQ=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=iqCJz/spOZrLeb8e3EdrNGrVU6sgsy7oHXgQ04nHxmrq+vYCWfcDT41wMAKoZvsgn\n 89daRpfogrH0x1ZyRjDTBfr31OtaZdOgVXAoZL7D9nqprTDQqw88pSVUw9ZAbYOyFh\n qks2ATy9CFSCGDqbt6iQzbAsq6/5yD9uSXc8gjwQ=", "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>", "Date": "Tue, 2 Nov 2021 09:35:38 +0530", "Message-Id": "<20211102040556.7840-3-venkatkumar.duvvuru@broadcom.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211102040556.7840-1-venkatkumar.duvvuru@broadcom.com>", "References": "<20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com>\n <20211102040556.7840-1-venkatkumar.duvvuru@broadcom.com>", "Subject": "[dpdk-dev] [PATCH v3 02/20] net/bnxt: add support for multi root\n capability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\nUpdate driver to read the multi root capability and ignore\npci address check while creating ulp session when multi root\ncapability is enabled in the hardware. DPDK HSI version updated\nfrom 1.10.1.70 to 1.10.2.54.\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Michael Baucom <michael.baucom@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 3 +\n drivers/net/bnxt/bnxt_hwrm.c | 8 +\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 2682 +++++++++++++++++++++---\n drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +-\n 4 files changed, 2407 insertions(+), 296 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 6743cf92b0..e3e38ffa19 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -723,6 +723,9 @@ struct bnxt {\n \tuint16_t\t\tchip_num;\n #define CHIP_NUM_58818\t\t0xd818\n #define BNXT_CHIP_SR2(bp)\t((bp)->chip_num == CHIP_NUM_58818)\n+#define\tBNXT_FLAGS2_MULTIROOT_EN\t\tBIT(4)\n+#define\tBNXT_MULTIROOT_EN(bp)\t\t\t\\\n+\t((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN)\n \n \tuint32_t\t\tfw_cap;\n #define BNXT_FW_CAP_HOT_RESET\t\tBIT(0)\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 181e607d7b..c7041143a3 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -3394,6 +3394,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)\n {\n \tstruct hwrm_func_qcfg_input req = {0};\n \tstruct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\tuint16_t flags;\n \tint rc;\n \n \tif (!BNXT_VF_IS_TRUSTED(bp))\n@@ -3417,6 +3418,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)\n \tbp->parent->fid = rte_le_to_cpu_16(resp->fid);\n \tbp->parent->port_id = rte_le_to_cpu_16(resp->port_id);\n \n+\tflags = rte_le_to_cpu_16(resp->flags);\n+\t/* check for the multi-root support */\n+\tif (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {\n+\t\tbp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;\n+\t\tPMD_DRV_LOG(DEBUG, \"PF enabled with multi root capability\\n\");\n+\t}\n+\n \tHWRM_UNLOCK();\n \n \treturn 0;\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 4d7efb19f4..2a1e6ab97e 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -657,6 +657,8 @@ struct cmd_nums {\n \t#define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)\n \t/* PTP - Query extended PTP configuration. */\n \t#define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)\n+\t/* The command is used to allocate KTLS crypto key contexts. */\n+\t#define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)\n \t/* Experimental */\n \t#define HWRM_SELFTEST_QLIST UINT32_C(0x200)\n \t/* Experimental */\n@@ -1056,8 +1058,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 2\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 44\n-#define HWRM_VERSION_STR \"1.10.2.44\"\n+#define HWRM_VERSION_RSVD 54\n+#define HWRM_VERSION_STR \"1.10.2.54\"\n \n /****************\n * hwrm_ver_get *\n@@ -1357,6 +1359,12 @@ struct hwrm_ver_get_output {\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \\\n \t\tUINT32_C(0x4000)\n+\t/*\n+\t * If set to 1, then firmware supports secure boot.\n+\t * If set to 0, then firmware doesn't support secure boot.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \\\n+\t\tUINT32_C(0x8000)\n \t/*\n \t * This field represents the major version of RoCE firmware.\n \t * A change in major version represents a major release.\n@@ -8283,8 +8291,14 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t/* Fast reset */\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \\\n \t\t(UINT32_C(0x4) << 8)\n+\t/*\n+\t * Reset was a result of a firmware activation. That is, the\n+\t * fw_activation flag was set in a FW_RESET operation.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \\\n+\t\t(UINT32_C(0x5) << 8)\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \\\n-\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET\n+\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION\n \t/*\n \t * Minimum time before driver should attempt access - units 100ms ticks.\n \t * Range 0-65535\n@@ -10244,8 +10258,21 @@ struct hwrm_async_event_cmpl_error_report_base {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * There was a low level error with an NVM write or erase.\n+\t * See nvm_err_type for more details.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \\\n+\t\tUINT32_C(0x3)\n+\t/*\n+\t * This indicates doorbell drop threshold was hit. When this\n+\t * threshold is crossed, it indicates one or more doorbells for\n+\t * the function were dropped by hardware.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \\\n+\t\tUINT32_C(0x4)\n \t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \\\n-\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD\n } __rte_packed;\n \n /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */\n@@ -10386,6 +10413,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal {\n \t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL\n } __rte_packed;\n \n+/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */\n+struct hwrm_async_event_cmpl_error_report_nvm {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * This async notification message is used to inform\n+\t * the driver that an error has occurred which may need\n+\t * the attention of the administrator.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \\\n+\t\tUINT32_C(0x45)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT\n+\t/* Event specific data. */\n+\tuint32_t\tevent_data2;\n+\t/* Indicates the address where error was detected */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \\\n+\t\tUINT32_C(0xffffffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \\\n+\t\t0\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates the type of error being reported. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \\\n+\t\t0\n+\t/*\n+\t * There was a low level error with an NVM operation.\n+\t * See nvm_err_type for more details.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR\n+\t/* The specific type of NVM error */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \\\n+\t\t8\n+\t/*\n+\t * There was a low level error with an NVM write operation.\n+\t * Verification of written data did not match.\n+\t * event_data2 will be the failing address.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \\\n+\t\t(UINT32_C(0x1) << 8)\n+\t/*\n+\t * There was a low level error with an NVM erase operation.\n+\t * All the bits were not erased.\n+\t * event_data2 will be the failing address.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \\\n+\t\t(UINT32_C(0x2) << 8)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE\n+} __rte_packed;\n+\n+/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */\n+struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \\\n+\t\t0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * This async notification message is used to inform\n+\t * the driver that an error has occurred which may need\n+\t * the attention of the administrator.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \\\n+\t\tUINT32_C(0x45)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT\n+\t/* Event specific data. */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \\\n+\t\t1\n+\t/* 8-lsb timestamp (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates the type of error being reported. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \\\n+\t\t0\n+\t/*\n+\t * This indicates doorbell drop threshold was hit. When this\n+\t * threshold is crossed, it indicates one or more doorbells for\n+\t * the function were dropped by hardware.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \\\n+\t\tUINT32_C(0x4)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD\n+} __rte_packed;\n+\n /* metadata_base_msg (size:64b/8B) */\n struct metadata_base_msg {\n \tuint16_t\tmd_type_link;\n@@ -11204,6 +11387,18 @@ struct hwrm_func_vf_cfg_input {\n \t */\n \t#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \\\n \t\tUINT32_C(0x800)\n+\t/*\n+\t * This bit must be '1' for the num_tx_key_ctxs field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * This bit must be '1' for the num_rx_key_ctxs field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \\\n+\t\tUINT32_C(0x2000)\n \t/*\n \t * The maximum transmission unit requested on the function.\n \t * The HWRM should make sure that the mtu of\n@@ -11353,7 +11548,10 @@ struct hwrm_func_vf_cfg_input {\n \tuint16_t\tnum_stat_ctxs;\n \t/* The number of HW ring groups requested for the VF. */\n \tuint16_t\tnum_hw_ring_grps;\n-\tuint8_t\tunused_0[4];\n+\t/* Number of Tx Key Contexts requested. */\n+\tuint16_t\tnum_tx_key_ctxs;\n+\t/* Number of Rx Key Contexts requested. */\n+\tuint16_t\tnum_rx_key_ctxs;\n } __rte_packed;\n \n /* hwrm_func_vf_cfg_output (size:128b/16B) */\n@@ -11423,7 +11621,7 @@ struct hwrm_func_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_qcaps_output (size:704b/88B) */\n+/* hwrm_func_qcaps_output (size:768b/96B) */\n struct hwrm_func_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -11787,7 +11985,13 @@ struct hwrm_func_qcaps_output {\n \t * (max_tx_rings) to the function.\n \t */\n \tuint16_t\tmax_sp_tx_rings;\n-\tuint8_t\tunused_0[2];\n+\t/*\n+\t * The maximum number of MSI-X vectors that may be allocated across\n+\t * all VFs for the function. This is valid only on the PF with SR-IOV\n+\t * enabled. Returns zero if this command is called on a PF with\n+\t * SR-IOV disabled or on a VF.\n+\t */\n+\tuint16_t\tmax_msix_vfs;\n \tuint32_t\tflags_ext;\n \t/*\n \t * If 1, the device can be configured to set the ECN bits in the\n@@ -11965,7 +12169,12 @@ struct hwrm_func_qcaps_output {\n \t * to the primate processor block.\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)\n-\tuint8_t\tunused_1;\n+\t/*\n+\t * Maximum number of Key Contexts supported per HWRM\n+\t * function call for allocating Key Contexts.\n+\t */\n+\tuint16_t\tmax_key_ctxs_alloc;\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -12023,7 +12232,7 @@ struct hwrm_func_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_qcfg_output (size:832b/104B) */\n+/* hwrm_func_qcfg_output (size:896b/112B) */\n struct hwrm_func_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -12614,7 +12823,11 @@ struct hwrm_func_qcfg_output {\n \t * value is used if ring MTU is not specified.\n \t */\n \tuint16_t\thost_mtu;\n-\tuint8_t\tunused_3;\n+\t/* Number of Tx Key Contexts allocated. */\n+\tuint16_t\talloc_tx_key_ctxs;\n+\t/* Number of Rx Key Contexts allocated. */\n+\tuint16_t\talloc_rx_key_ctxs;\n+\tuint8_t\tunused_3[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -12630,7 +12843,7 @@ struct hwrm_func_qcfg_output {\n *****************/\n \n \n-/* hwrm_func_cfg_input (size:832b/104B) */\n+/* hwrm_func_cfg_input (size:896b/112B) */\n struct hwrm_func_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -13076,6 +13289,18 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \\\n \t\tUINT32_C(0x20000000)\n+\t/*\n+\t * This bit must be '1' for the number of Tx Key Contexts\n+\t * field to be configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \\\n+\t\tUINT32_C(0x40000000)\n+\t/*\n+\t * This bit must be '1' for the number of Rx Key Contexts\n+\t * field to be configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \\\n+\t\tUINT32_C(0x80000000)\n \t/*\n \t * This field can be used by the admin PF to configure\n \t * mtu of foster PFs.\n@@ -13527,6 +13752,11 @@ struct hwrm_func_cfg_input {\n \t * ring that is assigned to a function has a valid mtu.\n \t */\n \tuint16_t\thost_mtu;\n+\t/* Number of Tx Key Contexts requested. */\n+\tuint16_t\tnum_tx_key_ctxs;\n+\t/* Number of Rx Key Contexts requested. */\n+\tuint16_t\tnum_rx_key_ctxs;\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_func_cfg_output (size:128b/16B) */\n@@ -14103,6 +14333,13 @@ struct hwrm_func_drv_rgtr_input {\n \t */\n \t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \\\n \t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is 1, the function's driver is indicating the\n+\t * support of handling the NPAR 1.2 feature where the s-tag may be\n+\t * a value other than 0x8100 or 0x88a8.\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \\\n+\t\tUINT32_C(0x200)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the os_type field to be\n@@ -14664,7 +14901,7 @@ struct hwrm_func_resource_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_func_resource_qcaps_output (size:448b/56B) */\n+/* hwrm_func_resource_qcaps_output (size:512b/64B) */\n struct hwrm_func_resource_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -14739,6 +14976,14 @@ struct hwrm_func_resource_qcaps_output {\n \t */\n \t#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \\\n \t\tUINT32_C(0x1)\n+\t/* Minimum guaranteed number of Tx Key Contexts */\n+\tuint16_t\tmin_tx_key_ctxs;\n+\t/* Maximum non-guaranteed number of Tx Key Contexts */\n+\tuint16_t\tmax_tx_key_ctxs;\n+\t/* Minimum guaranteed number of Rx Key Contexts */\n+\tuint16_t\tmin_rx_key_ctxs;\n+\t/* Maximum non-guaranteed number of Rx Key Contexts */\n+\tuint16_t\tmax_rx_key_ctxs;\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -14755,7 +15000,7 @@ struct hwrm_func_resource_qcaps_output {\n *****************************/\n \n \n-/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */\n+/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */\n struct hwrm_func_vf_resource_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -14829,6 +15074,14 @@ struct hwrm_func_vf_resource_cfg_input {\n \t */\n \t#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \\\n \t\tUINT32_C(0x1)\n+\t/* Minimum guaranteed number of Tx Key Contexts */\n+\tuint16_t\tmin_tx_key_ctxs;\n+\t/* Maximum non-guaranteed number of Tx Key Contexts */\n+\tuint16_t\tmax_tx_key_ctxs;\n+\t/* Minimum guaranteed number of Rx Key Contexts */\n+\tuint16_t\tmin_rx_key_ctxs;\n+\t/* Maximum non-guaranteed number of Rx Key Contexts */\n+\tuint16_t\tmax_rx_key_ctxs;\n \tuint8_t\tunused_0[2];\n } __rte_packed;\n \n@@ -14858,7 +15111,11 @@ struct hwrm_func_vf_resource_cfg_output {\n \tuint16_t\treserved_stat_ctx;\n \t/* Reserved number of ring groups */\n \tuint16_t\treserved_hw_ring_grps;\n-\tuint8_t\tunused_0[7];\n+\t/* Actual number of Tx Key Contexts reserved */\n+\tuint16_t\treserved_tx_key_ctxs;\n+\t/* Actual number of Rx Key Contexts reserved */\n+\tuint16_t\treserved_rx_key_ctxs;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -18132,7 +18389,7 @@ struct hwrm_error_recovery_qcfg_output {\n \n /***************************\n * hwrm_func_echo_response *\n- ****************************/\n+ ***************************/\n \n \n /* hwrm_func_echo_response_input (size:192b/24B) */\n@@ -18190,13 +18447,13 @@ struct hwrm_func_echo_response_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_func_vlan_qcfg *\n- ***********************/\n+/**************************\n+ * hwrm_func_ptp_pin_qcfg *\n+ **************************/\n \n \n-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n-struct hwrm_func_vlan_qcfg_input {\n+/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */\n+struct hwrm_func_ptp_pin_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -18225,18 +18482,11 @@ struct hwrm_func_vlan_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tunused_0[8];\n } __rte_packed;\n \n-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n-struct hwrm_func_vlan_qcfg_output {\n+/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */\n+struct hwrm_func_ptp_pin_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -18245,32 +18495,94 @@ struct hwrm_func_vlan_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint64_t\tunused_0;\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n \t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * The number of TSIO pins that are configured on this board\n+\t * Up to 4 pins can be returned in the response.\n \t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n+\tuint8_t\tnum_pins;\n+\t/* Pin state */\n+\tuint8_t\tstate;\n \t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * When this bit is '1', TSIO pin 0 is enabled.\n+\t * When this bit is '0', TSIO pin 0 is disabled.\n \t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\t/* Future use. */\n-\tuint32_t\trsvd3;\n-\tuint8_t\tunused_3[3];\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', TSIO pin 1 is enabled.\n+\t * When this bit is '0', TSIO pin 1 is disabled.\n+\t */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', TSIO pin 2 is enabled.\n+\t * When this bit is '0', TSIO pin 2 is disabled.\n+\t */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', TSIO pin 3 is enabled.\n+\t * When this bit is '0', TSIO pin 3 is disabled.\n+\t */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \\\n+\t\tUINT32_C(0x8)\n+\t/* Type of function for Pin #0. */\n+\tuint8_t\tpin0_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT\n+\t/* Type of function for Pin #1. */\n+\tuint8_t\tpin1_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT\n+\t/* Type of function for Pin #2. */\n+\tuint8_t\tpin2_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT\n+\t/* Type of function for Pin #3. */\n+\tuint8_t\tpin3_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT\n+\tuint8_t\tunused_0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -18281,13 +18593,13 @@ struct hwrm_func_vlan_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**********************\n- * hwrm_func_vlan_cfg *\n- **********************/\n+/*************************\n+ * hwrm_func_ptp_pin_cfg *\n+ *************************/\n \n \n-/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n-struct hwrm_func_vlan_cfg_input {\n+/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */\n+struct hwrm_func_ptp_pin_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -18316,74 +18628,148 @@ struct hwrm_func_vlan_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[2];\n \tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the stag_vid field to be\n+\t * This bit must be '1' for the pin0_state field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the ctag_vid field to be\n+\t * This bit must be '1' for the pin0_usage field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the stag_pcp field to be\n+\t * This bit must be '1' for the pin1_state field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the ctag_pcp field to be\n+\t * This bit must be '1' for the pin1_usage field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the stag_tpid field to be\n+\t * This bit must be '1' for the pin2_state field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the ctag_tpid field to be\n+\t * This bit must be '1' for the pin2_usage field to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * This bit must be '1' for the pin3_state field to be\n+\t * configured.\n \t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * This bit must be '1' for the pin3_usage field to be\n+\t * configured.\n \t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd1;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\tuint8_t\tunused_3[4];\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \\\n+\t\tUINT32_C(0x80)\n+\t/* Enable or disable functionality of Pin #0. */\n+\tuint8_t\tpin0_state;\n+\t/* Disabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)\n+\t/* Enabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED\n+\t/* Configure function for TSIO pin#0. */\n+\tuint8_t\tpin0_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT\n+\t/* Enable or disable functionality of Pin #1. */\n+\tuint8_t\tpin1_state;\n+\t/* Disabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)\n+\t/* Enabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED\n+\t/* Configure function for TSIO pin#1. */\n+\tuint8_t\tpin1_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT\n+\t/* Enable or disable functionality of Pin #2. */\n+\tuint8_t\tpin2_state;\n+\t/* Disabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)\n+\t/* Enabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED\n+\t/* Configure function for TSIO pin#2. */\n+\tuint8_t\tpin2_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT\n+\t/* Enable or disable functionality of Pin #3. */\n+\tuint8_t\tpin3_state;\n+\t/* Disabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)\n+\t/* Enabled */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED\n+\t/* Configure function for TSIO pin#3. */\n+\tuint8_t\tpin3_usage;\n+\t/* No function is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)\n+\t/* PPS IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)\n+\t/* PPS OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)\n+\t/* SYNC IN is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)\n+\t/* SYNC OUT is configured. */\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)\n+\t#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \\\n+\t\tHWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n-/* hwrm_func_vlan_cfg_output (size:128b/16B) */\n-struct hwrm_func_vlan_cfg_output {\n+/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */\n+struct hwrm_func_ptp_pin_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -18403,13 +18789,812 @@ struct hwrm_func_vlan_cfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*******************************\n- * hwrm_func_vf_vnic_ids_query *\n- *******************************/\n+/*********************\n+ * hwrm_func_ptp_cfg *\n+ *********************/\n \n \n-/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */\n-struct hwrm_func_vf_vnic_ids_query_input {\n+/* hwrm_func_ptp_cfg_input (size:320b/40B) */\n+struct hwrm_func_ptp_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the ptp_pps_event field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the ptp_freq_adj_dll_source field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the ptp_freq_adj_dll_phase field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the ptp_freq_adj_ext_period field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the ptp_freq_adj_ext_up field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the ptp_freq_adj_ext_phase field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \\\n+\t\tUINT32_C(0x20)\n+\t/* This field is used to enable interrupt for a specific PPS event. */\n+\tuint8_t\tptp_pps_event;\n+\t/*\n+\t * When this bit is set to '1', interrupt is enabled for internal\n+\t * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does\n+\t * not configure PPS_OUT on a TSIO pin, then firmware will allocate\n+\t * PPS_OUT to an unallocated pin.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to '1', interrupt is enabled for external\n+\t * PPS event. Latches timestamp on PPS_IN TSIO pin.\n+\t */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This field is used to set the source signal used to discipline\n+\t * PHC (PTP Hardware Clock)\n+\t */\n+\tuint8_t\tptp_freq_adj_dll_source;\n+\t/* No source is selected. Use servo to discipline PHC */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/* TSIO Pin #0 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \\\n+\t\tUINT32_C(0x1)\n+\t/* TSIO Pin #1 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \\\n+\t\tUINT32_C(0x2)\n+\t/* TSIO Pin #2 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \\\n+\t\tUINT32_C(0x3)\n+\t/* TSIO Pin #3 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \\\n+\t\tUINT32_C(0x4)\n+\t/* Port #0 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \\\n+\t\tUINT32_C(0x5)\n+\t/* Port #1 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \\\n+\t\tUINT32_C(0x6)\n+\t/* Port #2 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \\\n+\t\tUINT32_C(0x7)\n+\t/* Port #3 is selected as source signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \\\n+\t\tUINT32_C(0x8)\n+\t/* Invalid signal. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \\\n+\t\tHWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID\n+\t/*\n+\t * This field is used to provide phase adjustment for DLL\n+\t * used to discipline PHC (PTP Hardware clock)\n+\t */\n+\tuint8_t\tptp_freq_adj_dll_phase;\n+\t/* No Phase adjustment. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/* 4Khz sync in frequency. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \\\n+\t\tUINT32_C(0x1)\n+\t/* 8Khz sync in frequency. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \\\n+\t\tUINT32_C(0x2)\n+\t/* 10Mhz sync in frequency. */\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \\\n+\t\tHWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * Period in nanoseconds (ns) for external signal\n+\t * input.\n+\t */\n+\tuint32_t\tptp_freq_adj_ext_period;\n+\t/*\n+\t * Up time in nanoseconds (ns) of the duty cycle\n+\t * of the external signal. This value should be\n+\t * less than ptp_freq_adj_ext_period.\n+\t */\n+\tuint32_t\tptp_freq_adj_ext_up;\n+\t/*\n+\t * Phase value is provided. This field provides the\n+\t * least significant 32 bits of the phase input. The\n+\t * most significant 16 bits come from\n+\t * ptp_freq_adj_ext_phase_upper field. Setting this\n+\t * field requires setting ptp_freq_adj_ext_period\n+\t * field as well to identify the external signal\n+\t * pin.\n+\t */\n+\tuint32_t\tptp_freq_adj_ext_phase_lower;\n+\t/*\n+\t * Phase value is provided. The lower 16 bits of this field is used\n+\t * with the 32 bit value from ptp_freq_adj_ext_phase_lower\n+\t * to provide a 48 bit value input for Phase.\n+\t */\n+\tuint32_t\tptp_freq_adj_ext_phase_upper;\n+} __rte_packed;\n+\n+/* hwrm_func_ptp_cfg_output (size:128b/16B) */\n+struct hwrm_func_ptp_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_func_ptp_ts_query *\n+ **************************/\n+\n+\n+/* hwrm_func_ptp_ts_query_input (size:192b/24B) */\n+struct hwrm_func_ptp_ts_query_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* If set, the response includes PPS event timestamps */\n+\t#define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)\n+\t/* If set, the response includes PTM timestamps */\n+\t#define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)\n+\tuint8_t\tunused_0[4];\n+} __rte_packed;\n+\n+/* hwrm_func_ptp_ts_query_output (size:320b/40B) */\n+struct hwrm_func_ptp_ts_query_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Timestamp value of last PPS event latched. */\n+\tuint64_t\tpps_event_ts;\n+\t/* PTM local timestamp value. */\n+\tuint64_t\tptm_res_local_ts;\n+\t/* PTM Master timestamp value. */\n+\tuint64_t\tptm_pmstr_ts;\n+\t/* PTM Master propagation delay */\n+\tuint32_t\tptm_mstr_prop_dly;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*************************\n+ * hwrm_func_ptp_ext_cfg *\n+ *************************/\n+\n+\n+/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */\n+struct hwrm_func_ptp_ext_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the phc_master_fid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the phc_sec_fid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the phc_sec_mode field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the failover_timer field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This field is used to configure the Master function. Only this\n+\t * function can modify or condition the PHC. Only driver calls from\n+\t * this function are allowed to adjust frequency of PHC or configure\n+\t * PPS functionality.\n+\t * If driver does not specify this FID, then firmware will auto select\n+\t * the first function that makes the call to modify PHC as the Master.\n+\t */\n+\tuint16_t\tphc_master_fid;\n+\t/*\n+\t * This field is used to configure the secondary function. This\n+\t * function becomes the Master function in case of failover from\n+\t * Master function.\n+\t * If driver does not specify this FID, firmware will auto select\n+\t * the last non-master function to make a call to condition PHC as\n+\t * secondary.\n+\t */\n+\tuint16_t\tphc_sec_fid;\n+\t/*\n+\t * This field is used to configure conditions under which a function\n+\t * can become a secondary function.\n+\t */\n+\tuint8_t\tphc_sec_mode;\n+\t/*\n+\t * Immediately failover to the current secondary function. If there\n+\t * is no secondary function available, failover does not happen.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)\n+\t/*\n+\t * All functions (PF and VF) can be used during auto selection\n+\t * of a secondary function. This is not used in case of admin\n+\t * configured secondary function.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)\n+\t/*\n+\t * Only PF's can be selected as a secondary function during auto\n+\t * selection. This is not used in case of admin configured secondary\n+\t * function.\n+\t */\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)\n+\t#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \\\n+\t\tHWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * This field indicates the failover time is milliseconds. If the\n+\t * timeout expires, firmware will failover PTP configurability from\n+\t * current master to secondary fid.\n+\t * 0 - Failover timer is automatically selected based on the last\n+\t * adjFreq() call. If adjFreq() is not called for 3 * (last interval)\n+\t * the failover kicks in. For example, if last interval between\n+\t * adjFreq() calls was 2 seconds and the next adjFreq() is not made for\n+\t * at least 6 seconds, then secondary takes over as master to condition\n+\t * PHC. Firmware rounds up the failover timer to be a multiple of 250\n+\t * ms. Firmware checks every 250 ms to see if timer expired.\n+\t * 0xFFFFFFFF - If driver specifies this value, then failover never\n+\t * happens. Admin or auto selected Master will always be used for\n+\t * conditioning PHC.\n+\t * X - If driver specifies any other value, this is admin indicated\n+\t * failover timeout. If no adjFreq() call is made within this timeout\n+\t * value, then failover happens. This value should be a multiple of\n+\t * 250 ms. Firmware checks every 250 ms to see if timer expired.\n+\t */\n+\tuint32_t\tfailover_timer;\n+\tuint8_t\tunused_1[4];\n+} __rte_packed;\n+\n+/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */\n+struct hwrm_func_ptp_ext_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_func_ptp_ext_qcfg *\n+ **************************/\n+\n+\n+/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */\n+struct hwrm_func_ptp_ext_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tunused_0[8];\n+} __rte_packed;\n+\n+/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */\n+struct hwrm_func_ptp_ext_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Firmware returns the current PHC master function. This function\n+\t * could either be admin selected or auto selected.\n+\t */\n+\tuint16_t\tphc_master_fid;\n+\t/*\n+\t * Firmware returns the current PHC secondary function. This function\n+\t * could either be admin selected or auto selected.\n+\t */\n+\tuint16_t\tphc_sec_fid;\n+\t/*\n+\t * Firmware returns the last non-master/non-secondary function to\n+\t * make a call to condition PHC.\n+\t */\n+\tuint16_t\tphc_active_fid0;\n+\t/*\n+\t * Firmware returns the second last non-master/non-secondary function\n+\t * to make a call to condition PHC.\n+\t */\n+\tuint16_t\tphc_active_fid1;\n+\t/*\n+\t * Timestamp indicating the last time a failover happened. The master\n+\t * and secondary functions in the failover event is indicated in the\n+\t * next two fields.\n+\t */\n+\tuint32_t\tlast_failover_event;\n+\t/*\n+\t * Last failover happened from this function. This was the master\n+\t * function at the time of failover.\n+\t */\n+\tuint16_t\tfrom_fid;\n+\t/*\n+\t * Last failover happened to this function. This was the secondary\n+\t * function at the time of failover.\n+\t */\n+\tuint16_t\tto_fid;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***************************\n+ * hwrm_func_key_ctx_alloc *\n+ ***************************/\n+\n+\n+/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */\n+struct hwrm_func_key_ctx_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Function ID. */\n+\tuint16_t\tfid;\n+\t/* Number of Key Contexts to be allocated. */\n+\tuint16_t\tnum_key_ctxs;\n+\t/* DMA buffer size in bytes. */\n+\tuint32_t\tdma_bufr_size_bytes;\n+\t/* Key Context type. */\n+\tuint8_t\tkey_ctx_type;\n+\t/* Tx Key Context. */\n+\t#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)\n+\t/* Rx KTLS Context. */\n+\t#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)\n+\t#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \\\n+\t\tHWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX\n+\tuint8_t\tunused_0[7];\n+\t/* Host DMA address to send back KTLS context IDs. */\n+\tuint64_t\thost_dma_addr;\n+} __rte_packed;\n+\n+/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */\n+struct hwrm_func_key_ctx_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Actual number of Key Contexts allocated. */\n+\tuint16_t\tnum_key_ctxs_allocated;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/***********************\n+ * hwrm_func_vlan_qcfg *\n+ ***********************/\n+\n+\n+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n+struct hwrm_func_vlan_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n+struct hwrm_func_vlan_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint64_t\tunused_0;\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n+\t/*\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\t/* Future use. */\n+\tuint32_t\trsvd3;\n+\tuint8_t\tunused_3[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**********************\n+ * hwrm_func_vlan_cfg *\n+ **********************/\n+\n+\n+/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n+struct hwrm_func_vlan_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[2];\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the stag_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the ctag_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the stag_pcp field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the ctag_pcp field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the stag_tpid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the ctag_tpid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n+\t/*\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd1;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\tuint8_t\tunused_3[4];\n+} __rte_packed;\n+\n+/* hwrm_func_vlan_cfg_output (size:128b/16B) */\n+struct hwrm_func_vlan_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*******************************\n+ * hwrm_func_vf_vnic_ids_query *\n+ *******************************/\n+\n+\n+/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */\n+struct hwrm_func_vf_vnic_ids_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19128,7 +20313,7 @@ struct hwrm_func_spd_cfg_input {\n \t\tUINT32_C(0x10)\n \t/*\n \t * Ethertype value used in the encapsulated SPD packet header.\n-\t * The user must choose a value that is not conflicting with\n+\t * The user must chooose a value that is not conflicting with\n \t * publicly defined ethertype values. By default, the ethertype\n \t * value of 0xffff is used if there is no user specified value.\n \t */\n@@ -19387,7 +20572,7 @@ struct hwrm_func_spd_qcfg_output {\n \tuint8_t\tunused_1;\n \t/*\n \t * Ethertype value used in the encapsulated SPD packet header.\n-\t * The user must choose a value that is not conflicting with\n+\t * The user must chooose a value that is not conflicting with\n \t * publicly defined ethertype values. By default, the ethertype\n \t * value of 0xffff is used if there is no user specified value.\n \t */\n@@ -21398,6 +22583,12 @@ struct hwrm_port_mac_cfg_input {\n \t */\n \t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \\\n \t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the ptp_adj_phase field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \\\n+\t\tUINT32_C(0x400)\n \t/* Port ID of port that is to be configured. */\n \tuint16_t\tport_id;\n \t/*\n@@ -21590,7 +22781,12 @@ struct hwrm_port_mac_cfg_input {\n \t * of sync timer updates (measured in parts per billion).\n \t */\n \tint32_t\tptp_freq_adj_ppb;\n-\tuint8_t\tunused_1[4];\n+\t/*\n+\t * This unsigned field specifies the phase offset to be applied\n+\t * to the PHC (PTP Hardware Clock). This field is specified in\n+\t * nanoseconds.\n+\t */\n+\tuint32_t\tptp_adj_phase;\n } __rte_packed;\n \n /* hwrm_port_mac_cfg_output (size:128b/16B) */\n@@ -21991,7 +23187,7 @@ struct hwrm_port_mac_ptp_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __rte_packed;\n \n-/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */\n+/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */\n struct hwrm_port_mac_ptp_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -22024,10 +23220,23 @@ struct hwrm_port_mac_ptp_qcfg_output {\n \t */\n \t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \\\n \t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is set to '1', two specific registers for current\n+\t * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are\n+\t * directly accessible by the host.\n+\t */\n+\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \\\n+\t\tUINT32_C(0x10)\n \tuint8_t\tunused_0[3];\n-\t/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */\n+\t/*\n+\t * Offset of the PTP register for the lower 32 bits of timestamp\n+\t * for RX.\n+\t */\n \tuint32_t\trx_ts_reg_off_lower;\n-\t/* Offset of the PTP register for the upper 32 bits of timestamp for RX. */\n+\t/*\n+\t * Offset of the PTP register for the upper 32 bits of timestamp\n+\t * for RX.\n+\t */\n \tuint32_t\trx_ts_reg_off_upper;\n \t/* Offset of the PTP register for the sequence ID for RX. */\n \tuint32_t\trx_ts_reg_off_seq_id;\n@@ -22045,9 +23254,15 @@ struct hwrm_port_mac_ptp_qcfg_output {\n \tuint32_t\trx_ts_reg_off_fifo_adv;\n \t/* PTP timestamp granularity for RX. */\n \tuint32_t\trx_ts_reg_off_granularity;\n-\t/* Offset of the PTP register for the lower 32 bits of timestamp for TX. */\n+\t/*\n+\t * Offset of the PTP register for the lower 32 bits of timestamp\n+\t * for TX.\n+\t */\n \tuint32_t\ttx_ts_reg_off_lower;\n-\t/* Offset of the PTP register for the upper 32 bits of timestamp for TX. */\n+\t/*\n+\t * Offset of the PTP register for the upper 32 bits of timestamp\n+\t * for TX.\n+\t */\n \tuint32_t\ttx_ts_reg_off_upper;\n \t/* Offset of the PTP register for the sequence ID for TX. */\n \tuint32_t\ttx_ts_reg_off_seq_id;\n@@ -22055,6 +23270,10 @@ struct hwrm_port_mac_ptp_qcfg_output {\n \tuint32_t\ttx_ts_reg_off_fifo;\n \t/* PTP timestamp granularity for TX. */\n \tuint32_t\ttx_ts_reg_off_granularity;\n+\t/* Offset of register to get lower 32 bits of current time. */\n+\tuint32_t\tts_ref_clock_reg_lower;\n+\t/* Offset of register to get upper 32 bits of current time. */\n+\tuint32_t\tts_ref_clock_reg_upper;\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -22578,7 +23797,7 @@ struct tx_port_stats_ext {\n } __rte_packed;\n \n /* Port Rx Statistics extended Format */\n-/* rx_port_stats_ext (size:3648b/456B) */\n+/* rx_port_stats_ext (size:3776b/472B) */\n struct rx_port_stats_ext {\n \t/* Number of times link state changed to down */\n \tuint64_t\tlink_down_events;\n@@ -22697,6 +23916,13 @@ struct rx_port_stats_ext {\n \tuint64_t\trx_discard_packets_cos6;\n \t/* Total number of rx discard packets count on cos queue 7 */\n \tuint64_t\trx_discard_packets_cos7;\n+\t/* Total number of FEC blocks corrected by the FEC function in the PHY */\n+\tuint64_t\trx_fec_corrected_blocks;\n+\t/*\n+\t * Total number of FEC blocks determined to be uncorrectable by the\n+\t * FEC function in the PHY\n+\t */\n+\tuint64_t\trx_fec_uncorrectable_blocks;\n } __rte_packed;\n \n /*\n@@ -25981,6 +27207,309 @@ struct hwrm_port_tx_fir_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/***********************\n+ * hwrm_port_ep_tx_cfg *\n+ ***********************/\n+\n+\n+/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */\n+struct hwrm_port_ep_tx_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tenables;\n+\t/* When this bit is '1', the value in the ep0_min_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)\n+\t/* When this bit is '1', the value in the ep0_max_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)\n+\t/* When this bit is '1', the value in the ep1_min_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)\n+\t/* When this bit is '1', the value in the ep1_max_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)\n+\t/* When this bit is '1', the value in the ep2_min_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)\n+\t/* When this bit is '1', the value in the ep2_max_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)\n+\t/* When this bit is '1', the value in the ep3_min_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)\n+\t/* When this bit is '1', the value in the ep3_max_bw field is valid. */\n+\t#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)\n+\t/* A port index, from 0 to the number of front panel ports, minus 1. */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep0_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep0_max_bw;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep1_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep1_max_bw;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep2_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set of\n+\t * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of\n+\t * the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep2_max_bw;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep3_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep3_max_bw;\n+\tuint8_t\tunused_1[4];\n+} __rte_packed;\n+\n+/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */\n+struct hwrm_port_ep_tx_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */\n+struct hwrm_port_ep_tx_cfg_cmd_err {\n+\t/*\n+\t * command specific error codes for the cmd_err field in\n+\t * hwrm_err_output\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error. */\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* The port ID is invalid */\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \\\n+\t\tUINT32_C(0x1)\n+\t/* One of the PCIe endpoints configured is not active. */\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \\\n+\t\tUINT32_C(0x2)\n+\t/* A minimum bandwidth is out of range. */\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \\\n+\t\tUINT32_C(0x3)\n+\t/*\n+\t * One endpoint's minimum bandwidth is more than its maximum\n+\t * bandwidth.\n+\t */\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \\\n+\t\tUINT32_C(0x4)\n+\t/* The sum of the minimum bandwidths on the port is more than 100%. */\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \\\n+\t\tUINT32_C(0x5)\n+\t#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/************************\n+ * hwrm_port_ep_tx_qcfg *\n+ ************************/\n+\n+\n+/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */\n+struct hwrm_port_ep_tx_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The port whose endpoint rate limits are queried. */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused[7];\n+} __rte_packed;\n+\n+/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */\n+struct hwrm_port_ep_tx_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep0_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep0_max_bw;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep1_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep1_max_bw;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep2_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep2_max_bw;\n+\t/*\n+\t * Specifies a minimum guaranteed bandwidth, as a percentage of the\n+\t * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for\n+\t * the specified port. The range is 0 to 100. A value of 0 indicates no\n+\t * minimum rate. The endpoint's min_bw must be less than or equal to\n+\t * max_bw. The sum of all configured minimum bandwidths for a port must\n+\t * be less than or equal to 100.\n+\t */\n+\tuint8_t\tep3_min_bw;\n+\t/*\n+\t * Specifies the maximum portion of the port's bandwidth that the set\n+\t * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage\n+\t * of the link bandwidth, from 0 to 100. A value of 0 indicates no\n+\t * maximum rate.\n+\t */\n+\tuint8_t\tep3_max_bw;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /***********************\n * hwrm_queue_qportcfg *\n ***********************/\n@@ -26097,6 +27626,13 @@ struct hwrm_queue_qportcfg_output {\n \t */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * If this flag is set to '1', then service_profile will carry\n+\t * either lossy/lossless type and the new service_profile_type\n+\t * field will be used to determine if the queue is for L2/ROCE/CNP.\n+\t */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \\\n+\t\tUINT32_C(0x2)\n \t/*\n \t * Bitmask indicating which queues can be configured by the\n \t * hwrm_queue_pfcenable_cfg command.\n@@ -30204,67 +31740,221 @@ struct hwrm_queue_vlanpri2pri_qcfg_input {\n \t * to configure VLAN priority to user priority mapping on this port.\n \t */\n \tuint8_t\tport_id;\n-\tuint8_t\tunused_0[7];\n-} __rte_packed;\n-\n-/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */\n-struct hwrm_queue_vlanpri2pri_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */\n+struct hwrm_queue_vlanpri2pri_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * User priority assigned to VLAN priority 0. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri0_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 1. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri1_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 2. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri2_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 3. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri3_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 4. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri4_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 5. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri5_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 6. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri6_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 7. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri7_user_pri_id;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************************\n+ * hwrm_queue_vlanpri2pri_cfg *\n+ ******************************/\n+\n+\n+/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */\n+struct hwrm_queue_vlanpri2pri_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the vlanpri0_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the vlanpri1_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the vlanpri2_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the vlanpri3_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the vlanpri4_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the vlanpri5_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the vlanpri6_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the vlanpri7_user_pri_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure VLAN priority to user priority mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * User priority assigned to VLAN priority 0. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 0. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri0_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 1. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 1. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri1_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 2. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 2. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri2_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 3. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 3. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri3_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 4. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 4. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri4_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 5. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 5. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri5_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 6. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 6. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri6_user_pri_id;\n \t/*\n-\t * User priority assigned to VLAN priority 7. A value of 0xff\n-\t * indicates that no user priority is assigned. The default user\n-\t * priority will be used.\n+\t * User priority assigned to VLAN priority 7. This value can only\n+\t * be changed before traffic has started.\n \t */\n \tuint8_t\tvlanpri7_user_pri_id;\n+} __rte_packed;\n+\n+/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */\n+struct hwrm_queue_vlanpri2pri_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -30276,13 +31966,13 @@ struct hwrm_queue_vlanpri2pri_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/******************************\n- * hwrm_queue_vlanpri2pri_cfg *\n- ******************************/\n+/*************************\n+ * hwrm_queue_global_cfg *\n+ *************************/\n \n \n-/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */\n-struct hwrm_queue_vlanpri2pri_cfg_input {\n+/* hwrm_queue_global_cfg_input (size:192b/24B) */\n+struct hwrm_queue_global_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -30311,106 +32001,142 @@ struct hwrm_queue_vlanpri2pri_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the vlanpri0_user_pri_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the vlanpri1_user_pri_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \\\n-\t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the vlanpri2_user_pri_id field to be\n-\t * configured.\n+\t * Configuration mode for rx cos queues, configuring whether they\n+\t * use one shared buffer pool (across ports or PCIe endpoints) or\n+\t * independent per port or per endpoint buffer pools.\n \t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \\\n-\t\tUINT32_C(0x4)\n+\tuint8_t\tmode;\n+\t/* One shared buffer pool to be used by all RX CoS queues */\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)\n \t/*\n-\t * This bit must be '1' for the vlanpri3_user_pri_id field to be\n-\t * configured.\n+\t * Each port or PCIe endpoint to use an independent buffer pool\n+\t * for its RX CoS queues\n \t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \\\n-\t\tUINT32_C(0x8)\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \\\n+\t\tHWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT\n+\tuint8_t\tunused_0;\n+\tuint16_t\tenables;\n+\t/* This bit must be '1' when the mode field is configured. */\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the vlanpri4_user_pri_id field to be\n-\t * configured.\n+\t * This bit must be '1' when the maximum bandwidth for queue group 0\n+\t * (g0_max_bw) is configured.\n \t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \\\n-\t\tUINT32_C(0x10)\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the vlanpri5_user_pri_id field to be\n-\t * configured.\n+\t * This bit must be '1' when the maximum bandwidth for queue group 1\n+\t * (g1_max_bw) is configured.\n \t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \\\n-\t\tUINT32_C(0x20)\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the vlanpri6_user_pri_id field to be\n-\t * configured.\n+\t * This bit must be '1' when the maximum bandwidth for queue group 2\n+\t * (g2_max_bw) is configured.\n \t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \\\n-\t\tUINT32_C(0x40)\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the vlanpri7_user_pri_id field to be\n-\t * configured.\n+\t * This bit must be '1' when the maximum bandwidth for queue group 3\n+\t * (g3_max_bw) is configured.\n \t */\n-\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \\\n-\t\tUINT32_C(0x80)\n+\t#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure VLAN priority to user priority mapping on this port.\n+\t * Specifies the maximum receive rate, as a percentage of total link\n+\t * bandwidth, of the receive traffic through queue group 0. A value\n+\t * of 0 indicates no rate limit.\n+\t *\n+\t * A queue group is a set of queues, one per traffic class. In\n+\t * single-host mode, each panel port has its own queue group, and thus,\n+\t * this rate limit shapes the traffic received on a port, in this case,\n+\t * through port 0. In multi-root or multi-host mode, each PCIe endpoint\n+\t * on the NIC has its own queue group. In these cases, the rate limit\n+\t * shapes the traffic sent to the host through one of the PCIe\n+\t * endpoints, in this case endpoint 0.\n \t */\n-\tuint8_t\tport_id;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tg0_max_bw;\n \t/*\n-\t * User priority assigned to VLAN priority 0. This value can only\n-\t * be changed before traffic has started.\n+\t * Specifies the maximum rate of the traffic through receive CoS queue\n+\t * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of\n+\t * total link bandwidth (the sum of the bandwidths of all links). A\n+\t * value of 0 indicates no rate limit.\n \t */\n-\tuint8_t\tvlanpri0_user_pri_id;\n+\tuint8_t\tg1_max_bw;\n \t/*\n-\t * User priority assigned to VLAN priority 1. This value can only\n-\t * be changed before traffic has started.\n+\t * Specifies the maximum rate of the traffic through receive CoS queue\n+\t * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of\n+\t * total link bandwidth (the sum of the bandwidths of all links). A\n+\t * value of 0 indicates no rate limit.\n \t */\n-\tuint8_t\tvlanpri1_user_pri_id;\n+\tuint8_t\tg2_max_bw;\n \t/*\n-\t * User priority assigned to VLAN priority 2. This value can only\n-\t * be changed before traffic has started.\n+\t * Specifies the maximum receive rate, in Mbps, of the receive traffic\n+\t * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0\n+\t * indicates no rate limit.\n \t */\n-\tuint8_t\tvlanpri2_user_pri_id;\n+\tuint8_t\tg3_max_bw;\n+} __rte_packed;\n+\n+/* hwrm_queue_global_cfg_output (size:128b/16B) */\n+struct hwrm_queue_global_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * User priority assigned to VLAN priority 3. This value can only\n-\t * be changed before traffic has started.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tvlanpri3_user_pri_id;\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_queue_global_qcfg *\n+ **************************/\n+\n+\n+/* hwrm_queue_global_qcfg_input (size:128b/16B) */\n+struct hwrm_queue_global_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * User priority assigned to VLAN priority 4. This value can only\n-\t * be changed before traffic has started.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint8_t\tvlanpri4_user_pri_id;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * User priority assigned to VLAN priority 5. This value can only\n-\t * be changed before traffic has started.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint8_t\tvlanpri5_user_pri_id;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * User priority assigned to VLAN priority 6. This value can only\n-\t * be changed before traffic has started.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint8_t\tvlanpri6_user_pri_id;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * User priority assigned to VLAN priority 7. This value can only\n-\t * be changed before traffic has started.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint8_t\tvlanpri7_user_pri_id;\n+\tuint64_t\tresp_addr;\n } __rte_packed;\n \n-/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */\n-struct hwrm_queue_vlanpri2pri_cfg_output {\n+/* hwrm_queue_global_qcfg_output (size:320b/40B) */\n+struct hwrm_queue_global_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -30419,7 +32145,95 @@ struct hwrm_queue_vlanpri2pri_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* Port or PCIe endpoint id to be mapped for buffer pool 0. */\n+\tuint8_t\tbuffer_pool_id0_map;\n+\t/* Port or PCIe endpoint id to be mapped for buffer pool 1. */\n+\tuint8_t\tbuffer_pool_id1_map;\n+\t/* Port or PCIe endpoint id to be mapped for buffer pool 2. */\n+\tuint8_t\tbuffer_pool_id2_map;\n+\t/* Port or PCIe endpoint id to be mapped for buffer pool 3. */\n+\tuint8_t\tbuffer_pool_id3_map;\n+\t/* Size of buffer pool 0 (KBytes). */\n+\tuint32_t\tbuffer_pool_id0_size;\n+\t/* Size of buffer pool 1 (KBytes). */\n+\tuint32_t\tbuffer_pool_id1_size;\n+\t/* Size of buffer pool 2 (KBytes). */\n+\tuint32_t\tbuffer_pool_id2_size;\n+\t/* Size of buffer pool 3 (KBytes). */\n+\tuint32_t\tbuffer_pool_id3_size;\n+\tuint16_t\tflags;\n+\t/*\n+\t * Enumeration denoting whether the rx buffer pool mapping is\n+\t * per port or per PCIe endpoint\n+\t */\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * The buffer_pool_id[0-3]_map field represents mapping of rx\n+\t * buffer pools to a port.\n+\t */\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * The buffer_pool_id[0-3]_map field represents mapping of rx\n+\t * buffer pools to a PCIe endpoint.\n+\t */\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \\\n+\t\tHWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT\n+\t/*\n+\t * Configuration mode for rx cos queues, configuring whether they\n+\t * use one shared buffer pool (across ports or PCIe endpoints) or\n+\t * independent per port or per endpoint buffer pools.\n+\t */\n+\tuint8_t\tmode;\n+\t/* One shared buffer pool to be used by all RX CoS queues */\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)\n+\t/*\n+\t * Each port or PCIe endpoint to use an independent buffer pool\n+\t * for its RX CoS queues\n+\t */\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)\n+\t#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \\\n+\t\tHWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * Reports the rate limit applied to traffic through receive CoS queue\n+\t * group 0. The rate limit is a percentage of total link bandwidth. A\n+\t * value of 0 indicates no rate limit.\n+\t *\n+\t * A queue group is a set of queues, one per traffic class. In\n+\t * single-host mode, each panel port has its own queue group, and thus,\n+\t * this rate limit shapes the traffic received on a port, in this case,\n+\t * through port 0. In multi-root or multi-host mode, each PCIe endpoint\n+\t * on the NIC has its own queue group. In these cases, the rate limit\n+\t * shapes the traffic sent to the host through one of the PCIe\n+\t * endpoints, in this case endpoint 0.\n+\t */\n+\tuint8_t\tg0_max_bw;\n+\t/*\n+\t * Reports the rate limit applied to traffic through receive CoS queue\n+\t * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a\n+\t * percentage of total link bandwidth. A value of 0 indicates no rate\n+\t * limit.\n+\t */\n+\tuint8_t\tg1_max_bw;\n+\t/*\n+\t * Reports the rate limit applied to traffic through receive CoS queue\n+\t * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a\n+\t * percentage of total link bandwidth. A value of 0 indicates no rate\n+\t * limit.\n+\t */\n+\tuint8_t\tg2_max_bw;\n+\t/*\n+\t * Reports the rate limit applied to traffic through receive CoS queue\n+\t * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a\n+\t * percentage of total link bandwidth. A value of 0 indicates no rate\n+\t * limit.\n+\t */\n+\tuint8_t\tg3_max_bw;\n+\tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -31324,6 +33138,13 @@ struct hwrm_vnic_qcaps_output {\n \t */\n \t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \\\n \t\tUINT32_C(0x1000)\n+\t/*\n+\t * When this bit is set '1', it indicates that firmware returns\n+\t * INVALID_PARAM error, if host drivers choose invalid hash type\n+\t * bit combinations in vnic_rss_cfg.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \\\n+\t\tUINT32_C(0x2000)\n \t/*\n \t * This field advertises the maximum concurrent TPA aggregations\n \t * supported by the VNIC on new devices that support TPA v2.\n@@ -31674,7 +33495,34 @@ struct hwrm_vnic_rss_cfg_input {\n \tuint64_t\thash_key_tbl_addr;\n \t/* Index to the rss indirection table. */\n \tuint16_t\trss_ctx_idx;\n-\tuint8_t\tunused_1[6];\n+\tuint8_t\tflags;\n+\t/*\n+\t * When this bit is '1', it indicates that the hash_type field is\n+\t * interpreted as a change relative the current configuration. Each\n+\t * '1' bit in hash_type represents a header to add to the current\n+\t * hash. Zeroes designate the hash_type state bits that should remain\n+\t * unchanged, if possible. If this constraint on the existing state\n+\t * cannot be satisfied, then the implementation should preference\n+\t * adding other headers so as to honor the request to add the\n+\t * specified headers. It is an error to set this flag concurrently\n+\t * with hash_type_exclude.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates that the hash_type field is\n+\t * interpreted as a change relative the current configuration. Each\n+\t * '1' bit in hash_type represents a header to remove from the\n+\t * current hash. Zeroes designate the hash_type state bits that\n+\t * should remain unchanged, if possible. If this constraint on the\n+\t * existing state cannot be satisfied, then the implementation should\n+\t * preference removing other headers so as to honor the request to\n+\t * remove the specified headers. It is an error to set this flag\n+\t * concurrently with hash_type_include.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \\\n+\t\tUINT32_C(0x2)\n+\tuint8_t\tunused_1[5];\n } __rte_packed;\n \n /* hwrm_vnic_rss_cfg_output (size:128b/16B) */\n@@ -43062,6 +44910,161 @@ struct hwrm_cfa_tflib_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/**********************************\n+ * hwrm_cfa_lag_group_member_rgtr *\n+ **********************************/\n+\n+\n+/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */\n+struct hwrm_cfa_lag_group_member_rgtr_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tmode;\n+\t/*\n+\t * Transmit only on the active port. Automatically failover\n+\t * to backup port.\n+\t */\n+\t#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Transmit based on packet header ntuple hash. Packet with only\n+\t * layer 2 headers will hash using the destination MAC, source MAC\n+\t * and Ethertype fields. Packets with layer 3 (IP) headers will\n+\t * hash using the destination MAC, source MAC, IP protocol/next\n+\t * header, source IP address and destination IP address. Packets\n+\t * with layer 4 (TCP/UDP) headers will hash using the destination\n+\t * MAC, source MAC, IP protocol/next header, source IP address,\n+\t * destination IP address, source port and destination port fields.\n+\t */\n+\t#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \\\n+\t\tUINT32_C(0x2)\n+\t/* Transmit packets on all specified ports. */\n+\t#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \\\n+\t\tHWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST\n+\t/*\n+\t * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,\n+\t * bit2 = port 2, bit3 = port 4, bit4 = loopback port\n+\t */\n+\tuint8_t\tport_bitmap;\n+\t/* Specify the active port when active-backup mode is specified */\n+\tuint8_t\tactive_port;\n+\tuint8_t\tunused_0[5];\n+} __rte_packed;\n+\n+/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */\n+struct hwrm_cfa_lag_group_member_rgtr_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* lag group ID configured for the function */\n+\tuint16_t\tlag_id;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************************\n+ * hwrm_cfa_lag_group_member_unrgtr *\n+ ************************************/\n+\n+\n+/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */\n+struct hwrm_cfa_lag_group_member_unrgtr_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* lag group ID configured for the function */\n+\tuint16_t\tlag_id;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */\n+struct hwrm_cfa_lag_group_member_unrgtr_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /***********\n * hwrm_tf *\n ***********/\n@@ -43263,8 +45266,13 @@ struct hwrm_tf_session_open_output {\n \t * the newly created session.\n \t */\n \tuint32_t\tfw_session_client_id;\n+\t/* This field is used to return the status of fw session to host. */\n \tuint32_t\tflags;\n-\t/* Indicates if the shared session has been created. */\n+\t/*\n+\t * Indicates if the shared session has been created. Shared seesion\n+\t * should be the first session created ever. Its fw_rm_client_id\n+\t * should be 1. The AFM session's fw_rm_client_id is 0.\n+\t */\n \t#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \\\n \t\tUINT32_C(0x1)\n \t/*\n@@ -43745,7 +45753,7 @@ struct hwrm_tf_session_resc_qcaps_input {\n \t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX\n@@ -43860,7 +45868,7 @@ struct hwrm_tf_session_resc_alloc_input {\n \t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX\n@@ -43959,7 +45967,7 @@ struct hwrm_tf_session_resc_free_input {\n \t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX\n@@ -44043,7 +46051,7 @@ struct hwrm_tf_session_resc_flush_input {\n \t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX\n@@ -44248,7 +46256,7 @@ struct hwrm_tf_tbl_type_get_input {\n \t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX\n@@ -44337,7 +46345,7 @@ struct hwrm_tf_tbl_type_set_input {\n \t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX\n@@ -44819,7 +46827,7 @@ struct hwrm_tf_ext_em_qcaps_input {\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \\\n \t\tUINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \\\n \t\tUINT32_C(0x1)\n \t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \\\n@@ -44997,7 +47005,7 @@ struct hwrm_tf_ext_em_op_input {\n \t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX\n@@ -45104,7 +47112,7 @@ struct hwrm_tf_ext_em_cfg_input {\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \\\n \t\tUINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \\\n \t\tUINT32_C(0x1)\n \t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \\\n@@ -45309,7 +47317,7 @@ struct hwrm_tf_ext_em_qcfg_input {\n \t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX\n@@ -45335,7 +47343,7 @@ struct hwrm_tf_ext_em_qcfg_output {\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \\\n \t\tUINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \\\n \t\tUINT32_C(0x1)\n \t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \\\n@@ -45475,7 +47483,7 @@ struct hwrm_tf_em_insert_input {\n \t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX\n@@ -45556,7 +47564,7 @@ struct hwrm_tf_em_hash_insert_input {\n \t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX\n@@ -45637,13 +47645,13 @@ struct hwrm_tf_em_delete_input {\n \t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX\n \t/* Unused0 */\n \tuint16_t\tunused0;\n-\t/* EM internal flow hanndle. */\n+\t/* EM internal flow handle. */\n \tuint64_t\tflow_handle;\n \t/* EM Key value */\n \tuint64_t\tem_key[8];\n@@ -45785,7 +47793,7 @@ struct hwrm_tf_tcam_set_input {\n \t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX\n@@ -45887,7 +47895,7 @@ struct hwrm_tf_tcam_get_input {\n \t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX\n@@ -45983,7 +47991,7 @@ struct hwrm_tf_tcam_move_input {\n \t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX\n@@ -46066,7 +48074,7 @@ struct hwrm_tf_tcam_free_input {\n \t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX\n@@ -46149,7 +48157,7 @@ struct hwrm_tf_global_cfg_set_input {\n \t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX\n@@ -46233,7 +48241,7 @@ struct hwrm_tf_global_cfg_get_input {\n \t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX\n@@ -46308,7 +48316,7 @@ struct hwrm_tf_if_tbl_get_input {\n \t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX\n@@ -46397,7 +48405,7 @@ struct hwrm_tf_if_tbl_set_input {\n \t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX\n@@ -46484,7 +48492,7 @@ struct hwrm_tf_tbl_type_bulk_get_input {\n \t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)\n \t/* If this bit set to 0, then it indicates rx flow. */\n \t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n-\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t/* If this bit is set to 1, then it indicates tx flow. */\n \t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n \t#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX\n@@ -48261,7 +50269,7 @@ struct hwrm_nvm_get_dir_info_output {\n ******************/\n \n \n-/* hwrm_nvm_write_input (size:384b/48B) */\n+/* hwrm_nvm_write_input (size:448b/56B) */\n struct hwrm_nvm_write_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -48296,10 +50304,7 @@ struct hwrm_nvm_write_input {\n \t * This is where the source data is.\n \t */\n \tuint64_t\thost_src_addr;\n-\t/*\n-\t * The Directory Entry Type (valid values are defined in the\n-\t * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).\n-\t */\n+\t/* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */\n \tuint16_t\tdir_type;\n \t/*\n \t * Directory ordinal.\n@@ -48311,10 +50316,8 @@ struct hwrm_nvm_write_input {\n \t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */\n \tuint16_t\tdir_attr;\n \t/*\n-\t * Length of data to write, in bytes.May be\n-\t * less than or equal to the allocated size for the directory entry.\n-\t * The data length stored in the directory entry will be updated to\n-\t * reflect this value once the write is complete.\n+\t * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.\n+\t * The data length stored in the directory entry will be updated to reflect this value once the write is complete.\n \t */\n \tuint32_t\tdir_data_length;\n \t/* Option. */\n@@ -48327,17 +50330,41 @@ struct hwrm_nvm_write_input {\n \t#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * The requested length of the allocated NVM for the item, in bytes.\n-\t * This value may be greater than or equal to the specified data length (dir_data_length).\n+\t * This flag indicates the sender wants to modify a continuous\n+\t * NVRAM area using a batch of this HWRM requests. The\n+\t * offset of a request must be continuous to the end of previous\n+\t * request's. Firmware does not update the directory entry until\n+\t * receiving the last request, which is indicated by the batch_last\n+\t * flag. This flag is set usually when a sender does not have a\n+\t * block of memory that is big enough to hold the entire NVRAM\n+\t * data for send at one time.\n+\t */\n+\t#define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This flag can be used only when the batch_mode flag is set. It\n+\t * indicates this request is the last of batch requests.\n+\t */\n+\t#define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).\n \t * If this value is less than the specified data length, it will be ignored.\n-\t * The response will contain the actual allocated item length, which may\n-\t * be greater than the requested item length.\n-\t * The purpose for allocating more than the required number of bytes for\n-\t * an item's data is to pre-allocate extra storage (padding) to accommodate\n-\t * the potential future growth of an item (e.g. upgraded firmware with\n-\t * a size increase, log growth, expanded configuration data).\n+\t * The response will contain the actual allocated item length, which may be greater than the requested item length.\n+\t * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate\n+\t * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).\n \t */\n \tuint32_t\tdir_item_length;\n+\t/*\n+\t * 32-bit offset of data blob from where data is being written.\n+\t * Only valid for batch mode. For non-batch writes 'dont care'.\n+\t */\n+\tuint32_t\toffset;\n+\t/*\n+\t * Length of data to be written.Should be non-zero.\n+\t * Only valid for batch mode. For non-batch writes 'dont care'.\n+\t */\n+\tuint32_t\tlen;\n \tuint32_t\tunused_0;\n } __rte_packed;\n \n@@ -48352,10 +50379,8 @@ struct hwrm_nvm_write_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * Length of the allocated NVM for the item, in bytes. The value may be\n-\t * greater than or equal to the specified data length or the requested item length.\n-\t * The actual item length used when creating a new directory entry will\n-\t * be a multiple of an NVM block size.\n+\t * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.\n+\t * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.\n \t */\n \tuint32_t\tdir_item_length;\n \t/* The directory index of the created or modified item. */\n@@ -48699,10 +50724,7 @@ struct hwrm_nvm_get_dev_info_output {\n \t/* Total size, in bytes of the NVRAM device. */\n \tuint32_t\tnvram_size;\n \tuint32_t\treserved_size;\n-\t/*\n-\t * Available size that can be used, in bytes. Available size is the\n-\t * NVRAM size take away the used size and reserved size.\n-\t */\n+\t/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */\n \tuint32_t\tavailable_size;\n \t/* This field represents the major version of NVM cfg */\n \tuint8_t\tnvm_cfg_ver_maj;\n@@ -48844,10 +50866,7 @@ struct hwrm_nvm_mod_dir_entry_input {\n \t * The (0-based) instance of this Directory Type.\n \t */\n \tuint16_t\tdir_ordinal;\n-\t/*\n-\t * The Directory Entry Extension flags (see BNX_DIR_EXT_* for\n-\t * extension flag definitions).\n-\t */\n+\t/* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */\n \tuint16_t\tdir_ext;\n \t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */\n \tuint16_t\tdir_attr;\n@@ -49016,10 +51035,8 @@ struct hwrm_nvm_install_update_input {\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, then unspecified images, images not in the package file,\n-\t * will be safely deleted.\n-\t * When combined with erase_unused_space then unspecified images will be\n-\t * securely erased.\n+\t * If set to 1, then unspecified images, images not in the package file, will be safely deleted.\n+\t * When combined with erase_unused_space then unspecified images will be securely erased.\n \t */\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \\\n \t\tUINT32_C(0x2)\n@@ -49116,13 +51133,19 @@ struct hwrm_nvm_install_update_cmd_err {\n \t */\n \tuint8_t\tcode;\n \t/* Unknown error */\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n \t/* Unable to complete operation due to fragmentation */\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \\\n+\t\tUINT32_C(0x1)\n \t/* nvm is completely full. */\n-\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \\\n+\t\tUINT32_C(0x2)\n+\t/* Firmware update failed due to Anti-rollback. */\n+\t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \\\n+\t\tUINT32_C(0x3)\n \t#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE\n+\t\tHWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK\n \tuint8_t\tunused_0[7];\n } __rte_packed;\n \n@@ -49404,10 +51427,7 @@ struct hwrm_nvm_set_variable_input {\n \t/* index for the 4th dimensions */\n \tuint16_t\tindex_3;\n \tuint8_t\tflags;\n-\t/*\n-\t * When this bit is 1, flush internal cache after this write operation\n-\t * (see hwrm_nvm_flush command.)\n-\t */\n+\t/* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */\n \t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \\\n \t\tUINT32_C(0x1)\n \t/* encryption method */\n@@ -49589,6 +51609,84 @@ struct hwrm_nvm_validate_option_cmd_err {\n \tuint8_t\tunused_0[7];\n } __rte_packed;\n \n+/*******************\n+ * hwrm_nvm_defrag *\n+ *******************/\n+\n+\n+/* hwrm_nvm_defrag_input (size:192b/24B) */\n+struct hwrm_nvm_defrag_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* This bit must be '1' to perform NVM defragmentation. */\n+\t#define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)\n+\tuint8_t\tunused_0[4];\n+} __rte_packed;\n+\n+/* hwrm_nvm_defrag_output (size:128b/16B) */\n+struct hwrm_nvm_defrag_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */\n+struct hwrm_nvm_defrag_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* NVM defragmentation could not be performed */\n+\t#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)\n+\t#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n /****************\n * hwrm_oem_cmd *\n ****************/\ndiff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\nindex bd57229968..dbc8a3c5bb 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\n@@ -1010,13 +1010,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init)\n * pointer, otherwise allocate a new session.\n */\n static struct bnxt_ulp_session_state *\n-ulp_get_session(struct rte_pci_addr *pci_addr)\n+ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr)\n {\n \tstruct bnxt_ulp_session_state *session;\n \n+\t/* if multi root capability is enabled, then ignore the pci bus id */\n \tSTAILQ_FOREACH(session, &bnxt_ulp_session_list, next) {\n \t\tif (session->pci_info.domain == pci_addr->domain &&\n-\t\t session->pci_info.bus == pci_addr->bus) {\n+\t\t (BNXT_MULTIROOT_EN(bp) ||\n+\t\t session->pci_info.bus == pci_addr->bus)) {\n \t\t\treturn session;\n \t\t}\n \t}\n@@ -1044,7 +1046,7 @@ ulp_session_init(struct bnxt *bp,\n \n \tpthread_mutex_lock(&bnxt_ulp_global_mutex);\n \n-\tsession = ulp_get_session(pci_addr);\n+\tsession = ulp_get_session(bp, pci_addr);\n \tif (!session) {\n \t\t/* Not Found the session Allocate a new one */\n \t\tsession = rte_zmalloc(\"bnxt_ulp_session\",\n@@ -1547,7 +1549,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp)\n \tpci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device);\n \tpci_addr = &pci_dev->addr;\n \tpthread_mutex_lock(&bnxt_ulp_global_mutex);\n-\tsession = ulp_get_session(pci_addr);\n+\tsession = ulp_get_session(bp, pci_addr);\n \tpthread_mutex_unlock(&bnxt_ulp_global_mutex);\n \n \t/* session not found then just exit */\n", "prefixes": [ "v3", "02/20" ] }