@@ -723,6 +723,9 @@ struct bnxt {
uint16_t chip_num;
#define CHIP_NUM_58818 0xd818
#define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818)
+#define BNXT_FLAGS2_MULTIROOT_EN BIT(4)
+#define BNXT_MULTIROOT_EN(bp) \
+ ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN)
uint32_t fw_cap;
#define BNXT_FW_CAP_HOT_RESET BIT(0)
@@ -3394,6 +3394,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
{
struct hwrm_func_qcfg_input req = {0};
struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
+ uint16_t flags;
int rc;
if (!BNXT_VF_IS_TRUSTED(bp))
@@ -3417,6 +3418,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
bp->parent->fid = rte_le_to_cpu_16(resp->fid);
bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
+ flags = rte_le_to_cpu_16(resp->flags);
+ /* check for the multi-root support */
+ if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
+ bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
+ PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
+ }
+
HWRM_UNLOCK();
return 0;
@@ -657,6 +657,8 @@ struct cmd_nums {
#define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
/* PTP - Query extended PTP configuration. */
#define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
+ /* The command is used to allocate KTLS crypto key contexts. */
+ #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
@@ -1056,8 +1058,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 2
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 44
-#define HWRM_VERSION_STR "1.10.2.44"
+#define HWRM_VERSION_RSVD 54
+#define HWRM_VERSION_STR "1.10.2.54"
/****************
* hwrm_ver_get *
@@ -1357,6 +1359,12 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
UINT32_C(0x4000)
+ /*
+ * If set to 1, then firmware supports secure boot.
+ * If set to 0, then firmware doesn't support secure boot.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \
+ UINT32_C(0x8000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -8283,8 +8291,14 @@ struct hwrm_async_event_cmpl_reset_notify {
/* Fast reset */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
(UINT32_C(0x4) << 8)
+ /*
+ * Reset was a result of a firmware activation. That is, the
+ * fw_activation flag was set in a FW_RESET operation.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \
+ (UINT32_C(0x5) << 8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
- HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET
+ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
/*
* Minimum time before driver should attempt access - units 100ms ticks.
* Range 0-65535
@@ -10244,8 +10258,21 @@ struct hwrm_async_event_cmpl_error_report_base {
*/
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
UINT32_C(0x2)
+ /*
+ * There was a low level error with an NVM write or erase.
+ * See nvm_err_type for more details.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \
+ UINT32_C(0x3)
+ /*
+ * This indicates doorbell drop threshold was hit. When this
+ * threshold is crossed, it indicates one or more doorbells for
+ * the function were dropped by hardware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
+ UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \
- HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
} __rte_packed;
/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
@@ -10386,6 +10413,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal {
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
} __rte_packed;
+/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_nvm {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ /* Indicates the address where error was detected */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \
+ UINT32_C(0xffffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \
+ 0
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /*
+ * There was a low level error with an NVM operation.
+ * See nvm_err_type for more details.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \
+ UINT32_C(0x3)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
+ /* The specific type of NVM error */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \
+ 8
+ /*
+ * There was a low level error with an NVM write operation.
+ * Verification of written data did not match.
+ * event_data2 will be the failing address.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \
+ (UINT32_C(0x1) << 8)
+ /*
+ * There was a low level error with an NVM erase operation.
+ * All the bits were not erased.
+ * event_data2 will be the failing address.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \
+ (UINT32_C(0x2) << 8)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \
+ 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /*
+ * This indicates doorbell drop threshold was hit. When this
+ * threshold is crossed, it indicates one or more doorbells for
+ * the function were dropped by hardware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
+ UINT32_C(0x4)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
+} __rte_packed;
+
/* metadata_base_msg (size:64b/8B) */
struct metadata_base_msg {
uint16_t md_type_link;
@@ -11204,6 +11387,18 @@ struct hwrm_func_vf_cfg_input {
*/
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the num_tx_key_ctxs field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the num_rx_key_ctxs field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \
+ UINT32_C(0x2000)
/*
* The maximum transmission unit requested on the function.
* The HWRM should make sure that the mtu of
@@ -11353,7 +11548,10 @@ struct hwrm_func_vf_cfg_input {
uint16_t num_stat_ctxs;
/* The number of HW ring groups requested for the VF. */
uint16_t num_hw_ring_grps;
- uint8_t unused_0[4];
+ /* Number of Tx Key Contexts requested. */
+ uint16_t num_tx_key_ctxs;
+ /* Number of Rx Key Contexts requested. */
+ uint16_t num_rx_key_ctxs;
} __rte_packed;
/* hwrm_func_vf_cfg_output (size:128b/16B) */
@@ -11423,7 +11621,7 @@ struct hwrm_func_qcaps_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcaps_output (size:704b/88B) */
+/* hwrm_func_qcaps_output (size:768b/96B) */
struct hwrm_func_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -11787,7 +11985,13 @@ struct hwrm_func_qcaps_output {
* (max_tx_rings) to the function.
*/
uint16_t max_sp_tx_rings;
- uint8_t unused_0[2];
+ /*
+ * The maximum number of MSI-X vectors that may be allocated across
+ * all VFs for the function. This is valid only on the PF with SR-IOV
+ * enabled. Returns zero if this command is called on a PF with
+ * SR-IOV disabled or on a VF.
+ */
+ uint16_t max_msix_vfs;
uint32_t flags_ext;
/*
* If 1, the device can be configured to set the ECN bits in the
@@ -11965,7 +12169,12 @@ struct hwrm_func_qcaps_output {
* to the primate processor block.
*/
#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
- uint8_t unused_1;
+ /*
+ * Maximum number of Key Contexts supported per HWRM
+ * function call for allocating Key Contexts.
+ */
+ uint16_t max_key_ctxs_alloc;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -12023,7 +12232,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcfg_output (size:832b/104B) */
+/* hwrm_func_qcfg_output (size:896b/112B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -12614,7 +12823,11 @@ struct hwrm_func_qcfg_output {
* value is used if ring MTU is not specified.
*/
uint16_t host_mtu;
- uint8_t unused_3;
+ /* Number of Tx Key Contexts allocated. */
+ uint16_t alloc_tx_key_ctxs;
+ /* Number of Rx Key Contexts allocated. */
+ uint16_t alloc_rx_key_ctxs;
+ uint8_t unused_3[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -12630,7 +12843,7 @@ struct hwrm_func_qcfg_output {
*****************/
-/* hwrm_func_cfg_input (size:832b/104B) */
+/* hwrm_func_cfg_input (size:896b/112B) */
struct hwrm_func_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13076,6 +13289,18 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \
UINT32_C(0x20000000)
+ /*
+ * This bit must be '1' for the number of Tx Key Contexts
+ * field to be configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \
+ UINT32_C(0x40000000)
+ /*
+ * This bit must be '1' for the number of Rx Key Contexts
+ * field to be configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \
+ UINT32_C(0x80000000)
/*
* This field can be used by the admin PF to configure
* mtu of foster PFs.
@@ -13527,6 +13752,11 @@ struct hwrm_func_cfg_input {
* ring that is assigned to a function has a valid mtu.
*/
uint16_t host_mtu;
+ /* Number of Tx Key Contexts requested. */
+ uint16_t num_tx_key_ctxs;
+ /* Number of Rx Key Contexts requested. */
+ uint16_t num_rx_key_ctxs;
+ uint8_t unused_0[4];
} __rte_packed;
/* hwrm_func_cfg_output (size:128b/16B) */
@@ -14103,6 +14333,13 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \
UINT32_C(0x100)
+ /*
+ * When this bit is 1, the function's driver is indicating the
+ * support of handling the NPAR 1.2 feature where the s-tag may be
+ * a value other than 0x8100 or 0x88a8.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \
+ UINT32_C(0x200)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -14664,7 +14901,7 @@ struct hwrm_func_resource_qcaps_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_resource_qcaps_output (size:448b/56B) */
+/* hwrm_func_resource_qcaps_output (size:512b/64B) */
struct hwrm_func_resource_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -14739,6 +14976,14 @@ struct hwrm_func_resource_qcaps_output {
*/
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ /* Minimum guaranteed number of Tx Key Contexts */
+ uint16_t min_tx_key_ctxs;
+ /* Maximum non-guaranteed number of Tx Key Contexts */
+ uint16_t max_tx_key_ctxs;
+ /* Minimum guaranteed number of Rx Key Contexts */
+ uint16_t min_rx_key_ctxs;
+ /* Maximum non-guaranteed number of Rx Key Contexts */
+ uint16_t max_rx_key_ctxs;
uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
@@ -14755,7 +15000,7 @@ struct hwrm_func_resource_qcaps_output {
*****************************/
-/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
+/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
struct hwrm_func_vf_resource_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -14829,6 +15074,14 @@ struct hwrm_func_vf_resource_cfg_input {
*/
#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ /* Minimum guaranteed number of Tx Key Contexts */
+ uint16_t min_tx_key_ctxs;
+ /* Maximum non-guaranteed number of Tx Key Contexts */
+ uint16_t max_tx_key_ctxs;
+ /* Minimum guaranteed number of Rx Key Contexts */
+ uint16_t min_rx_key_ctxs;
+ /* Maximum non-guaranteed number of Rx Key Contexts */
+ uint16_t max_rx_key_ctxs;
uint8_t unused_0[2];
} __rte_packed;
@@ -14858,7 +15111,11 @@ struct hwrm_func_vf_resource_cfg_output {
uint16_t reserved_stat_ctx;
/* Reserved number of ring groups */
uint16_t reserved_hw_ring_grps;
- uint8_t unused_0[7];
+ /* Actual number of Tx Key Contexts reserved */
+ uint16_t reserved_tx_key_ctxs;
+ /* Actual number of Rx Key Contexts reserved */
+ uint16_t reserved_rx_key_ctxs;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -18132,7 +18389,7 @@ struct hwrm_error_recovery_qcfg_output {
/***************************
* hwrm_func_echo_response *
- ****************************/
+ ***************************/
/* hwrm_func_echo_response_input (size:192b/24B) */
@@ -18190,13 +18447,13 @@ struct hwrm_func_echo_response_output {
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/**************************
+ * hwrm_func_ptp_pin_qcfg *
+ **************************/
-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
-struct hwrm_func_vlan_qcfg_input {
+/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
+struct hwrm_func_ptp_pin_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -18225,18 +18482,11 @@ struct hwrm_func_vlan_qcfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[6];
+ uint8_t unused_0[8];
} __rte_packed;
-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
-struct hwrm_func_vlan_qcfg_output {
+/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
+struct hwrm_func_ptp_pin_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -18245,32 +18495,94 @@ struct hwrm_func_vlan_qcfg_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint64_t unused_0;
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
/*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * The number of TSIO pins that are configured on this board
+ * Up to 4 pins can be returned in the response.
*/
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
+ uint8_t num_pins;
+ /* Pin state */
+ uint8_t state;
/*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * When this bit is '1', TSIO pin 0 is enabled.
+ * When this bit is '0', TSIO pin 0 is disabled.
*/
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd2;
- /* Future use. */
- uint32_t rsvd3;
- uint8_t unused_3[3];
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', TSIO pin 1 is enabled.
+ * When this bit is '0', TSIO pin 1 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', TSIO pin 2 is enabled.
+ * When this bit is '0', TSIO pin 2 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', TSIO pin 3 is enabled.
+ * When this bit is '0', TSIO pin 3 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \
+ UINT32_C(0x8)
+ /* Type of function for Pin #0. */
+ uint8_t pin0_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT
+ /* Type of function for Pin #1. */
+ uint8_t pin1_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT
+ /* Type of function for Pin #2. */
+ uint8_t pin2_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT
+ /* Type of function for Pin #3. */
+ uint8_t pin3_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT
+ uint8_t unused_0;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -18281,13 +18593,13 @@ struct hwrm_func_vlan_qcfg_output {
uint8_t valid;
} __rte_packed;
-/**********************
- * hwrm_func_vlan_cfg *
- **********************/
+/*************************
+ * hwrm_func_ptp_pin_cfg *
+ *************************/
-/* hwrm_func_vlan_cfg_input (size:384b/48B) */
-struct hwrm_func_vlan_cfg_input {
+/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
+struct hwrm_func_ptp_pin_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -18316,74 +18628,148 @@ struct hwrm_func_vlan_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[2];
uint32_t enables;
/*
- * This bit must be '1' for the stag_vid field to be
+ * This bit must be '1' for the pin0_state field to be
* configured.
*/
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \
+ UINT32_C(0x1)
/*
- * This bit must be '1' for the ctag_vid field to be
+ * This bit must be '1' for the pin0_usage field to be
* configured.
*/
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \
+ UINT32_C(0x2)
/*
- * This bit must be '1' for the stag_pcp field to be
+ * This bit must be '1' for the pin1_state field to be
* configured.
*/
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \
+ UINT32_C(0x4)
/*
- * This bit must be '1' for the ctag_pcp field to be
+ * This bit must be '1' for the pin1_usage field to be
* configured.
*/
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \
+ UINT32_C(0x8)
/*
- * This bit must be '1' for the stag_tpid field to be
+ * This bit must be '1' for the pin2_state field to be
* configured.
*/
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \
+ UINT32_C(0x10)
/*
- * This bit must be '1' for the ctag_tpid field to be
+ * This bit must be '1' for the pin2_usage field to be
* configured.
*/
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \
+ UINT32_C(0x20)
/*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * This bit must be '1' for the pin3_state field to be
+ * configured.
*/
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \
+ UINT32_C(0x40)
/*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * This bit must be '1' for the pin3_usage field to be
+ * configured.
*/
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd1;
- /* Future use. */
- uint32_t rsvd2;
- uint8_t unused_3[4];
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \
+ UINT32_C(0x80)
+ /* Enable or disable functionality of Pin #0. */
+ uint8_t pin0_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED
+ /* Configure function for TSIO pin#0. */
+ uint8_t pin0_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT
+ /* Enable or disable functionality of Pin #1. */
+ uint8_t pin1_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED
+ /* Configure function for TSIO pin#1. */
+ uint8_t pin1_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT
+ /* Enable or disable functionality of Pin #2. */
+ uint8_t pin2_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED
+ /* Configure function for TSIO pin#2. */
+ uint8_t pin2_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT
+ /* Enable or disable functionality of Pin #3. */
+ uint8_t pin3_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED
+ /* Configure function for TSIO pin#3. */
+ uint8_t pin3_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_func_vlan_cfg_output (size:128b/16B) */
-struct hwrm_func_vlan_cfg_output {
+/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
+struct hwrm_func_ptp_pin_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -18403,13 +18789,812 @@ struct hwrm_func_vlan_cfg_output {
uint8_t valid;
} __rte_packed;
-/*******************************
- * hwrm_func_vf_vnic_ids_query *
- *******************************/
+/*********************
+ * hwrm_func_ptp_cfg *
+ *********************/
-/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
-struct hwrm_func_vf_vnic_ids_query_input {
+/* hwrm_func_ptp_cfg_input (size:320b/40B) */
+struct hwrm_func_ptp_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t enables;
+ /*
+ * This bit must be '1' for the ptp_pps_event field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_dll_source field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_dll_phase field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ext_period field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ext_up field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ext_phase field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \
+ UINT32_C(0x20)
+ /* This field is used to enable interrupt for a specific PPS event. */
+ uint8_t ptp_pps_event;
+ /*
+ * When this bit is set to '1', interrupt is enabled for internal
+ * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does
+ * not configure PPS_OUT on a TSIO pin, then firmware will allocate
+ * PPS_OUT to an unallocated pin.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', interrupt is enabled for external
+ * PPS event. Latches timestamp on PPS_IN TSIO pin.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \
+ UINT32_C(0x2)
+ /*
+ * This field is used to set the source signal used to discipline
+ * PHC (PTP Hardware Clock)
+ */
+ uint8_t ptp_freq_adj_dll_source;
+ /* No source is selected. Use servo to discipline PHC */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \
+ UINT32_C(0x0)
+ /* TSIO Pin #0 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \
+ UINT32_C(0x1)
+ /* TSIO Pin #1 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \
+ UINT32_C(0x2)
+ /* TSIO Pin #2 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \
+ UINT32_C(0x3)
+ /* TSIO Pin #3 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \
+ UINT32_C(0x4)
+ /* Port #0 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \
+ UINT32_C(0x5)
+ /* Port #1 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \
+ UINT32_C(0x6)
+ /* Port #2 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \
+ UINT32_C(0x7)
+ /* Port #3 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \
+ UINT32_C(0x8)
+ /* Invalid signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \
+ UINT32_C(0xff)
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \
+ HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
+ /*
+ * This field is used to provide phase adjustment for DLL
+ * used to discipline PHC (PTP Hardware clock)
+ */
+ uint8_t ptp_freq_adj_dll_phase;
+ /* No Phase adjustment. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \
+ UINT32_C(0x0)
+ /* 4Khz sync in frequency. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \
+ UINT32_C(0x1)
+ /* 8Khz sync in frequency. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \
+ UINT32_C(0x2)
+ /* 10Mhz sync in frequency. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \
+ UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \
+ HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M
+ uint8_t unused_0[3];
+ /*
+ * Period in nanoseconds (ns) for external signal
+ * input.
+ */
+ uint32_t ptp_freq_adj_ext_period;
+ /*
+ * Up time in nanoseconds (ns) of the duty cycle
+ * of the external signal. This value should be
+ * less than ptp_freq_adj_ext_period.
+ */
+ uint32_t ptp_freq_adj_ext_up;
+ /*
+ * Phase value is provided. This field provides the
+ * least significant 32 bits of the phase input. The
+ * most significant 16 bits come from
+ * ptp_freq_adj_ext_phase_upper field. Setting this
+ * field requires setting ptp_freq_adj_ext_period
+ * field as well to identify the external signal
+ * pin.
+ */
+ uint32_t ptp_freq_adj_ext_phase_lower;
+ /*
+ * Phase value is provided. The lower 16 bits of this field is used
+ * with the 32 bit value from ptp_freq_adj_ext_phase_lower
+ * to provide a 48 bit value input for Phase.
+ */
+ uint32_t ptp_freq_adj_ext_phase_upper;
+} __rte_packed;
+
+/* hwrm_func_ptp_cfg_output (size:128b/16B) */
+struct hwrm_func_ptp_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_func_ptp_ts_query *
+ **************************/
+
+
+/* hwrm_func_ptp_ts_query_input (size:192b/24B) */
+struct hwrm_func_ptp_ts_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If set, the response includes PPS event timestamps */
+ #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)
+ /* If set, the response includes PTM timestamps */
+ #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_func_ptp_ts_query_output (size:320b/40B) */
+struct hwrm_func_ptp_ts_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Timestamp value of last PPS event latched. */
+ uint64_t pps_event_ts;
+ /* PTM local timestamp value. */
+ uint64_t ptm_res_local_ts;
+ /* PTM Master timestamp value. */
+ uint64_t ptm_pmstr_ts;
+ /* PTM Master propagation delay */
+ uint32_t ptm_mstr_prop_dly;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_func_ptp_ext_cfg *
+ *************************/
+
+
+/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
+struct hwrm_func_ptp_ext_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t enables;
+ /*
+ * This bit must be '1' for the phc_master_fid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the phc_sec_fid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the phc_sec_mode field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the failover_timer field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \
+ UINT32_C(0x8)
+ /*
+ * This field is used to configure the Master function. Only this
+ * function can modify or condition the PHC. Only driver calls from
+ * this function are allowed to adjust frequency of PHC or configure
+ * PPS functionality.
+ * If driver does not specify this FID, then firmware will auto select
+ * the first function that makes the call to modify PHC as the Master.
+ */
+ uint16_t phc_master_fid;
+ /*
+ * This field is used to configure the secondary function. This
+ * function becomes the Master function in case of failover from
+ * Master function.
+ * If driver does not specify this FID, firmware will auto select
+ * the last non-master function to make a call to condition PHC as
+ * secondary.
+ */
+ uint16_t phc_sec_fid;
+ /*
+ * This field is used to configure conditions under which a function
+ * can become a secondary function.
+ */
+ uint8_t phc_sec_mode;
+ /*
+ * Immediately failover to the current secondary function. If there
+ * is no secondary function available, failover does not happen.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)
+ /*
+ * All functions (PF and VF) can be used during auto selection
+ * of a secondary function. This is not used in case of admin
+ * configured secondary function.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)
+ /*
+ * Only PF's can be selected as a secondary function during auto
+ * selection. This is not used in case of admin configured secondary
+ * function.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \
+ HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY
+ uint8_t unused_0;
+ /*
+ * This field indicates the failover time is milliseconds. If the
+ * timeout expires, firmware will failover PTP configurability from
+ * current master to secondary fid.
+ * 0 - Failover timer is automatically selected based on the last
+ * adjFreq() call. If adjFreq() is not called for 3 * (last interval)
+ * the failover kicks in. For example, if last interval between
+ * adjFreq() calls was 2 seconds and the next adjFreq() is not made for
+ * at least 6 seconds, then secondary takes over as master to condition
+ * PHC. Firmware rounds up the failover timer to be a multiple of 250
+ * ms. Firmware checks every 250 ms to see if timer expired.
+ * 0xFFFFFFFF - If driver specifies this value, then failover never
+ * happens. Admin or auto selected Master will always be used for
+ * conditioning PHC.
+ * X - If driver specifies any other value, this is admin indicated
+ * failover timeout. If no adjFreq() call is made within this timeout
+ * value, then failover happens. This value should be a multiple of
+ * 250 ms. Firmware checks every 250 ms to see if timer expired.
+ */
+ uint32_t failover_timer;
+ uint8_t unused_1[4];
+} __rte_packed;
+
+/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
+struct hwrm_func_ptp_ext_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_func_ptp_ext_qcfg *
+ **************************/
+
+
+/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
+struct hwrm_func_ptp_ext_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __rte_packed;
+
+/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
+struct hwrm_func_ptp_ext_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Firmware returns the current PHC master function. This function
+ * could either be admin selected or auto selected.
+ */
+ uint16_t phc_master_fid;
+ /*
+ * Firmware returns the current PHC secondary function. This function
+ * could either be admin selected or auto selected.
+ */
+ uint16_t phc_sec_fid;
+ /*
+ * Firmware returns the last non-master/non-secondary function to
+ * make a call to condition PHC.
+ */
+ uint16_t phc_active_fid0;
+ /*
+ * Firmware returns the second last non-master/non-secondary function
+ * to make a call to condition PHC.
+ */
+ uint16_t phc_active_fid1;
+ /*
+ * Timestamp indicating the last time a failover happened. The master
+ * and secondary functions in the failover event is indicated in the
+ * next two fields.
+ */
+ uint32_t last_failover_event;
+ /*
+ * Last failover happened from this function. This was the master
+ * function at the time of failover.
+ */
+ uint16_t from_fid;
+ /*
+ * Last failover happened to this function. This was the secondary
+ * function at the time of failover.
+ */
+ uint16_t to_fid;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_func_key_ctx_alloc *
+ ***************************/
+
+
+/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */
+struct hwrm_func_key_ctx_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Function ID. */
+ uint16_t fid;
+ /* Number of Key Contexts to be allocated. */
+ uint16_t num_key_ctxs;
+ /* DMA buffer size in bytes. */
+ uint32_t dma_bufr_size_bytes;
+ /* Key Context type. */
+ uint8_t key_ctx_type;
+ /* Tx Key Context. */
+ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
+ /* Rx KTLS Context. */
+ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
+ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \
+ HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX
+ uint8_t unused_0[7];
+ /* Host DMA address to send back KTLS context IDs. */
+ uint64_t host_dma_addr;
+} __rte_packed;
+
+/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */
+struct hwrm_func_key_ctx_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Actual number of Key Contexts allocated. */
+ uint16_t num_key_ctxs_allocated;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
+
+
+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
+struct hwrm_func_vlan_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Function ID of the function that is being
+ * configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
+ */
+ uint16_t fid;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
+struct hwrm_func_vlan_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint64_t unused_0;
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
+ /*
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
+ /*
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd2;
+ /* Future use. */
+ uint32_t rsvd3;
+ uint8_t unused_3[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_func_vlan_cfg *
+ **********************/
+
+
+/* hwrm_func_vlan_cfg_input (size:384b/48B) */
+struct hwrm_func_vlan_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Function ID of the function that is being
+ * configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
+ */
+ uint16_t fid;
+ uint8_t unused_0[2];
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the stag_vid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the ctag_vid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the stag_pcp field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the ctag_pcp field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the stag_tpid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ctag_tpid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
+ /*
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
+ /*
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd1;
+ /* Future use. */
+ uint32_t rsvd2;
+ uint8_t unused_3[4];
+} __rte_packed;
+
+/* hwrm_func_vlan_cfg_output (size:128b/16B) */
+struct hwrm_func_vlan_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_func_vf_vnic_ids_query *
+ *******************************/
+
+
+/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
+struct hwrm_func_vf_vnic_ids_query_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -19128,7 +20313,7 @@ struct hwrm_func_spd_cfg_input {
UINT32_C(0x10)
/*
* Ethertype value used in the encapsulated SPD packet header.
- * The user must choose a value that is not conflicting with
+ * The user must chooose a value that is not conflicting with
* publicly defined ethertype values. By default, the ethertype
* value of 0xffff is used if there is no user specified value.
*/
@@ -19387,7 +20572,7 @@ struct hwrm_func_spd_qcfg_output {
uint8_t unused_1;
/*
* Ethertype value used in the encapsulated SPD packet header.
- * The user must choose a value that is not conflicting with
+ * The user must chooose a value that is not conflicting with
* publicly defined ethertype values. By default, the ethertype
* value of 0xffff is used if there is no user specified value.
*/
@@ -21398,6 +22583,12 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the ptp_adj_phase field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \
+ UINT32_C(0x400)
/* Port ID of port that is to be configured. */
uint16_t port_id;
/*
@@ -21590,7 +22781,12 @@ struct hwrm_port_mac_cfg_input {
* of sync timer updates (measured in parts per billion).
*/
int32_t ptp_freq_adj_ppb;
- uint8_t unused_1[4];
+ /*
+ * This unsigned field specifies the phase offset to be applied
+ * to the PHC (PTP Hardware Clock). This field is specified in
+ * nanoseconds.
+ */
+ uint32_t ptp_adj_phase;
} __rte_packed;
/* hwrm_port_mac_cfg_output (size:128b/16B) */
@@ -21991,7 +23187,7 @@ struct hwrm_port_mac_ptp_qcfg_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
+/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
struct hwrm_port_mac_ptp_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -22024,10 +23220,23 @@ struct hwrm_port_mac_ptp_qcfg_output {
*/
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x8)
+ /*
+ * When this bit is set to '1', two specific registers for current
+ * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are
+ * directly accessible by the host.
+ */
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \
+ UINT32_C(0x10)
uint8_t unused_0[3];
- /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
+ /*
+ * Offset of the PTP register for the lower 32 bits of timestamp
+ * for RX.
+ */
uint32_t rx_ts_reg_off_lower;
- /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
+ /*
+ * Offset of the PTP register for the upper 32 bits of timestamp
+ * for RX.
+ */
uint32_t rx_ts_reg_off_upper;
/* Offset of the PTP register for the sequence ID for RX. */
uint32_t rx_ts_reg_off_seq_id;
@@ -22045,9 +23254,15 @@ struct hwrm_port_mac_ptp_qcfg_output {
uint32_t rx_ts_reg_off_fifo_adv;
/* PTP timestamp granularity for RX. */
uint32_t rx_ts_reg_off_granularity;
- /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
+ /*
+ * Offset of the PTP register for the lower 32 bits of timestamp
+ * for TX.
+ */
uint32_t tx_ts_reg_off_lower;
- /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
+ /*
+ * Offset of the PTP register for the upper 32 bits of timestamp
+ * for TX.
+ */
uint32_t tx_ts_reg_off_upper;
/* Offset of the PTP register for the sequence ID for TX. */
uint32_t tx_ts_reg_off_seq_id;
@@ -22055,6 +23270,10 @@ struct hwrm_port_mac_ptp_qcfg_output {
uint32_t tx_ts_reg_off_fifo;
/* PTP timestamp granularity for TX. */
uint32_t tx_ts_reg_off_granularity;
+ /* Offset of register to get lower 32 bits of current time. */
+ uint32_t ts_ref_clock_reg_lower;
+ /* Offset of register to get upper 32 bits of current time. */
+ uint32_t ts_ref_clock_reg_upper;
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
@@ -22578,7 +23797,7 @@ struct tx_port_stats_ext {
} __rte_packed;
/* Port Rx Statistics extended Format */
-/* rx_port_stats_ext (size:3648b/456B) */
+/* rx_port_stats_ext (size:3776b/472B) */
struct rx_port_stats_ext {
/* Number of times link state changed to down */
uint64_t link_down_events;
@@ -22697,6 +23916,13 @@ struct rx_port_stats_ext {
uint64_t rx_discard_packets_cos6;
/* Total number of rx discard packets count on cos queue 7 */
uint64_t rx_discard_packets_cos7;
+ /* Total number of FEC blocks corrected by the FEC function in the PHY */
+ uint64_t rx_fec_corrected_blocks;
+ /*
+ * Total number of FEC blocks determined to be uncorrectable by the
+ * FEC function in the PHY
+ */
+ uint64_t rx_fec_uncorrectable_blocks;
} __rte_packed;
/*
@@ -25981,6 +27207,309 @@ struct hwrm_port_tx_fir_qcfg_output {
uint8_t valid;
} __rte_packed;
+/***********************
+ * hwrm_port_ep_tx_cfg *
+ ***********************/
+
+
+/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */
+struct hwrm_port_ep_tx_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t enables;
+ /* When this bit is '1', the value in the ep0_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)
+ /* When this bit is '1', the value in the ep0_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)
+ /* When this bit is '1', the value in the ep1_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)
+ /* When this bit is '1', the value in the ep1_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)
+ /* When this bit is '1', the value in the ep2_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)
+ /* When this bit is '1', the value in the ep2_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)
+ /* When this bit is '1', the value in the ep3_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)
+ /* When this bit is '1', the value in the ep3_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)
+ /* A port index, from 0 to the number of front panel ports, minus 1. */
+ uint8_t port_id;
+ uint8_t unused;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep0_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep0_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep1_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep1_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep2_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set of
+ * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of
+ * the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep2_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep3_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep3_max_bw;
+ uint8_t unused_1[4];
+} __rte_packed;
+
+/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */
+struct hwrm_port_ep_tx_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */
+struct hwrm_port_ep_tx_cfg_cmd_err {
+ /*
+ * command specific error codes for the cmd_err field in
+ * hwrm_err_output
+ */
+ uint8_t code;
+ /* Unknown error. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
+ /* The port ID is invalid */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \
+ UINT32_C(0x1)
+ /* One of the PCIe endpoints configured is not active. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \
+ UINT32_C(0x2)
+ /* A minimum bandwidth is out of range. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \
+ UINT32_C(0x3)
+ /*
+ * One endpoint's minimum bandwidth is more than its maximum
+ * bandwidth.
+ */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \
+ UINT32_C(0x4)
+ /* The sum of the minimum bandwidths on the port is more than 100%. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \
+ UINT32_C(0x5)
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \
+ HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/************************
+ * hwrm_port_ep_tx_qcfg *
+ ************************/
+
+
+/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */
+struct hwrm_port_ep_tx_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The port whose endpoint rate limits are queried. */
+ uint8_t port_id;
+ uint8_t unused[7];
+} __rte_packed;
+
+/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */
+struct hwrm_port_ep_tx_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep0_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep0_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep1_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep1_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep2_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep2_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep3_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep3_max_bw;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -26097,6 +27626,13 @@ struct hwrm_queue_qportcfg_output {
*/
#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
UINT32_C(0x1)
+ /*
+ * If this flag is set to '1', then service_profile will carry
+ * either lossy/lossless type and the new service_profile_type
+ * field will be used to determine if the queue is for L2/ROCE/CNP.
+ */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \
+ UINT32_C(0x2)
/*
* Bitmask indicating which queues can be configured by the
* hwrm_queue_pfcenable_cfg command.
@@ -30204,67 +31740,221 @@ struct hwrm_queue_vlanpri2pri_qcfg_input {
* to configure VLAN priority to user priority mapping on this port.
*/
uint8_t port_id;
- uint8_t unused_0[7];
-} __rte_packed;
-
-/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
-struct hwrm_queue_vlanpri2pri_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
+struct hwrm_queue_vlanpri2pri_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * User priority assigned to VLAN priority 0. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri0_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 1. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri1_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 2. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri2_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 3. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri3_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 4. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri4_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 5. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri5_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 6. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri6_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 7. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri7_user_pri_id;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_queue_vlanpri2pri_cfg *
+ ******************************/
+
+
+/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
+struct hwrm_queue_vlanpri2pri_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vlanpri0_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the vlanpri1_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the vlanpri2_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the vlanpri3_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the vlanpri4_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the vlanpri5_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the vlanpri6_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the vlanpri7_user_pri_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
+ UINT32_C(0x80)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure VLAN priority to user priority mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[3];
/*
- * User priority assigned to VLAN priority 0. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 0. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri0_user_pri_id;
/*
- * User priority assigned to VLAN priority 1. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 1. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri1_user_pri_id;
/*
- * User priority assigned to VLAN priority 2. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 2. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri2_user_pri_id;
/*
- * User priority assigned to VLAN priority 3. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 3. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri3_user_pri_id;
/*
- * User priority assigned to VLAN priority 4. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 4. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri4_user_pri_id;
/*
- * User priority assigned to VLAN priority 5. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 5. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri5_user_pri_id;
/*
- * User priority assigned to VLAN priority 6. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 6. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri6_user_pri_id;
/*
- * User priority assigned to VLAN priority 7. A value of 0xff
- * indicates that no user priority is assigned. The default user
- * priority will be used.
+ * User priority assigned to VLAN priority 7. This value can only
+ * be changed before traffic has started.
*/
uint8_t vlanpri7_user_pri_id;
+} __rte_packed;
+
+/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
+struct hwrm_queue_vlanpri2pri_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -30276,13 +31966,13 @@ struct hwrm_queue_vlanpri2pri_qcfg_output {
uint8_t valid;
} __rte_packed;
-/******************************
- * hwrm_queue_vlanpri2pri_cfg *
- ******************************/
+/*************************
+ * hwrm_queue_global_cfg *
+ *************************/
-/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
-struct hwrm_queue_vlanpri2pri_cfg_input {
+/* hwrm_queue_global_cfg_input (size:192b/24B) */
+struct hwrm_queue_global_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -30311,106 +32001,142 @@ struct hwrm_queue_vlanpri2pri_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- /*
- * This bit must be '1' for the vlanpri0_user_pri_id field to be
- * configured.
- */
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
- UINT32_C(0x1)
- /*
- * This bit must be '1' for the vlanpri1_user_pri_id field to be
- * configured.
- */
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
- UINT32_C(0x2)
/*
- * This bit must be '1' for the vlanpri2_user_pri_id field to be
- * configured.
+ * Configuration mode for rx cos queues, configuring whether they
+ * use one shared buffer pool (across ports or PCIe endpoints) or
+ * independent per port or per endpoint buffer pools.
*/
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
- UINT32_C(0x4)
+ uint8_t mode;
+ /* One shared buffer pool to be used by all RX CoS queues */
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)
/*
- * This bit must be '1' for the vlanpri3_user_pri_id field to be
- * configured.
+ * Each port or PCIe endpoint to use an independent buffer pool
+ * for its RX CoS queues
*/
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
- UINT32_C(0x8)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \
+ HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT
+ uint8_t unused_0;
+ uint16_t enables;
+ /* This bit must be '1' when the mode field is configured. */
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)
/*
- * This bit must be '1' for the vlanpri4_user_pri_id field to be
- * configured.
+ * This bit must be '1' when the maximum bandwidth for queue group 0
+ * (g0_max_bw) is configured.
*/
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
- UINT32_C(0x10)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)
/*
- * This bit must be '1' for the vlanpri5_user_pri_id field to be
- * configured.
+ * This bit must be '1' when the maximum bandwidth for queue group 1
+ * (g1_max_bw) is configured.
*/
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
- UINT32_C(0x20)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)
/*
- * This bit must be '1' for the vlanpri6_user_pri_id field to be
- * configured.
+ * This bit must be '1' when the maximum bandwidth for queue group 2
+ * (g2_max_bw) is configured.
*/
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
- UINT32_C(0x40)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)
/*
- * This bit must be '1' for the vlanpri7_user_pri_id field to be
- * configured.
+ * This bit must be '1' when the maximum bandwidth for queue group 3
+ * (g3_max_bw) is configured.
*/
- #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
- UINT32_C(0x80)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \
+ UINT32_C(0x10)
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure VLAN priority to user priority mapping on this port.
+ * Specifies the maximum receive rate, as a percentage of total link
+ * bandwidth, of the receive traffic through queue group 0. A value
+ * of 0 indicates no rate limit.
+ *
+ * A queue group is a set of queues, one per traffic class. In
+ * single-host mode, each panel port has its own queue group, and thus,
+ * this rate limit shapes the traffic received on a port, in this case,
+ * through port 0. In multi-root or multi-host mode, each PCIe endpoint
+ * on the NIC has its own queue group. In these cases, the rate limit
+ * shapes the traffic sent to the host through one of the PCIe
+ * endpoints, in this case endpoint 0.
*/
- uint8_t port_id;
- uint8_t unused_0[3];
+ uint8_t g0_max_bw;
/*
- * User priority assigned to VLAN priority 0. This value can only
- * be changed before traffic has started.
+ * Specifies the maximum rate of the traffic through receive CoS queue
+ * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of
+ * total link bandwidth (the sum of the bandwidths of all links). A
+ * value of 0 indicates no rate limit.
*/
- uint8_t vlanpri0_user_pri_id;
+ uint8_t g1_max_bw;
/*
- * User priority assigned to VLAN priority 1. This value can only
- * be changed before traffic has started.
+ * Specifies the maximum rate of the traffic through receive CoS queue
+ * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of
+ * total link bandwidth (the sum of the bandwidths of all links). A
+ * value of 0 indicates no rate limit.
*/
- uint8_t vlanpri1_user_pri_id;
+ uint8_t g2_max_bw;
/*
- * User priority assigned to VLAN priority 2. This value can only
- * be changed before traffic has started.
+ * Specifies the maximum receive rate, in Mbps, of the receive traffic
+ * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0
+ * indicates no rate limit.
*/
- uint8_t vlanpri2_user_pri_id;
+ uint8_t g3_max_bw;
+} __rte_packed;
+
+/* hwrm_queue_global_cfg_output (size:128b/16B) */
+struct hwrm_queue_global_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * User priority assigned to VLAN priority 3. This value can only
- * be changed before traffic has started.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t vlanpri3_user_pri_id;
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_queue_global_qcfg *
+ **************************/
+
+
+/* hwrm_queue_global_qcfg_input (size:128b/16B) */
+struct hwrm_queue_global_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * User priority assigned to VLAN priority 4. This value can only
- * be changed before traffic has started.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t vlanpri4_user_pri_id;
+ uint16_t cmpl_ring;
/*
- * User priority assigned to VLAN priority 5. This value can only
- * be changed before traffic has started.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t vlanpri5_user_pri_id;
+ uint16_t seq_id;
/*
- * User priority assigned to VLAN priority 6. This value can only
- * be changed before traffic has started.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint8_t vlanpri6_user_pri_id;
+ uint16_t target_id;
/*
- * User priority assigned to VLAN priority 7. This value can only
- * be changed before traffic has started.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint8_t vlanpri7_user_pri_id;
+ uint64_t resp_addr;
} __rte_packed;
-/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
-struct hwrm_queue_vlanpri2pri_cfg_output {
+/* hwrm_queue_global_qcfg_output (size:320b/40B) */
+struct hwrm_queue_global_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -30419,7 +32145,95 @@ struct hwrm_queue_vlanpri2pri_cfg_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* Port or PCIe endpoint id to be mapped for buffer pool 0. */
+ uint8_t buffer_pool_id0_map;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 1. */
+ uint8_t buffer_pool_id1_map;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 2. */
+ uint8_t buffer_pool_id2_map;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 3. */
+ uint8_t buffer_pool_id3_map;
+ /* Size of buffer pool 0 (KBytes). */
+ uint32_t buffer_pool_id0_size;
+ /* Size of buffer pool 1 (KBytes). */
+ uint32_t buffer_pool_id1_size;
+ /* Size of buffer pool 2 (KBytes). */
+ uint32_t buffer_pool_id2_size;
+ /* Size of buffer pool 3 (KBytes). */
+ uint32_t buffer_pool_id3_size;
+ uint16_t flags;
+ /*
+ * Enumeration denoting whether the rx buffer pool mapping is
+ * per port or per PCIe endpoint
+ */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \
+ UINT32_C(0x1)
+ /*
+ * The buffer_pool_id[0-3]_map field represents mapping of rx
+ * buffer pools to a port.
+ */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \
+ UINT32_C(0x0)
+ /*
+ * The buffer_pool_id[0-3]_map field represents mapping of rx
+ * buffer pools to a PCIe endpoint.
+ */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \
+ UINT32_C(0x1)
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \
+ HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT
+ /*
+ * Configuration mode for rx cos queues, configuring whether they
+ * use one shared buffer pool (across ports or PCIe endpoints) or
+ * independent per port or per endpoint buffer pools.
+ */
+ uint8_t mode;
+ /* One shared buffer pool to be used by all RX CoS queues */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)
+ /*
+ * Each port or PCIe endpoint to use an independent buffer pool
+ * for its RX CoS queues
+ */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \
+ HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT
+ uint8_t unused_0;
+ /*
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 0. The rate limit is a percentage of total link bandwidth. A
+ * value of 0 indicates no rate limit.
+ *
+ * A queue group is a set of queues, one per traffic class. In
+ * single-host mode, each panel port has its own queue group, and thus,
+ * this rate limit shapes the traffic received on a port, in this case,
+ * through port 0. In multi-root or multi-host mode, each PCIe endpoint
+ * on the NIC has its own queue group. In these cases, the rate limit
+ * shapes the traffic sent to the host through one of the PCIe
+ * endpoints, in this case endpoint 0.
+ */
+ uint8_t g0_max_bw;
+ /*
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a
+ * percentage of total link bandwidth. A value of 0 indicates no rate
+ * limit.
+ */
+ uint8_t g1_max_bw;
+ /*
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a
+ * percentage of total link bandwidth. A value of 0 indicates no rate
+ * limit.
+ */
+ uint8_t g2_max_bw;
+ /*
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a
+ * percentage of total link bandwidth. A value of 0 indicates no rate
+ * limit.
+ */
+ uint8_t g3_max_bw;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -31324,6 +33138,13 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
UINT32_C(0x1000)
+ /*
+ * When this bit is set '1', it indicates that firmware returns
+ * INVALID_PARAM error, if host drivers choose invalid hash type
+ * bit combinations in vnic_rss_cfg.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \
+ UINT32_C(0x2000)
/*
* This field advertises the maximum concurrent TPA aggregations
* supported by the VNIC on new devices that support TPA v2.
@@ -31674,7 +33495,34 @@ struct hwrm_vnic_rss_cfg_input {
uint64_t hash_key_tbl_addr;
/* Index to the rss indirection table. */
uint16_t rss_ctx_idx;
- uint8_t unused_1[6];
+ uint8_t flags;
+ /*
+ * When this bit is '1', it indicates that the hash_type field is
+ * interpreted as a change relative the current configuration. Each
+ * '1' bit in hash_type represents a header to add to the current
+ * hash. Zeroes designate the hash_type state bits that should remain
+ * unchanged, if possible. If this constraint on the existing state
+ * cannot be satisfied, then the implementation should preference
+ * adding other headers so as to honor the request to add the
+ * specified headers. It is an error to set this flag concurrently
+ * with hash_type_exclude.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the hash_type field is
+ * interpreted as a change relative the current configuration. Each
+ * '1' bit in hash_type represents a header to remove from the
+ * current hash. Zeroes designate the hash_type state bits that
+ * should remain unchanged, if possible. If this constraint on the
+ * existing state cannot be satisfied, then the implementation should
+ * preference removing other headers so as to honor the request to
+ * remove the specified headers. It is an error to set this flag
+ * concurrently with hash_type_include.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \
+ UINT32_C(0x2)
+ uint8_t unused_1[5];
} __rte_packed;
/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
@@ -43062,6 +44910,161 @@ struct hwrm_cfa_tflib_output {
uint8_t valid;
} __rte_packed;
+/**********************************
+ * hwrm_cfa_lag_group_member_rgtr *
+ **********************************/
+
+
+/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */
+struct hwrm_cfa_lag_group_member_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t mode;
+ /*
+ * Transmit only on the active port. Automatically failover
+ * to backup port.
+ */
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \
+ UINT32_C(0x1)
+ /*
+ * Transmit based on packet header ntuple hash. Packet with only
+ * layer 2 headers will hash using the destination MAC, source MAC
+ * and Ethertype fields. Packets with layer 3 (IP) headers will
+ * hash using the destination MAC, source MAC, IP protocol/next
+ * header, source IP address and destination IP address. Packets
+ * with layer 4 (TCP/UDP) headers will hash using the destination
+ * MAC, source MAC, IP protocol/next header, source IP address,
+ * destination IP address, source port and destination port fields.
+ */
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \
+ UINT32_C(0x2)
+ /* Transmit packets on all specified ports. */
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \
+ UINT32_C(0x3)
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \
+ HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST
+ /*
+ * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,
+ * bit2 = port 2, bit3 = port 4, bit4 = loopback port
+ */
+ uint8_t port_bitmap;
+ /* Specify the active port when active-backup mode is specified */
+ uint8_t active_port;
+ uint8_t unused_0[5];
+} __rte_packed;
+
+/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_lag_group_member_rgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* lag group ID configured for the function */
+ uint16_t lag_id;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************************
+ * hwrm_cfa_lag_group_member_unrgtr *
+ ************************************/
+
+
+/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_lag_group_member_unrgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* lag group ID configured for the function */
+ uint16_t lag_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_lag_group_member_unrgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/***********
* hwrm_tf *
***********/
@@ -43263,8 +45266,13 @@ struct hwrm_tf_session_open_output {
* the newly created session.
*/
uint32_t fw_session_client_id;
+ /* This field is used to return the status of fw session to host. */
uint32_t flags;
- /* Indicates if the shared session has been created. */
+ /*
+ * Indicates if the shared session has been created. Shared seesion
+ * should be the first session created ever. Its fw_rm_client_id
+ * should be 1. The AFM session's fw_rm_client_id is 0.
+ */
#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \
UINT32_C(0x1)
/*
@@ -43745,7 +45753,7 @@ struct hwrm_tf_session_resc_qcaps_input {
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
@@ -43860,7 +45868,7 @@ struct hwrm_tf_session_resc_alloc_input {
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
@@ -43959,7 +45967,7 @@ struct hwrm_tf_session_resc_free_input {
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
@@ -44043,7 +46051,7 @@ struct hwrm_tf_session_resc_flush_input {
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
@@ -44248,7 +46256,7 @@ struct hwrm_tf_tbl_type_get_input {
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
@@ -44337,7 +46345,7 @@ struct hwrm_tf_tbl_type_set_input {
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
@@ -44819,7 +46827,7 @@ struct hwrm_tf_ext_em_qcaps_input {
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
UINT32_C(0x1)
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
@@ -44997,7 +47005,7 @@ struct hwrm_tf_ext_em_op_input {
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
@@ -45104,7 +47112,7 @@ struct hwrm_tf_ext_em_cfg_input {
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
UINT32_C(0x1)
#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
@@ -45309,7 +47317,7 @@ struct hwrm_tf_ext_em_qcfg_input {
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
@@ -45335,7 +47343,7 @@ struct hwrm_tf_ext_em_qcfg_output {
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
UINT32_C(0x1)
#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
@@ -45475,7 +47483,7 @@ struct hwrm_tf_em_insert_input {
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
@@ -45556,7 +47564,7 @@ struct hwrm_tf_em_hash_insert_input {
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
@@ -45637,13 +47645,13 @@ struct hwrm_tf_em_delete_input {
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
/* Unused0 */
uint16_t unused0;
- /* EM internal flow hanndle. */
+ /* EM internal flow handle. */
uint64_t flow_handle;
/* EM Key value */
uint64_t em_key[8];
@@ -45785,7 +47793,7 @@ struct hwrm_tf_tcam_set_input {
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
@@ -45887,7 +47895,7 @@ struct hwrm_tf_tcam_get_input {
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
@@ -45983,7 +47991,7 @@ struct hwrm_tf_tcam_move_input {
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
@@ -46066,7 +48074,7 @@ struct hwrm_tf_tcam_free_input {
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
@@ -46149,7 +48157,7 @@ struct hwrm_tf_global_cfg_set_input {
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
@@ -46233,7 +48241,7 @@ struct hwrm_tf_global_cfg_get_input {
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
@@ -46308,7 +48316,7 @@ struct hwrm_tf_if_tbl_get_input {
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
@@ -46397,7 +48405,7 @@ struct hwrm_tf_if_tbl_set_input {
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
@@ -46484,7 +48492,7 @@ struct hwrm_tf_tbl_type_bulk_get_input {
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
@@ -48261,7 +50269,7 @@ struct hwrm_nvm_get_dir_info_output {
******************/
-/* hwrm_nvm_write_input (size:384b/48B) */
+/* hwrm_nvm_write_input (size:448b/56B) */
struct hwrm_nvm_write_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -48296,10 +50304,7 @@ struct hwrm_nvm_write_input {
* This is where the source data is.
*/
uint64_t host_src_addr;
- /*
- * The Directory Entry Type (valid values are defined in the
- * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
- */
+ /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
uint16_t dir_type;
/*
* Directory ordinal.
@@ -48311,10 +50316,8 @@ struct hwrm_nvm_write_input {
/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
uint16_t dir_attr;
/*
- * Length of data to write, in bytes.May be
- * less than or equal to the allocated size for the directory entry.
- * The data length stored in the directory entry will be updated to
- * reflect this value once the write is complete.
+ * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
+ * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
*/
uint32_t dir_data_length;
/* Option. */
@@ -48327,17 +50330,41 @@ struct hwrm_nvm_write_input {
#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
UINT32_C(0x1)
/*
- * The requested length of the allocated NVM for the item, in bytes.
- * This value may be greater than or equal to the specified data length (dir_data_length).
+ * This flag indicates the sender wants to modify a continuous
+ * NVRAM area using a batch of this HWRM requests. The
+ * offset of a request must be continuous to the end of previous
+ * request's. Firmware does not update the directory entry until
+ * receiving the last request, which is indicated by the batch_last
+ * flag. This flag is set usually when a sender does not have a
+ * block of memory that is big enough to hold the entire NVRAM
+ * data for send at one time.
+ */
+ #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \
+ UINT32_C(0x2)
+ /*
+ * This flag can be used only when the batch_mode flag is set. It
+ * indicates this request is the last of batch requests.
+ */
+ #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \
+ UINT32_C(0x4)
+ /*
+ * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
* If this value is less than the specified data length, it will be ignored.
- * The response will contain the actual allocated item length, which may
- * be greater than the requested item length.
- * The purpose for allocating more than the required number of bytes for
- * an item's data is to pre-allocate extra storage (padding) to accommodate
- * the potential future growth of an item (e.g. upgraded firmware with
- * a size increase, log growth, expanded configuration data).
+ * The response will contain the actual allocated item length, which may be greater than the requested item length.
+ * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
+ * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
*/
uint32_t dir_item_length;
+ /*
+ * 32-bit offset of data blob from where data is being written.
+ * Only valid for batch mode. For non-batch writes 'dont care'.
+ */
+ uint32_t offset;
+ /*
+ * Length of data to be written.Should be non-zero.
+ * Only valid for batch mode. For non-batch writes 'dont care'.
+ */
+ uint32_t len;
uint32_t unused_0;
} __rte_packed;
@@ -48352,10 +50379,8 @@ struct hwrm_nvm_write_output {
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * Length of the allocated NVM for the item, in bytes. The value may be
- * greater than or equal to the specified data length or the requested item length.
- * The actual item length used when creating a new directory entry will
- * be a multiple of an NVM block size.
+ * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
+ * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
*/
uint32_t dir_item_length;
/* The directory index of the created or modified item. */
@@ -48699,10 +50724,7 @@ struct hwrm_nvm_get_dev_info_output {
/* Total size, in bytes of the NVRAM device. */
uint32_t nvram_size;
uint32_t reserved_size;
- /*
- * Available size that can be used, in bytes. Available size is the
- * NVRAM size take away the used size and reserved size.
- */
+ /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
uint32_t available_size;
/* This field represents the major version of NVM cfg */
uint8_t nvm_cfg_ver_maj;
@@ -48844,10 +50866,7 @@ struct hwrm_nvm_mod_dir_entry_input {
* The (0-based) instance of this Directory Type.
*/
uint16_t dir_ordinal;
- /*
- * The Directory Entry Extension flags (see BNX_DIR_EXT_* for
- * extension flag definitions).
- */
+ /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
uint16_t dir_ext;
/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
uint16_t dir_attr;
@@ -49016,10 +51035,8 @@ struct hwrm_nvm_install_update_input {
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
UINT32_C(0x1)
/*
- * If set to 1, then unspecified images, images not in the package file,
- * will be safely deleted.
- * When combined with erase_unused_space then unspecified images will be
- * securely erased.
+ * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
+ * When combined with erase_unused_space then unspecified images will be securely erased.
*/
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
UINT32_C(0x2)
@@ -49116,13 +51133,19 @@ struct hwrm_nvm_install_update_cmd_err {
*/
uint8_t code;
/* Unknown error */
- #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
/* Unable to complete operation due to fragmentation */
- #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \
+ UINT32_C(0x1)
/* nvm is completely full. */
- #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \
+ UINT32_C(0x2)
+ /* Firmware update failed due to Anti-rollback. */
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \
+ UINT32_C(0x3)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
- HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
+ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
uint8_t unused_0[7];
} __rte_packed;
@@ -49404,10 +51427,7 @@ struct hwrm_nvm_set_variable_input {
/* index for the 4th dimensions */
uint16_t index_3;
uint8_t flags;
- /*
- * When this bit is 1, flush internal cache after this write operation
- * (see hwrm_nvm_flush command.)
- */
+ /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
UINT32_C(0x1)
/* encryption method */
@@ -49589,6 +51609,84 @@ struct hwrm_nvm_validate_option_cmd_err {
uint8_t unused_0[7];
} __rte_packed;
+/*******************
+ * hwrm_nvm_defrag *
+ *******************/
+
+
+/* hwrm_nvm_defrag_input (size:192b/24B) */
+struct hwrm_nvm_defrag_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* This bit must be '1' to perform NVM defragmentation. */
+ #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_nvm_defrag_output (size:128b/16B) */
+struct hwrm_nvm_defrag_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */
+struct hwrm_nvm_defrag_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* NVM defragmentation could not be performed */
+ #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \
+ HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL
+ uint8_t unused_0[7];
+} __rte_packed;
+
/****************
* hwrm_oem_cmd *
****************/
@@ -1010,13 +1010,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init)
* pointer, otherwise allocate a new session.
*/
static struct bnxt_ulp_session_state *
-ulp_get_session(struct rte_pci_addr *pci_addr)
+ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr)
{
struct bnxt_ulp_session_state *session;
+ /* if multi root capability is enabled, then ignore the pci bus id */
STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) {
if (session->pci_info.domain == pci_addr->domain &&
- session->pci_info.bus == pci_addr->bus) {
+ (BNXT_MULTIROOT_EN(bp) ||
+ session->pci_info.bus == pci_addr->bus)) {
return session;
}
}
@@ -1044,7 +1046,7 @@ ulp_session_init(struct bnxt *bp,
pthread_mutex_lock(&bnxt_ulp_global_mutex);
- session = ulp_get_session(pci_addr);
+ session = ulp_get_session(bp, pci_addr);
if (!session) {
/* Not Found the session Allocate a new one */
session = rte_zmalloc("bnxt_ulp_session",
@@ -1547,7 +1549,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device);
pci_addr = &pci_dev->addr;
pthread_mutex_lock(&bnxt_ulp_global_mutex);
- session = ulp_get_session(pci_addr);
+ session = ulp_get_session(bp, pci_addr);
pthread_mutex_unlock(&bnxt_ulp_global_mutex);
/* session not found then just exit */