diff mbox series

[v2] crypto/qat: fix gen3 legacy capabilities

Message ID 20231115161413.2520429-1-ciara.power@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series [v2] crypto/qat: fix gen3 legacy capabilities |

Checks

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ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/github-robot: build success github build: passed
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ci/iol-intel-Performance success Performance Testing PASS
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ci/iol-intel-Functional success Functional Testing PASS
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ci/iol-unit-arm64-testing success Testing PASS
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ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS

Commit Message

Power, Ciara Nov. 15, 2023, 4:14 p.m. UTC 
  When the legacy capability flag was enabled for QAT GEN3,
in the case of the last legacy capability in the list being SM3 or SM4,
when no slice is on the device, the loop continues instead of checking
if the end of the legacy capbilities list has been met.

To fix this, the check for the end of the legacy capabilities list is
moved to the top of the loop, so it is detected when the last legacy
element is SM and no SM slice exists.

Fixes: cffb726b7797 ("crypto/qat: enable insecure algorithms")
Cc: stable@dpdk.org

Signed-off-by: Ciara Power <ciara.power@intel.com>

---
v2: updating sender email
---
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Ji, Kai Nov. 15, 2023, 4:42 p.m. UTC | #1 
Acked-by: Kai Ji <kai.ji@intel.com>
Akhil Goyal Nov. 16, 2023, 5:53 p.m. UTC | #2 
> When the legacy capability flag was enabled for QAT GEN3,
> in the case of the last legacy capability in the list being SM3 or SM4,
> when no slice is on the device, the loop continues instead of checking
> if the end of the legacy capbilities list has been met.
> 
> To fix this, the check for the end of the legacy capabilities list is
> moved to the top of the loop, so it is detected when the last legacy
> element is SM and no SM slice exists.
> 
> Fixes: cffb726b7797 ("crypto/qat: enable insecure algorithms")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>
Applied to dpdk-next-crypto
Thanks.
diff mbox series

Patch

diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 0a939161f9..150f77ab0c 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -232,6 +232,13 @@  qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,
 	}
 
 	for (i = 0; i < capa_num; i++, iter++) {
+		if (unlikely(qat_legacy_capa) && (i == legacy_capa_num)) {
+			capabilities = qat_sym_crypto_caps_gen3;
+			addr += curr_capa;
+			curr_capa = 0;
+			iter = 0;
+		}
+
 		if (slice_map & ICP_ACCEL_MASK_SM4_SLICE && (
 			check_cipher_capa(&capabilities[iter],
 				RTE_CRYPTO_CIPHER_SM4_ECB) ||
@@ -249,13 +256,6 @@  qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,
 		memcpy(addr + curr_capa, capabilities + iter,
 			sizeof(struct rte_cryptodev_capabilities));
 		curr_capa++;
-
-		if (unlikely(qat_legacy_capa) && (i == legacy_capa_num-1)) {
-			capabilities = qat_sym_crypto_caps_gen3;
-			addr += curr_capa;
-			curr_capa = 0;
-			iter = -1;
-		}
 	}
 	internals->qat_dev_capabilities = internals->capa_mz->addr;