Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
---
drivers/dma/idxd/idxd_hw_defs.h | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
@@ -26,7 +26,7 @@ enum rte_idxd_ops {
* Hardware descriptor used by DSA hardware, for both bursts and
* for individual operations.
*/
-struct idxd_hw_desc {
+struct __rte_aligned(64) idxd_hw_desc {
uint32_t pasid;
uint32_t op_flags;
rte_iova_t completion;
@@ -43,7 +43,7 @@ struct idxd_hw_desc {
/* remaining 26 bytes are reserved */
uint16_t reserved[13];
-} __rte_aligned(64);
+};
#define IDXD_COMP_STATUS_INCOMPLETE 0
#define IDXD_COMP_STATUS_SUCCESS 1
@@ -55,7 +55,7 @@ struct idxd_hw_desc {
/**
* Completion record structure written back by DSA
*/
-struct idxd_completion {
+struct __rte_aligned(32) idxd_completion {
uint8_t status;
uint8_t result;
/* 16-bits pad here */
@@ -63,7 +63,7 @@ struct idxd_completion {
rte_iova_t fault_address;
uint32_t invalid_flags;
-} __rte_aligned(32);
+};
/*** Definitions for Intel(R) Data Streaming Accelerator ***/
@@ -83,20 +83,20 @@ enum rte_idxd_cmds {
/* General bar0 registers */
struct rte_idxd_bar0 {
- uint32_t __rte_cache_aligned version; /* offset 0x00 */
- uint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */
- uint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */
- uint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */
- uint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */
- uint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */
- uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */
- uint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */
- uint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */
- uint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */
- uint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */
- uint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */
- uint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */
- uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */
+ alignas(RTE_CACHE_LINE_SIZE) uint32_t version; /* offset 0x00 */
+ alignas(0x10) uint64_t gencap; /* offset 0x10 */
+ alignas(0x10) uint64_t wqcap; /* offset 0x20 */
+ alignas(0x10) uint64_t grpcap; /* offset 0x30 */
+ alignas(0x08) uint64_t engcap; /* offset 0x38 */
+ alignas(0x10) uint64_t opcap; /* offset 0x40 */
+ alignas(0x20) uint64_t offsets[2]; /* offset 0x60 */
+ alignas(0x20) uint32_t gencfg; /* offset 0x80 */
+ alignas(0x08) uint32_t genctrl; /* offset 0x88 */
+ alignas(0x10) uint32_t gensts; /* offset 0x90 */
+ alignas(0x08) uint32_t intcause; /* offset 0x98 */
+ alignas(0x10) uint32_t cmd; /* offset 0xA0 */
+ alignas(0x08) uint32_t cmdstatus; /* offset 0xA8 */
+ alignas(0x20) uint64_t swerror[4]; /* offset 0xC0 */
};
/* workqueue config is provided by array of uint32_t. */
@@ -118,7 +118,7 @@ enum rte_idxd_wqcfg {
#define WQ_STATE_MASK 0x3
struct rte_idxd_grpcfg {
- uint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t grpwqcfg[4]; /* 64-byte register set */
uint64_t grpengcfg; /* offset 32 */
uint32_t grpflags; /* offset 40 */
};