diff mbox series

[44/83] event/dsw: move alignment attribute on types

Message ID 1710949096-5786-45-git-send-email-roretzla@linux.microsoft.com (mailing list archive)
State Superseded
Delegated to: David Marchand
Headers
Series move alignment attribute on types |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tyler Retzlaff March 20, 2024, 3:37 p.m. UTC 
  Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
---
 drivers/event/dsw/dsw_evdev.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/event/dsw/dsw_evdev.h b/drivers/event/dsw/dsw_evdev.h
index d745c89..3a5989f 100644
--- a/drivers/event/dsw/dsw_evdev.h
+++ b/drivers/event/dsw/dsw_evdev.h
@@ -131,7 +131,7 @@  enum dsw_migration_state {
 	DSW_MIGRATION_STATE_UNPAUSING
 };
 
-struct dsw_port {
+struct __rte_cache_aligned dsw_port {
 	uint16_t id;
 
 	/* Keeping a pointer here to avoid container_of() calls, which
@@ -222,22 +222,22 @@  struct dsw_port {
 	 */
 	struct rte_event in_buffer[DSW_MAX_EVENTS];
 
-	struct rte_event_ring *in_ring __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) struct rte_event_ring *in_ring;
 
-	struct rte_ring *ctl_in_ring __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) struct rte_ring *ctl_in_ring;
 
 	/* Estimate of current port load. */
-	int16_t load __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) int16_t load;
 	/* Estimate of flows currently migrating to this port. */
-	int32_t immigration_load __rte_cache_aligned;
-} __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) int32_t immigration_load;
+};
 
 struct dsw_queue {
 	uint8_t schedule_type;
 	uint64_t serving_ports;
 	uint16_t num_serving_ports;
 
-	uint8_t flow_to_port_map[DSW_MAX_FLOWS] __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) uint8_t flow_to_port_map[DSW_MAX_FLOWS];
 };
 
 /* Limited by the size of the 'serving_ports' bitmask */
@@ -252,19 +252,19 @@  struct dsw_evdev {
 	uint8_t num_queues;
 	int32_t max_inflight;
 
-	int32_t credits_on_loan __rte_cache_aligned;
+	alignas(RTE_CACHE_LINE_SIZE) int32_t credits_on_loan;
 };
 
 #define DSW_CTL_PAUS_REQ (0)
 #define DSW_CTL_UNPAUS_REQ (1)
 #define DSW_CTL_CFM (2)
 
-struct dsw_ctl_msg {
+struct __rte_aligned(4) dsw_ctl_msg {
 	uint8_t type;
 	uint8_t originating_port_id;
 	uint8_t qfs_len;
 	struct dsw_queue_flow qfs[DSW_MAX_FLOWS_PER_MIGRATION];
-} __rte_aligned(4);
+};
 
 uint16_t dsw_event_enqueue(void *port, const struct rte_event *event);
 uint16_t dsw_event_enqueue_burst(void *port,