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GET /api/patches/99050/?format=api
{ "id": 99050, "url": "https://patches.dpdk.org/api/patches/99050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210917013923.4004-2-alvinx.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210917013923.4004-2-alvinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210917013923.4004-2-alvinx.zhang@intel.com", "date": "2021-09-17T01:39:23", "name": "[v2,2/2] app/testpmd: fix txonly forwording", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "94bb0b3e9fb3afac55007a4080e4ef8bba52b4a6", "submitter": { "id": 1398, "url": "https://patches.dpdk.org/api/people/1398/?format=api", "name": "Alvin Zhang", "email": "alvinx.zhang@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210917013923.4004-2-alvinx.zhang@intel.com/mbox/", "series": [ { "id": 18989, "url": "https://patches.dpdk.org/api/series/18989/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18989", "date": "2021-09-17T01:39:22", "name": "[v2,1/2] app/testpmd: update forward engine beginning", "version": 2, "mbox": "https://patches.dpdk.org/series/18989/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/99050/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/99050/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C1BF6A0C43;\n\tFri, 17 Sep 2021 03:39:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 31CDC410EC;\n\tFri, 17 Sep 2021 03:39:36 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 4D63440689;\n Fri, 17 Sep 2021 03:39:33 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Sep 2021 18:39:32 -0700", "from shwdenpg235.ccr.corp.intel.com ([10.253.106.22])\n by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Sep 2021 18:39:30 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10109\"; a=\"202859063\"", "E=Sophos;i=\"5.85,299,1624345200\"; d=\"scan'208\";a=\"202859063\"", "E=Sophos;i=\"5.85,299,1624345200\"; d=\"scan'208\";a=\"453134082\"" ], "From": "Alvin Zhang <alvinx.zhang@intel.com>", "To": "xiaoyun.li@intel.com,\n\tkonstantin.ananyev@intel.com", "Cc": "dev@dpdk.org,\n\tAlvin Zhang <alvinx.zhang@intel.com>,\n\tstable@dpdk.org", "Date": "Fri, 17 Sep 2021 09:39:23 +0800", "Message-Id": "<20210917013923.4004-2-alvinx.zhang@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20210917013923.4004-1-alvinx.zhang@intel.com>", "References": "<20210902082013.7704-1-alvinx.zhang@intel.com>\n <20210917013923.4004-1-alvinx.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 2/2] app/testpmd: fix txonly forwording", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When random number of Tx segments is enabled, because the actual\nnumber of segments may be only one, the first segment of the Tx\npackets must accommodate a complete being sending Eth/IP/UDP packet.\n\nBesides, if multiple flow is enabled, the forwarding will update\nthe IP and UDP header, these headers shouldn't cross segments.\nThis also requires the first Tx segment can accommodate a complete\nEth/IP/UDP packet.\n\nIn addition, if time stamp is enabled, the forwarding need more\nTx segment space for time stamp information.\n\nThis patch adds checks in beginning of forward engine to make sure\nall above conditions are meet.\n\nBugzilla ID: 797\nFixes: 79bec05b32b7 (\"app/testpmd: add ability to split outgoing packets\")\nCc: stable@dpdk.org\n\nSigned-off-by: Alvin Zhang <alvinx.zhang@intel.com>\n---\n app/test-pmd/txonly.c | 67 ++++++++++++++++++++++++++++++++++++++++++---------\n 1 file changed, 55 insertions(+), 12 deletions(-)", "diff": "diff --git a/app/test-pmd/txonly.c b/app/test-pmd/txonly.c\nindex 386a4ff..40f4075 100644\n--- a/app/test-pmd/txonly.c\n+++ b/app/test-pmd/txonly.c\n@@ -40,6 +40,13 @@\n \n #include \"testpmd.h\"\n \n+struct tx_timestamp {\n+\trte_be32_t signature;\n+\trte_be16_t pkt_idx;\n+\trte_be16_t queue_idx;\n+\trte_be64_t ts;\n+};\n+\n /* use RFC863 Discard Protocol */\n uint16_t tx_udp_src_port = 9;\n uint16_t tx_udp_dst_port = 9;\n@@ -257,12 +264,7 @@\n \n \tif (unlikely(timestamp_enable)) {\n \t\tuint64_t skew = RTE_PER_LCORE(timestamp_qskew);\n-\t\tstruct {\n-\t\t\trte_be32_t signature;\n-\t\t\trte_be16_t pkt_idx;\n-\t\t\trte_be16_t queue_idx;\n-\t\t\trte_be64_t ts;\n-\t\t} timestamp_mark;\n+\t\tstruct tx_timestamp timestamp_mark;\n \n \t\tif (unlikely(timestamp_init_req !=\n \t\t\t\tRTE_PER_LCORE(timestamp_idone))) {\n@@ -438,13 +440,23 @@\n static int\n tx_only_begin(portid_t pi)\n {\n-\tuint16_t pkt_data_len;\n+\tuint16_t pkt_hdr_len, pkt_data_len;\n \tint dynf;\n \n-\tpkt_data_len = (uint16_t) (tx_pkt_length - (\n-\t\t\t\t\tsizeof(struct rte_ether_hdr) +\n-\t\t\t\t\tsizeof(struct rte_ipv4_hdr) +\n-\t\t\t\t\tsizeof(struct rte_udp_hdr)));\n+\tpkt_hdr_len = (uint16_t)(sizeof(struct rte_ether_hdr) +\n+\t\t\t\t sizeof(struct rte_ipv4_hdr) +\n+\t\t\t\t sizeof(struct rte_udp_hdr));\n+\tpkt_data_len = tx_pkt_length - pkt_hdr_len;\n+\n+\tif ((tx_pkt_split == TX_PKT_SPLIT_RND || txonly_multi_flow) &&\n+\t tx_pkt_seg_lengths[0] < pkt_hdr_len) {\n+\t\tTESTPMD_LOG(ERR,\n+\t\t\t \"Random segment number or multiple flow enabled,\"\n+\t\t\t \" but tx_pkt_seg_lengths[0] %u < %u (needed)\\n\",\n+\t\t\t tx_pkt_seg_lengths[0], pkt_hdr_len);\n+\t\treturn -EINVAL;\n+\t}\n+\n \tsetup_pkt_udp_ip_headers(&pkt_ip_hdr, &pkt_udp_hdr, pkt_data_len);\n \n \ttimestamp_enable = false;\n@@ -463,8 +475,39 @@\n \t\t\t timestamp_mask &&\n \t\t\t timestamp_off >= 0 &&\n \t\t\t !rte_eth_read_clock(pi, ×tamp_initial[pi]);\n-\tif (timestamp_enable)\n+\n+\tif (timestamp_enable) {\n+\t\tpkt_hdr_len += sizeof(struct timestamp);\n+\n+\t\tif (tx_pkt_split == TX_PKT_SPLIT_RND) {\n+\t\t\tif (tx_pkt_seg_lengths[0] < pkt_hdr_len) {\n+\t\t\t\tTESTPMD_LOG(ERR,\n+\t\t\t\t\t \"Time stamp and random segment number enabled,\"\n+\t\t\t\t\t \" but tx_pkt_seg_lengths[0] %u < %u (needed)\\n\",\n+\t\t\t\t\t tx_pkt_seg_lengths[0], pkt_hdr_len);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tuint16_t total = 0;\n+\t\t\tuint8_t i;\n+\n+\t\t\tfor (i = 0; i < tx_pkt_nb_segs; i++) {\n+\t\t\t\ttotal += tx_pkt_seg_lengths[i];\n+\t\t\t\tif (total >= pkt_hdr_len)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (total < pkt_hdr_len) {\n+\t\t\t\tTESTPMD_LOG(ERR,\n+\t\t\t\t\t \"No enough Tx segment space for time stamp info.\"\n+\t\t\t\t\t \" total %u < %u (needed)\\n\",\n+\t\t\t\t\t total, pkt_hdr_len);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t}\n \t\ttimestamp_init_req++;\n+\t}\n+\n \t/* Make sure all settings are visible on forwarding cores.*/\n \trte_wmb();\n \treturn 0;\n", "prefixes": [ "v2", "2/2" ] }