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GET /api/patches/97533/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 97533,
    "url": "https://patches.dpdk.org/api/patches/97533/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210830075647.3011046-1-yuying.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210830075647.3011046-1-yuying.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210830075647.3011046-1-yuying.zhang@intel.com",
    "date": "2021-08-30T07:56:46",
    "name": "[RFC,1/2] net/ice/base: support drop any and steer all to queue",
    "commit_ref": null,
    "pull_url": null,
    "state": "rfc",
    "archived": true,
    "hash": "63058730594561c45056b81504b94c48eadbf4d4",
    "submitter": {
        "id": 1844,
        "url": "https://patches.dpdk.org/api/people/1844/?format=api",
        "name": "Zhang, Yuying",
        "email": "yuying.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210830075647.3011046-1-yuying.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 18521,
            "url": "https://patches.dpdk.org/api/series/18521/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18521",
            "date": "2021-08-30T07:56:46",
            "name": "[RFC,1/2] net/ice/base: support drop any and steer all to queue",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/18521/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/97533/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/97533/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7C250A034F;\n\tMon, 30 Aug 2021 10:13:44 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 01A744111E;\n\tMon, 30 Aug 2021 10:13:44 +0200 (CEST)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id BE080410FA\n for <dev@dpdk.org>; Mon, 30 Aug 2021 10:13:42 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Aug 2021 01:13:41 -0700",
            "from dpdk-yyzhang2.sh.intel.com ([10.67.117.158])\n by fmsmga002.fm.intel.com with ESMTP; 30 Aug 2021 01:13:39 -0700"
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10091\"; a=\"218272766\"",
            "E=Sophos;i=\"5.84,362,1620716400\"; d=\"scan'208\";a=\"218272766\"",
            "E=Sophos;i=\"5.84,362,1620716400\"; d=\"scan'208\";a=\"540244819\""
        ],
        "X-ExtLoop1": "1",
        "From": "Yuying Zhang <yuying.zhang@intel.com>",
        "To": "dev@dpdk.org,\n\tqi.z.zhang@intel.com",
        "Cc": "Yuying Zhang <yuying.zhang@intel.com>",
        "Date": "Mon, 30 Aug 2021 07:56:46 +0000",
        "Message-Id": "<20210830075647.3011046-1-yuying.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH RFC 1/2] net/ice/base: support drop any and steer\n all to queue",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch supports drop any and steer all to queue in switch\nfilter.\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c     | 73 +++++++++++++++---------\n drivers/net/ice/base/ice_flex_pipe.h     |  5 +-\n drivers/net/ice/base/ice_flex_type.h     |  1 +\n drivers/net/ice/base/ice_protocol_type.h |  3 +-\n drivers/net/ice/base/ice_switch.c        | 39 +++++++------\n 5 files changed, 73 insertions(+), 48 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex cf470bc4f0..2ebef279a0 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -1711,23 +1711,30 @@ static enum ice_prof_type\n ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv)\n {\n \tu16 i;\n+\tbool is_any = false;\n \n \tfor (i = 0; i < hw->blk[ICE_BLK_SW].es.fvw; i++) {\n+\t\tif (fv->ew[i].off != ICE_NAN_OFFSET)\n+\t\t\tis_any = true;\n+\n \t\t/* UDP tunnel will have UDP_OF protocol ID and VNI offset */\n \t\tif (fv->ew[i].prot_id == (u8)ICE_PROT_UDP_OF &&\n \t\t    fv->ew[i].off == ICE_VNI_OFFSET)\n-\t\t\treturn ICE_PROF_TUN_UDP;\n+\t\t\treturn ICE_PROF_TUN_UDP | ICE_PROF_ANY;\n \n \t\t/* GRE tunnel will have GRE protocol */\n \t\tif (fv->ew[i].prot_id == (u8)ICE_PROT_GRE_OF)\n-\t\t\treturn ICE_PROF_TUN_GRE;\n+\t\t\treturn ICE_PROF_TUN_GRE | ICE_PROF_ANY;\n \n \t\t/* PPPOE tunnel will have PPPOE protocol */\n \t\tif (fv->ew[i].prot_id == (u8)ICE_PROT_PPPOE)\n-\t\t\treturn ICE_PROF_TUN_PPPOE;\n+\t\t\treturn ICE_PROF_TUN_PPPOE | ICE_PROF_ANY;\n \t}\n \n-\treturn ICE_PROF_NON_TUN;\n+\tif (is_any)\n+\t\treturn ICE_PROF_NON_TUN | ICE_PROF_ANY;\n+\telse\n+\t\treturn ICE_PROF_NON_TUN;\n }\n \n /**\n@@ -1764,7 +1771,6 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs,\n \t\tif (fv) {\n \t\t\t/* Determine field vector type */\n \t\t\tprof_type = ice_get_sw_prof_type(hw, fv);\n-\n \t\t\tif (req_profs & prof_type)\n \t\t\t\tice_set_bit((u16)offset, bm);\n \t\t}\n@@ -1787,8 +1793,9 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs,\n  * allocated for every list entry.\n  */\n enum ice_status\n-ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt,\n-\t\t   ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)\n+ice_get_sw_fv_list(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,\n+\t\t   u8 *prot_ids, u16 ids_cnt, ice_bitmap_t *bm,\n+\t\t   struct LIST_HEAD_TYPE *fv_list)\n {\n \tstruct ice_sw_fv_list_entry *fvl;\n \tstruct ice_sw_fv_list_entry *tmp;\n@@ -1799,7 +1806,7 @@ ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt,\n \n \tice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM);\n \n-\tif (!ids_cnt || !hw->seg)\n+\tif (tun_type != ICE_ANY && (!ids_cnt || !hw->seg))\n \t\treturn ICE_ERR_PARAM;\n \n \tice_seg = hw->seg;\n@@ -1819,28 +1826,38 @@ ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt,\n \t\tif (!ice_is_bit_set(bm, (u16)offset))\n \t\t\tcontinue;\n \n-\t\tfor (i = 0; i < ids_cnt; i++) {\n-\t\t\tint j;\n+\t\tif (tun_type == ICE_ANY) {\n+\t\t\tfvl = (struct ice_sw_fv_list_entry *)\n+\t\t\t       ice_malloc(hw, sizeof(*fvl));\n+\t\t\tif (!fvl)\n+\t\t\t\tgoto err;\n+\t\t\tfvl->fv_ptr = fv;\n+\t\t\tfvl->profile_id = offset;\n+\t\t\tLIST_ADD(&fvl->list_entry, fv_list);\n+\t\t} else {\n+\t\t\tfor (i = 0; i < ids_cnt; i++) {\n+\t\t\t\tint j;\n \n-\t\t\t/* This code assumes that if a switch field vector line\n-\t\t\t * has a matching protocol, then this line will contain\n-\t\t\t * the entries necessary to represent every field in\n-\t\t\t * that protocol header.\n-\t\t\t */\n-\t\t\tfor (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++)\n-\t\t\t\tif (fv->ew[j].prot_id == prot_ids[i])\n+\t\t\t\t/* This code assumes that if a switch field vector\n+\t\t\t\t * line has a matching protocol, then this line\n+\t\t\t\t * will contain the entries necessary to represent\n+\t\t\t\t * every field in that protocol header.\n+\t\t\t\t */\n+\t\t\t\tfor (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++)\n+\t\t\t\t\tif (fv->ew[j].prot_id == prot_ids[i])\n+\t\t\t\t\t\tbreak;\n+\t\t\t\tif (j >= hw->blk[ICE_BLK_SW].es.fvw)\n \t\t\t\t\tbreak;\n-\t\t\tif (j >= hw->blk[ICE_BLK_SW].es.fvw)\n-\t\t\t\tbreak;\n-\t\t\tif (i + 1 == ids_cnt) {\n-\t\t\t\tfvl = (struct ice_sw_fv_list_entry *)\n-\t\t\t\t\tice_malloc(hw, sizeof(*fvl));\n-\t\t\t\tif (!fvl)\n-\t\t\t\t\tgoto err;\n-\t\t\t\tfvl->fv_ptr = fv;\n-\t\t\t\tfvl->profile_id = offset;\n-\t\t\t\tLIST_ADD(&fvl->list_entry, fv_list);\n-\t\t\t\tbreak;\n+\t\t\t\tif (i + 1 == ids_cnt) {\n+\t\t\t\t\tfvl = (struct ice_sw_fv_list_entry *)\n+\t\t\t\t\t\tice_malloc(hw, sizeof(*fvl));\n+\t\t\t\t\tif (!fvl)\n+\t\t\t\t\t\tgoto err;\n+\t\t\t\t\tfvl->fv_ptr = fv;\n+\t\t\t\t\tfvl->profile_id = offset;\n+\t\t\t\t\tLIST_ADD(&fvl->list_entry, fv_list);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n \t\t\t}\n \t\t}\n \t} while (fv);\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nindex 58e3c1d1ec..ca9b216f69 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.h\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -36,8 +36,9 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,\n void\n ice_init_prof_result_bm(struct ice_hw *hw);\n enum ice_status\n-ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt,\n-\t\t   ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);\n+ice_get_sw_fv_list(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,\n+\t\t   u8 *prot_ids, u16 ids_cnt, ice_bitmap_t *bm,\n+\t\t   struct LIST_HEAD_TYPE *fv_list);\n enum ice_status\n ice_pkg_buf_unreserve_section(struct ice_buf_build *bld, u16 count);\n u16 ice_pkg_buf_get_free_space(struct ice_buf_build *bld);\ndiff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h\nindex c7f92b9150..b63b984688 100644\n--- a/drivers/net/ice/base/ice_flex_type.h\n+++ b/drivers/net/ice/base/ice_flex_type.h\n@@ -916,6 +916,7 @@ enum ice_prof_type {\n \tICE_PROF_TUN_GRE = 0x4,\n \tICE_PROF_TUN_PPPOE = 0x8,\n \tICE_PROF_TUN_ALL = 0xE,\n+\tICE_PROF_ANY = 0x10,\n \tICE_PROF_ALL = 0xFF,\n };\n \ndiff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h\nindex d769ad0580..0a8c39b369 100644\n--- a/drivers/net/ice/base/ice_protocol_type.h\n+++ b/drivers/net/ice/base/ice_protocol_type.h\n@@ -109,6 +109,7 @@ enum ice_sw_tunnel_type {\n \tICE_SW_TUN_PPPOE_PAY_QINQ,\n \tICE_SW_TUN_PPPOE_IPV4_QINQ,\n \tICE_SW_TUN_PPPOE_IPV6_QINQ,\n+\tICE_ANY,\n \tICE_ALL_TUNNELS /* All tunnel types including NVGRE */\n };\n \n@@ -164,7 +165,7 @@ enum ice_prot_id {\n };\n \n #define ICE_VNI_OFFSET\t\t12 /* offset of VNI from ICE_PROT_UDP_OF */\n-\n+#define ICE_NAN_OFFSET\t\t511\n #define ICE_MAC_OFOS_HW\t\t1\n #define ICE_MAC_IL_HW\t\t4\n #define ICE_ETYPE_OL_HW\t\t9\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 4568242c10..4bf9761909 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -7235,19 +7235,22 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,\n  * @fv_list: pointer to a list that holds the returned field vectors\n  */\n static enum ice_status\n-ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n+ice_get_fv(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,\n+\t   struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t   ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)\n {\n \tenum ice_status status;\n \tu8 *prot_ids;\n \tu16 i;\n \n-\tif (!lkups_cnt)\n+\tif (!lkups_cnt && tun_type != ICE_ANY)\n \t\treturn ICE_SUCCESS;\n \n-\tprot_ids = (u8 *)ice_calloc(hw, lkups_cnt, sizeof(*prot_ids));\n-\tif (!prot_ids)\n-\t\treturn ICE_ERR_NO_MEMORY;\n+\tif (lkups_cnt) {\n+\t\tprot_ids = (u8 *)ice_calloc(hw, lkups_cnt, sizeof(*prot_ids));\n+\t\tif (!prot_ids)\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t}\n \n \tfor (i = 0; i < lkups_cnt; i++)\n \t\tif (!ice_prot_type_to_id(lkups[i].type, &prot_ids[i])) {\n@@ -7256,10 +7259,12 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t\t}\n \n \t/* Find field vectors that include all specified protocol types */\n-\tstatus = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, bm, fv_list);\n+\tstatus = ice_get_sw_fv_list(hw, tun_type, prot_ids,\n+\t\t\t\t    lkups_cnt, bm, fv_list);\n \n free_mem:\n-\tice_free(hw, prot_ids);\n+\tif (lkups_cnt)\n+\t\tice_free(hw, prot_ids);\n \treturn status;\n }\n \n@@ -7340,6 +7345,9 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n \tice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES);\n \n \tswitch (rinfo->tun_type) {\n+\tcase ICE_ANY:\n+\t\tprof_type = ICE_PROF_ANY;\n+\t\tbreak;\n \tcase ICE_NON_TUN:\n \tcase ICE_NON_TUN_QINQ:\n \t\tprof_type = ICE_PROF_NON_TUN;\n@@ -7495,6 +7503,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,\n bool ice_is_prof_rule(enum ice_sw_tunnel_type type)\n {\n \tswitch (type) {\n+\tcase ICE_ANY:\n \tcase ICE_SW_TUN_PROFID_IPV6_ESP:\n \tcase ICE_SW_TUN_PROFID_IPV6_AH:\n \tcase ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3:\n@@ -7579,7 +7588,8 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t */\n \tice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap);\n \n-\tstatus = ice_get_fv(hw, lkups, lkups_cnt, fv_bitmap, &rm->fv_list);\n+\tstatus = ice_get_fv(hw, rinfo->tun_type, lkups, lkups_cnt,\n+\t\t\t    fv_bitmap, &rm->fv_list);\n \tif (status)\n \t\tgoto err_unroll;\n \n@@ -8314,15 +8324,10 @@ ice_adv_add_update_vsi_list(struct ice_hw *hw,\n \tenum ice_status status;\n \tu16 vsi_list_id = 0;\n \n-\tif (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_Q ||\n-\t    cur_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP ||\n-\t    cur_fltr->sw_act.fltr_act == ICE_DROP_PACKET)\n-\t\treturn ICE_ERR_NOT_IMPL;\n-\n-\tif ((new_fltr->sw_act.fltr_act == ICE_FWD_TO_Q ||\n-\t     new_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP) &&\n-\t    (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_VSI ||\n-\t     cur_fltr->sw_act.fltr_act == ICE_FWD_TO_VSI_LIST))\n+\tif ((cur_fltr->sw_act.fltr_act != ICE_FWD_TO_VSI &&\n+\t     cur_fltr->sw_act.fltr_act != ICE_FWD_TO_VSI_LIST) ||\n+\t    (new_fltr->sw_act.fltr_act != ICE_FWD_TO_VSI &&\n+\t     new_fltr->sw_act.fltr_act != ICE_FWD_TO_VSI_LIST))\n \t\treturn ICE_ERR_NOT_IMPL;\n \n \tif (m_entry->vsi_count < 2 && !m_entry->vsi_list_info) {\n",
    "prefixes": [
        "RFC",
        "1/2"
    ]
}