Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/96834/?format=api
{ "id": 96834, "url": "https://patches.dpdk.org/api/patches/96834/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210812071244.28799-13-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210812071244.28799-13-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210812071244.28799-13-hemant.agrawal@nxp.com", "date": "2021-08-12T07:12:40", "name": "[RFC,12/16] crypto/dpaa_sec: support raw datapath APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "483e05948970d55f27c57d58c06d5481df472f1b", "submitter": { "id": 477, "url": "https://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210812071244.28799-13-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 18259, "url": "https://patches.dpdk.org/api/series/18259/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18259", "date": "2021-08-12T07:12:28", "name": "crypto: add raw vector support in DPAAx", "version": 1, "mbox": "https://patches.dpdk.org/series/18259/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/96834/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/96834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BADDEA0C52;\n\tThu, 12 Aug 2021 09:17:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 09D1C41256;\n\tThu, 12 Aug 2021 09:16:28 +0200 (CEST)", "from EUR02-VE1-obe.outbound.protection.outlook.com\n (mail-eopbgr20054.outbound.protection.outlook.com [40.107.2.54])\n by mails.dpdk.org (Postfix) with ESMTP id E18434124E\n for <dev@dpdk.org>; Thu, 12 Aug 2021 09:16:26 +0200 (CEST)", "from DU2PR04MB8630.eurprd04.prod.outlook.com (2603:10a6:10:2dd::15)\n by DB9PR04MB8461.eurprd04.prod.outlook.com (2603:10a6:10:2bc::7) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.13; Thu, 12 Aug\n 2021 07:16:25 +0000", "from DU2PR04MB8630.eurprd04.prod.outlook.com\n ([fe80::2590:514a:df1f:a793]) by DU2PR04MB8630.eurprd04.prod.outlook.com\n ([fe80::2590:514a:df1f:a793%9]) with mapi id 15.20.4415.016; Thu, 12 Aug 2021\n 07:16:25 +0000", "from dpdk-xeon.ap.freescale.net (92.120.0.67) by\n SG2PR02CA0105.apcprd02.prod.outlook.com (2603:1096:4:92::21) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4415.14 via Frontend Transport; Thu, 12 Aug 2021 07:16:24 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=BkwOqsRTjCs7wwhK+BS/R/wFlYunInXaqx1b2cnlAijKIY5vbK6cB3kxF2N4t5ytBB0CCJwfeDSBWujwLiEpzdGnAmDvhLvo21YGHh1XEcd08bzrwWa4CAKLf2RmT/9yi8xYZGZXKOqANZ7ItH4qM+RsHFRpc5LodM6thF83sn9k453XsuaaJ9EgdxqeToBEmYyaOrODPTpeT4lzdo9OWf83lV88MkK6VbYwGEhj9qINlbFu1+8iSXE/TZTgBSHXiTVd97wSeiuLC5csJUdPOdCbt6jvgLvRXxtF0RVNxc0ads3CLuL5ueb/tHN27JwEMxwzMUZrlrTCjCLDzAoFqQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=YGmrYm6JLfyDoN5NMvf40kDmDwYB/q3XaawwAGhd1ZA=;\n b=HO6vas7uSSoOYhKWaR48tbPDuJaOqOQbmCH1xbjvZqKuz7gnEj/hCXUuTPzu5ECOnrtx0bti8BrI60n8VkTXhO7GAwYw+G7c5gY/1jkUtG7ZtZ3IeEaVvoAQzPVhfWph5ddu1K46+KORf3Ytf5PiH1GNOVg2ZJ7Rr3Bi7LLK7aw9pNw87sCy2iZGPSzJJEqcECs9yYNEhi2V8KHylFG9BX6h4baw8DhIzTvPQIEzOmnZWF7NlDZ/VnM9Kb6Rs6a8AgheFiQGg0x55UYsVuJdGBxCbfB95dw9/w7rTi3B1rzjTdvYuZKzZRO1BMU4ts7k5/NosLfrE6v+uIXMmP2u+w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=YGmrYm6JLfyDoN5NMvf40kDmDwYB/q3XaawwAGhd1ZA=;\n b=hbdGcbqAhNTcToNoNrI8zaCq69p//HutMbWWel4By7ckABPySZao+Hp92NA9LSx5qMpgILI/VuvrQs1pVxs0z1dwYw5N6r28c773Hmbi4L38gbQKpR3v8wPtfxf5AhnPYRIxb9atHgAez+FNHhWhTpGvJj//wiTu9dauNObMlgg=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=nxp.com;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com", "Cc": "Gagandeep Singh <g.singh@nxp.com>", "Date": "Thu, 12 Aug 2021 12:42:40 +0530", "Message-Id": "<20210812071244.28799-13-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210812071244.28799-1-hemant.agrawal@nxp.com>", "References": "<20210812071244.28799-1-hemant.agrawal@nxp.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR02CA0105.apcprd02.prod.outlook.com\n (2603:1096:4:92::21) To DU2PR04MB8630.eurprd04.prod.outlook.com\n (2603:10a6:10:2dd::15)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "541de44d-3b3e-4683-94ea-08d95d6118a4", "X-MS-TrafficTypeDiagnostic": "DB9PR04MB8461:", "X-MS-Exchange-Transport-Forked": "True", "X-Microsoft-Antispam-PRVS": "\n <DB9PR04MB84611516C9D558A287BADF7089F99@DB9PR04MB8461.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4303;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n RQInBGB9BhTgbnEiFJqjhGV/dcH8UoNmzRGxI94fBe2Fiml7swYwJ2Z8yKC4MewtTWOEQlvu2SL/z+693ovzp49/4sm2gFkb+RmIZvwA3Hvu34xVRbxAoxNynWRfbZpvMEUe7IgKE5PPWHRSLDxXXT/gMrHlQZ4lwvARp7iDhvG8o1o59rLxmxcCkdBaGz25L0Tvku1+duDmZWeLYfFpOFCHiP72gfagEyTd8m6WuXGjQW0wqPoBegKL5bTKuzE1ZyYVEfS7x8oqaa8BldLRafLXUsv+o5ZXBx196fsHYLgcPk7yLK3WQXhlWylIuhB/MSMgsXz4G7vSADrINCjlcyKyjRWGBnJXirNN5wTluGR2X02LQ0Wdfo/bwAEJpR5zgqGVor2eXRwSPo3J7KIEOhcDlqmzyEzgnHCXjWKHUBFJ+ViqXreVf75oe+mc7s770/4M0ORYmK7UMNjkrc+AQ5IhcXhWFhqtQs5WJS5En+tMpH2Xv86Zr0HPealj5G2YrUcSjlgXDYM/eQAOjLULLDwuXtfV7rjyvaG7XCmwInDD1xgfbU/wiY9hBormK5AAsfCqlAaIEhiuGBi/HP51kx8v/ef4vad/aCy9AV78LoIwmiEET5kw+/C0FiWaN3mt8tZDq7rorEbbY7PFRMCQJwmYC2JzAPj3L9fAnI/Alynh78q1WyQwZ2z1BvS0d69iNNDOmp4JJH2Pr+HpubDQsw==", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:DU2PR04MB8630.eurprd04.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(4636009)(376002)(346002)(39860400002)(396003)(136003)(366004)(30864003)(8936002)(956004)(6512007)(2616005)(2906002)(6666004)(36756003)(86362001)(4326008)(83380400001)(38350700002)(44832011)(478600001)(26005)(6506007)(66476007)(186003)(52116002)(5660300002)(1076003)(66556008)(6486002)(38100700002)(8676002)(66946007)(316002);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n 07xcimUOUJaQBIfmrK/lU3I15FJldLkY2i1rxNDrFR1MF/twC9fvtlojsJCPd8inQRUmWEVZJgiktC6OO5JMLumpQVbWPgNytBwrCKbTSBFwoU0LwRF1cMU33bzZ9dB3+LWY7CuhfASxkGfOYb6sb0Y38qX7WEYQKCc1IBOfDPS5Alsrvk4wUy1LB2cNpy3FXzp+vc68NPxe189zlgsbLyBsNvjuFIzpxHOzGAFZ+0ZqfZIwCyLyUswoBM95+VsrCQOag5wm6prxJ8JylC33LjhS1x71fNU4lhwuyFKJ5iBrg5p7IMZ9U0EBjTOlFaSeZ2PFgrzFrnmEEfRlx0CptZcKZrkmDqlvzxo4MkQQMkaNk3fUyuqXuKF10pPt3AupVD+tmRGre2Njl2WOb07iBsXC9b9d3K/Eznxk0WBPHFCcwdc+UproItW41pmaGdmiEX9hTwPXZe5f/H2ILRU7pBYZpzhxo0cPYSMUxsXMDlCVZgPOsWT3/8FEzOkOSSo2WXs7+B8sjWgWRn/YnJeOgaWDPKbPqlx9JIszrEW/Mv3JDM5as9Rfdpxs71wp2WuB21G4qxnXC/XMTI1YZtCszL8L58PuBDFLuhhWqmEYjnLHccMSLwNa0VmwQ5C1ylsu6MM5RCRSLJtOOq1OfpJpHX1g37pRLeKFf4VNwE2SedUUAih6gp5BOuHu+0OXxSmTvggn7+ZUhSsoRRj/oj2MeU1eFy9ZZLwSv/VRSpVFgmtDyNwZs2jnmDzlVJEeirK7odKUOfaOgeEorWIaOKvClUKXmKMKamX8wDUGC2sGnV44dmyX2Jhd73gnzChchO8fxBQ49DYqs/Ec4GJsBUlgG7qPrNGBi6qg/+29iFz+QsoRgCNctK2XwcHQdGaS6D2qRfM8AIgFal0kwzIZ/yGA5SDiqGNqcU8WdJQb+0yCDs4LQFF7JwWpZhzKJ1/YPyj+IjpZfTLeK8dfy5NufR8nXe75xWo8Xjs53Eke2d/RTDABUECHwdjR2PNKq7te8uh2AcRk4ODfPTR3IQj0+JkNwAy8FUsFQ5fSNgPizZfvHiYAsB9XLxyhzf34iFkAbKVrejQCCKsI749W2rlRvkAdReNfZ/MEsaHiWKuRYTz0ZFP3uRmoOtJKTMUh9GU+EeWQeDTeC0MX4ryB2fs5ESOT7J5E5yaHQ4zELPp7v2itGRXfnYFxaCV0yZooYNFeG5uKC/zMvNMYy8fNohDroudczatCZb0ooJfN40dOMHRhQmrsKzw/wFKy01KSPPvVVpSLlzmVbVW7qWEeaYYW19iDMz7t3J1q/X7yQ6jbdz2KP+FZxB4uOCmwGr/ddUhcVWEc", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 541de44d-3b3e-4683-94ea-08d95d6118a4", "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR04MB8630.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Aug 2021 07:16:25.8287 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n m5zlN+zx0k/gOnkvdvpnSO4szWDo0jQ6K40iOzDi4JFgmAgCgdgad5uh3ZKh/QfmoSDJlK0D4H7wMRaj0H8VsA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB9PR04MB8461", "Subject": "[dpdk-dev] [RFC 12/16] crypto/dpaa_sec: support raw datapath APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Gagandeep Singh <g.singh@nxp.com>\n\nThis patch add raw vector API framework for dpaa_sec driver.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/crypto/dpaa_sec/dpaa_sec.c | 23 +-\n drivers/crypto/dpaa_sec/dpaa_sec.h | 39 +-\n drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c | 485 ++++++++++++++++++++++\n drivers/crypto/dpaa_sec/meson.build | 4 +-\n 4 files changed, 537 insertions(+), 14 deletions(-)\n create mode 100644 drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c", "diff": "diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c\nindex 19d4684e24..7534f80195 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.c\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c\n@@ -45,10 +45,7 @@\n #include <dpaa_sec_log.h>\n #include <dpaax_iova_table.h>\n \n-static uint8_t cryptodev_driver_id;\n-\n-static int\n-dpaa_sec_attach_sess_q(struct dpaa_sec_qp *qp, dpaa_sec_session *sess);\n+uint8_t dpaa_cryptodev_driver_id;\n \n static inline void\n dpaa_sec_op_ending(struct dpaa_sec_op_ctx *ctx)\n@@ -1745,8 +1742,8 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\tcase RTE_CRYPTO_OP_WITH_SESSION:\n \t\t\t\tses = (dpaa_sec_session *)\n \t\t\t\t\tget_sym_session_private_data(\n-\t\t\t\t\t\t\top->sym->session,\n-\t\t\t\t\t\t\tcryptodev_driver_id);\n+\t\t\t\t\t\top->sym->session,\n+\t\t\t\t\t\tdpaa_cryptodev_driver_id);\n \t\t\t\tbreak;\n #ifdef RTE_LIB_SECURITY\n \t\t\tcase RTE_CRYPTO_OP_SECURITY_SESSION:\n@@ -2307,7 +2304,7 @@ dpaa_sec_detach_rxq(struct dpaa_sec_dev_private *qi, struct qman_fq *fq)\n \treturn -1;\n }\n \n-static int\n+int\n dpaa_sec_attach_sess_q(struct dpaa_sec_qp *qp, dpaa_sec_session *sess)\n {\n \tint ret;\n@@ -3115,7 +3112,7 @@ dpaa_sec_dev_infos_get(struct rte_cryptodev *dev,\n \t\tinfo->feature_flags = dev->feature_flags;\n \t\tinfo->capabilities = dpaa_sec_capabilities;\n \t\tinfo->sym.max_nb_sessions = internals->max_nb_sessions;\n-\t\tinfo->driver_id = cryptodev_driver_id;\n+\t\tinfo->driver_id = dpaa_cryptodev_driver_id;\n \t}\n }\n \n@@ -3311,7 +3308,10 @@ static struct rte_cryptodev_ops crypto_ops = {\n \t.queue_pair_release = dpaa_sec_queue_pair_release,\n \t.sym_session_get_size = dpaa_sec_sym_session_get_size,\n \t.sym_session_configure = dpaa_sec_sym_session_configure,\n-\t.sym_session_clear = dpaa_sec_sym_session_clear\n+\t.sym_session_clear = dpaa_sec_sym_session_clear,\n+\t/* Raw data-path API related operations */\n+\t.sym_get_raw_dp_ctx_size = dpaa_sec_get_dp_ctx_size,\n+\t.sym_configure_raw_dp_ctx = dpaa_sec_configure_raw_dp_ctx,\n };\n \n #ifdef RTE_LIB_SECURITY\n@@ -3362,7 +3362,7 @@ dpaa_sec_dev_init(struct rte_cryptodev *cryptodev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n-\tcryptodev->driver_id = cryptodev_driver_id;\n+\tcryptodev->driver_id = dpaa_cryptodev_driver_id;\n \tcryptodev->dev_ops = &crypto_ops;\n \n \tcryptodev->enqueue_burst = dpaa_sec_enqueue_burst;\n@@ -3371,6 +3371,7 @@ dpaa_sec_dev_init(struct rte_cryptodev *cryptodev)\n \t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n \t\t\tRTE_CRYPTODEV_FF_SECURITY |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_RAW_DP |\n \t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n@@ -3536,5 +3537,5 @@ static struct cryptodev_driver dpaa_sec_crypto_drv;\n \n RTE_PMD_REGISTER_DPAA(CRYPTODEV_NAME_DPAA_SEC_PMD, rte_dpaa_sec_driver);\n RTE_PMD_REGISTER_CRYPTO_DRIVER(dpaa_sec_crypto_drv, rte_dpaa_sec_driver.driver,\n-\t\tcryptodev_driver_id);\n+\t\tdpaa_cryptodev_driver_id);\n RTE_LOG_REGISTER(dpaa_logtype_sec, pmd.crypto.dpaa, NOTICE);\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec.h b/drivers/crypto/dpaa_sec/dpaa_sec.h\nindex 368699678b..f6e83d46e7 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.h\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.h\n@@ -19,6 +19,8 @@\n #define AES_CTR_IV_LEN\t\t16\n #define AES_GCM_IV_LEN\t\t12\n \n+extern uint8_t dpaa_cryptodev_driver_id;\n+\n #define DPAA_IPv6_DEFAULT_VTC_FLOW\t0x60000000\n \n /* Minimum job descriptor consists of a oneword job descriptor HEADER and\n@@ -117,6 +119,24 @@ struct sec_pdcp_ctxt {\n \tuint32_t hfn_threshold;\t/*!< HFN Threashold for key renegotiation */\n };\n #endif\n+\n+typedef int (*dpaa_sec_build_fd_t)(\n+\tvoid *qp, uint8_t *drv_ctx, struct rte_crypto_vec *data_vec,\n+\tuint16_t n_data_vecs, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad_or_auth_iv,\n+\tvoid *user_data);\n+\n+typedef struct dpaa_sec_job* (*dpaa_sec_build_raw_dp_fd_t)(uint8_t *drv_ctx,\n+\t\t\tstruct rte_crypto_sgl *sgl,\n+\t\t\tstruct rte_crypto_sgl *dest_sgl,\n+\t\t\tstruct rte_crypto_va_iova_ptr *iv,\n+\t\t\tstruct rte_crypto_va_iova_ptr *digest,\n+\t\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t\tunion rte_crypto_sym_ofs ofs,\n+\t\t\tvoid *userdata);\n+\n typedef struct dpaa_sec_session_entry {\n \tstruct sec_cdb cdb;\t/**< cmd block associated with qp */\n \tstruct dpaa_sec_qp *qp[MAX_DPAA_CORES];\n@@ -129,6 +149,8 @@ typedef struct dpaa_sec_session_entry {\n #ifdef RTE_LIB_SECURITY\n \tenum rte_security_session_protocol proto_alg; /*!< Security Algorithm*/\n #endif\n+\tdpaa_sec_build_fd_t build_fd;\n+\tdpaa_sec_build_raw_dp_fd_t build_raw_dp_fd;\n \tunion {\n \t\tstruct {\n \t\t\tuint8_t *data;\t/**< pointer to key data */\n@@ -211,7 +233,10 @@ struct dpaa_sec_job {\n #define DPAA_MAX_NB_MAX_DIGEST\t32\n struct dpaa_sec_op_ctx {\n \tstruct dpaa_sec_job job;\n-\tstruct rte_crypto_op *op;\n+\tunion {\n+\t\tstruct rte_crypto_op *op;\n+\t\tvoid *userdata;\n+\t};\n \tstruct rte_mempool *ctx_pool; /* mempool pointer for dpaa_sec_op_ctx */\n \tuint32_t fd_status;\n \tint64_t vtop_offset;\n@@ -803,4 +828,16 @@ calc_chksum(void *buffer, int len)\n \treturn result;\n }\n \n+int\n+dpaa_sec_configure_raw_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n+\tenum rte_crypto_op_sess_type sess_type,\n+\tunion rte_cryptodev_session_ctx session_ctx, uint8_t is_update);\n+\n+int\n+dpaa_sec_get_dp_ctx_size(struct rte_cryptodev *dev);\n+\n+int\n+dpaa_sec_attach_sess_q(struct dpaa_sec_qp *qp, dpaa_sec_session *sess);\n+\n #endif /* _DPAA_SEC_H_ */\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c b/drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c\nnew file mode 100644\nindex 0000000000..ee0ca2e0d5\n--- /dev/null\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c\n@@ -0,0 +1,485 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021 NXP\n+ */\n+\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#ifdef RTE_LIB_SECURITY\n+#include <rte_security_driver.h>\n+#endif\n+\n+/* RTA header files */\n+#include <desc/ipsec.h>\n+\n+#include <rte_dpaa_bus.h>\n+#include <dpaa_sec.h>\n+#include <dpaa_sec_log.h>\n+\n+struct dpaa_sec_raw_dp_ctx {\n+\tdpaa_sec_session *session;\n+\tuint32_t tail;\n+\tuint32_t head;\n+\tuint16_t cached_enqueue;\n+\tuint16_t cached_dequeue;\n+};\n+\n+static __rte_always_inline int\n+dpaa_sec_raw_enqueue_done(void *qp_data, uint8_t *drv_ctx, uint32_t n)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(n);\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+dpaa_sec_raw_dequeue_done(void *qp_data, uint8_t *drv_ctx, uint32_t n)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(n);\n+\n+\treturn 0;\n+}\n+\n+static inline struct dpaa_sec_op_ctx *\n+dpaa_sec_alloc_raw_ctx(dpaa_sec_session *ses, int sg_count)\n+{\n+\tstruct dpaa_sec_op_ctx *ctx;\n+\tint i, retval;\n+\n+\tretval = rte_mempool_get(\n+\t\t\tses->qp[rte_lcore_id() % MAX_DPAA_CORES]->ctx_pool,\n+\t\t\t(void **)(&ctx));\n+\tif (!ctx || retval) {\n+\t\tDPAA_SEC_DP_WARN(\"Alloc sec descriptor failed!\");\n+\t\treturn NULL;\n+\t}\n+\t/*\n+\t * Clear SG memory. There are 16 SG entries of 16 Bytes each.\n+\t * one call to dcbz_64() clear 64 bytes, hence calling it 4 times\n+\t * to clear all the SG entries. dpaa_sec_alloc_ctx() is called for\n+\t * each packet, memset is costlier than dcbz_64().\n+\t */\n+\tfor (i = 0; i < sg_count && i < MAX_JOB_SG_ENTRIES; i += 4)\n+\t\tdcbz_64(&ctx->job.sg[i]);\n+\n+\tctx->ctx_pool = ses->qp[rte_lcore_id() % MAX_DPAA_CORES]->ctx_pool;\n+\tctx->vtop_offset = (size_t) ctx - rte_mempool_virt2iova(ctx);\n+\n+\treturn ctx;\n+}\n+\n+static struct dpaa_sec_job *\n+build_dpaa_raw_dp_auth_fd(uint8_t *drv_ctx,\n+\t\t\tstruct rte_crypto_sgl *sgl,\n+\t\t\tstruct rte_crypto_sgl *dest_sgl,\n+\t\t\tstruct rte_crypto_va_iova_ptr *iv,\n+\t\t\tstruct rte_crypto_va_iova_ptr *digest,\n+\t\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t\tunion rte_crypto_sym_ofs ofs,\n+\t\t\tvoid *userdata)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(dest_sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\n+\treturn NULL;\n+}\n+\n+static struct dpaa_sec_job *\n+build_dpaa_raw_dp_cipher_fd(uint8_t *drv_ctx,\n+\t\t\tstruct rte_crypto_sgl *sgl,\n+\t\t\tstruct rte_crypto_sgl *dest_sgl,\n+\t\t\tstruct rte_crypto_va_iova_ptr *iv,\n+\t\t\tstruct rte_crypto_va_iova_ptr *digest,\n+\t\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t\tunion rte_crypto_sym_ofs ofs,\n+\t\t\tvoid *userdata)\n+{\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tdpaa_sec_session *ses =\n+\t\t((struct dpaa_sec_raw_dp_ctx *)drv_ctx)->session;\n+\tstruct dpaa_sec_job *cf;\n+\tstruct dpaa_sec_op_ctx *ctx;\n+\tstruct qm_sg_entry *sg, *out_sg, *in_sg;\n+\tunsigned int i;\n+\tuint8_t *IV_ptr = iv->va;\n+\tint data_len, total_len = 0, data_offset;\n+\n+\tfor (i = 0; i < sgl->num; i++)\n+\t\ttotal_len += sgl->vec[i].len;\n+\n+\tdata_len = total_len - ofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\tdata_offset = ofs.ofs.cipher.head;\n+\n+\t/* Support lengths in bits only for SNOW3G and ZUC */\n+\tif (sgl->num > MAX_SG_ENTRIES) {\n+\t\tDPAA_SEC_DP_ERR(\"Cipher: Max sec segs supported is %d\",\n+\t\t\t\tMAX_SG_ENTRIES);\n+\t\treturn NULL;\n+\t}\n+\n+\tctx = dpaa_sec_alloc_raw_ctx(ses, sgl->num * 2 + 3);\n+\tif (!ctx)\n+\t\treturn NULL;\n+\n+\tcf = &ctx->job;\n+\tctx->userdata = (void *)userdata;\n+\n+\t/* output */\n+\tout_sg = &cf->sg[0];\n+\tout_sg->extension = 1;\n+\tout_sg->length = data_len;\n+\tqm_sg_entry_set64(out_sg, rte_dpaa_mem_vtop(&cf->sg[2]));\n+\tcpu_to_hw_sg(out_sg);\n+\n+\tif (dest_sgl) {\n+\t\t/* 1st seg */\n+\t\tsg = &cf->sg[2];\n+\t\tqm_sg_entry_set64(sg, dest_sgl->vec[0].iova);\n+\t\tsg->length = dest_sgl->vec[0].len - data_offset;\n+\t\tsg->offset = data_offset;\n+\n+\t\t/* Successive segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tcpu_to_hw_sg(sg);\n+\t\t\tsg++;\n+\t\t\tqm_sg_entry_set64(sg, dest_sgl->vec[i].iova);\n+\t\t\tsg->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* 1st seg */\n+\t\tsg = &cf->sg[2];\n+\t\tqm_sg_entry_set64(sg, sgl->vec[0].iova);\n+\t\tsg->length = sgl->vec[0].len - data_offset;\n+\t\tsg->offset = data_offset;\n+\n+\t\t/* Successive segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tcpu_to_hw_sg(sg);\n+\t\t\tsg++;\n+\t\t\tqm_sg_entry_set64(sg, sgl->vec[i].iova);\n+\t\t\tsg->length = sgl->vec[i].len;\n+\t\t}\n+\n+\t}\n+\tsg->final = 1;\n+\tcpu_to_hw_sg(sg);\n+\n+\t/* input */\n+\tin_sg = &cf->sg[1];\n+\tin_sg->extension = 1;\n+\tin_sg->final = 1;\n+\tin_sg->length = data_len + ses->iv.length;\n+\n+\tsg++;\n+\tqm_sg_entry_set64(in_sg, rte_dpaa_mem_vtop(sg));\n+\tcpu_to_hw_sg(in_sg);\n+\n+\t/* IV */\n+\tqm_sg_entry_set64(sg, rte_dpaa_mem_vtop(IV_ptr));\n+\tsg->length = ses->iv.length;\n+\tcpu_to_hw_sg(sg);\n+\n+\t/* 1st seg */\n+\tsg++;\n+\tqm_sg_entry_set64(sg, sgl->vec[0].iova);\n+\tsg->length = sgl->vec[0].len - data_offset;\n+\tsg->offset = data_offset;\n+\n+\t/* Successive segs */\n+\tfor (i = 1; i < sgl->num; i++) {\n+\t\tcpu_to_hw_sg(sg);\n+\t\tsg++;\n+\t\tqm_sg_entry_set64(sg, sgl->vec[i].iova);\n+\t\tsg->length = sgl->vec[i].len;\n+\t}\n+\tsg->final = 1;\n+\tcpu_to_hw_sg(sg);\n+\n+\treturn cf;\n+}\n+\n+static uint32_t\n+dpaa_sec_raw_enqueue_burst(void *qp_data, uint8_t *drv_ctx,\n+\tstruct rte_crypto_sym_vec *vec, union rte_crypto_sym_ofs ofs,\n+\tvoid *user_data[], int *status)\n+{\n+\t/* Function to transmit the frames to given device and queuepair */\n+\tuint32_t loop;\n+\tstruct dpaa_sec_qp *dpaa_qp = (struct dpaa_sec_qp *)qp_data;\n+\tuint16_t num_tx = 0;\n+\tstruct qm_fd fds[DPAA_SEC_BURST], *fd;\n+\tuint32_t frames_to_send;\n+\tstruct dpaa_sec_job *cf;\n+\tdpaa_sec_session *ses =\n+\t\t\t((struct dpaa_sec_raw_dp_ctx *)drv_ctx)->session;\n+\tuint32_t flags[DPAA_SEC_BURST] = {0};\n+\tstruct qman_fq *inq[DPAA_SEC_BURST];\n+\n+\tif (unlikely(!DPAA_PER_LCORE_PORTAL)) {\n+\t\tif (rte_dpaa_portal_init((void *)0)) {\n+\t\t\tDPAA_SEC_ERR(\"Failure in affining portal\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\twhile (vec->num) {\n+\t\tframes_to_send = (vec->num > DPAA_SEC_BURST) ?\n+\t\t\t\tDPAA_SEC_BURST : vec->num;\n+\t\tfor (loop = 0; loop < frames_to_send; loop++) {\n+\t\t\tif (unlikely(!ses->qp[rte_lcore_id() % MAX_DPAA_CORES])) {\n+\t\t\t\tif (dpaa_sec_attach_sess_q(dpaa_qp, ses)) {\n+\t\t\t\t\tframes_to_send = loop;\n+\t\t\t\t\tgoto send_pkts;\n+\t\t\t\t}\n+\t\t\t} else if (unlikely(ses->qp[rte_lcore_id() %\n+\t\t\t\t\t\tMAX_DPAA_CORES] != dpaa_qp)) {\n+\t\t\t\tDPAA_SEC_DP_ERR(\"Old:sess->qp = %p\"\n+\t\t\t\t\t\" New qp = %p\\n\",\n+\t\t\t\t\tses->qp[rte_lcore_id() %\n+\t\t\t\t\tMAX_DPAA_CORES], dpaa_qp);\n+\t\t\t\tframes_to_send = loop;\n+\t\t\t\tgoto send_pkts;\n+\t\t\t}\n+\n+\t\t\t/*Clear the unused FD fields before sending*/\n+\t\t\tfd = &fds[loop];\n+\t\t\tmemset(fd, 0, sizeof(struct qm_fd));\n+\t\t\tcf = ses->build_raw_dp_fd(drv_ctx,\n+\t\t\t\t\t\t&vec->src_sgl[loop],\n+\t\t\t\t\t\t&vec->dest_sgl[loop],\n+\t\t\t\t\t\t&vec->iv[loop],\n+\t\t\t\t\t\t&vec->digest[loop],\n+\t\t\t\t\t\t&vec->auth_iv[loop],\n+\t\t\t\t\t\tofs,\n+\t\t\t\t\t\tuser_data[loop]);\n+\t\t\tif (!cf) {\n+\t\t\t\tDPAA_SEC_ERR(\"error: Improper packet contents\"\n+\t\t\t\t\t\" for crypto operation\");\n+\t\t\t\tgoto skip_tx;\n+\t\t\t}\n+\t\t\tinq[loop] = ses->inq[rte_lcore_id() % MAX_DPAA_CORES];\n+\t\t\tfd->opaque_addr = 0;\n+\t\t\tfd->cmd = 0;\n+\t\t\tqm_fd_addr_set64(fd, rte_dpaa_mem_vtop(cf->sg));\n+\t\t\tfd->_format1 = qm_fd_compound;\n+\t\t\tfd->length29 = 2 * sizeof(struct qm_sg_entry);\n+\n+\t\t\tstatus[loop] = 1;\n+\t\t}\n+send_pkts:\n+\t\tloop = 0;\n+\t\twhile (loop < frames_to_send) {\n+\t\t\tloop += qman_enqueue_multi_fq(&inq[loop], &fds[loop],\n+\t\t\t\t\t&flags[loop], frames_to_send - loop);\n+\t\t}\n+\t\tvec->num -= frames_to_send;\n+\t\tnum_tx += frames_to_send;\n+\t}\n+\n+skip_tx:\n+\tdpaa_qp->tx_pkts += num_tx;\n+\tdpaa_qp->tx_errs += vec->num - num_tx;\n+\n+\treturn num_tx;\n+}\n+\n+static int\n+dpaa_sec_deq_raw(struct dpaa_sec_qp *qp, void **out_user_data,\n+\t\tuint8_t is_user_data_array,\n+\t\trte_cryptodev_raw_post_dequeue_t post_dequeue,\n+\t\tint nb_ops)\n+{\n+\tstruct qman_fq *fq;\n+\tunsigned int pkts = 0;\n+\tint num_rx_bufs, ret;\n+\tstruct qm_dqrr_entry *dq;\n+\tuint32_t vdqcr_flags = 0;\n+\tuint8_t is_success = 0;\n+\n+\tfq = &qp->outq;\n+\t/*\n+\t * Until request for four buffers, we provide exact number of buffers.\n+\t * Otherwise we do not set the QM_VDQCR_EXACT flag.\n+\t * Not setting QM_VDQCR_EXACT flag can provide two more buffers than\n+\t * requested, so we request two less in this case.\n+\t */\n+\tif (nb_ops < 4) {\n+\t\tvdqcr_flags = QM_VDQCR_EXACT;\n+\t\tnum_rx_bufs = nb_ops;\n+\t} else {\n+\t\tnum_rx_bufs = nb_ops > DPAA_MAX_DEQUEUE_NUM_FRAMES ?\n+\t\t\t(DPAA_MAX_DEQUEUE_NUM_FRAMES - 2) : (nb_ops - 2);\n+\t}\n+\tret = qman_set_vdq(fq, num_rx_bufs, vdqcr_flags);\n+\tif (ret)\n+\t\treturn 0;\n+\n+\tdo {\n+\t\tconst struct qm_fd *fd;\n+\t\tstruct dpaa_sec_job *job;\n+\t\tstruct dpaa_sec_op_ctx *ctx;\n+\n+\t\tdq = qman_dequeue(fq);\n+\t\tif (!dq)\n+\t\t\tcontinue;\n+\n+\t\tfd = &dq->fd;\n+\t\t/* sg is embedded in an op ctx,\n+\t\t * sg[0] is for output\n+\t\t * sg[1] for input\n+\t\t */\n+\t\tjob = rte_dpaa_mem_ptov(qm_fd_addr_get64(fd));\n+\n+\t\tctx = container_of(job, struct dpaa_sec_op_ctx, job);\n+\t\tctx->fd_status = fd->status;\n+\t\tif (is_user_data_array)\n+\t\t\tout_user_data[pkts] = ctx->userdata;\n+\t\telse\n+\t\t\tout_user_data[0] = ctx->userdata;\n+\n+\t\tif (!ctx->fd_status) {\n+\t\t\tis_success = true;\n+\t\t} else {\n+\t\t\tis_success = false;\n+\t\t\tDPAA_SEC_DP_WARN(\"SEC return err:0x%x\", ctx->fd_status);\n+\t\t}\n+\t\tpost_dequeue(ctx->op, pkts, is_success);\n+\t\tpkts++;\n+\n+\t\t/* report op status to sym->op and then free the ctx memory */\n+\t\trte_mempool_put(ctx->ctx_pool, (void *)ctx);\n+\n+\t\tqman_dqrr_consume(fq, dq);\n+\t} while (fq->flags & QMAN_FQ_STATE_VDQCR);\n+\n+\treturn pkts;\n+}\n+\n+\n+static __rte_always_inline uint32_t\n+dpaa_sec_raw_dequeue_burst(void *qp_data, uint8_t *drv_ctx,\n+\trte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,\n+\tuint32_t max_nb_to_dequeue,\n+\trte_cryptodev_raw_post_dequeue_t post_dequeue,\n+\tvoid **out_user_data, uint8_t is_user_data_array,\n+\tuint32_t *n_success, int *dequeue_status)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(get_dequeue_count);\n+\tuint16_t num_rx;\n+\tstruct dpaa_sec_qp *dpaa_qp = (struct dpaa_sec_qp *)qp_data;\n+\tuint32_t nb_ops = max_nb_to_dequeue;\n+\n+\tif (unlikely(!DPAA_PER_LCORE_PORTAL)) {\n+\t\tif (rte_dpaa_portal_init((void *)0)) {\n+\t\t\tDPAA_SEC_ERR(\"Failure in affining portal\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\tnum_rx = dpaa_sec_deq_raw(dpaa_qp, out_user_data,\n+\t\t\tis_user_data_array, post_dequeue, nb_ops);\n+\n+\tdpaa_qp->rx_pkts += num_rx;\n+\t*dequeue_status = 1;\n+\t*n_success = num_rx;\n+\n+\tDPAA_SEC_DP_DEBUG(\"SEC Received %d Packets\\n\", num_rx);\n+\n+\treturn num_rx;\n+}\n+\n+static __rte_always_inline int\n+dpaa_sec_raw_enqueue(void *qp_data, uint8_t *drv_ctx,\n+\tstruct rte_crypto_vec *data_vec,\n+\tuint16_t n_data_vecs, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad_or_auth_iv,\n+\tvoid *user_data)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(data_vec);\n+\tRTE_SET_USED(n_data_vecs);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(aad_or_auth_iv);\n+\tRTE_SET_USED(user_data);\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline void *\n+dpaa_sec_raw_dequeue(void *qp_data, uint8_t *drv_ctx, int *dequeue_status,\n+\tenum rte_crypto_op_status *op_status)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(dequeue_status);\n+\tRTE_SET_USED(op_status);\n+\n+\treturn NULL;\n+}\n+\n+int\n+dpaa_sec_configure_raw_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n+\tenum rte_crypto_op_sess_type sess_type,\n+\tunion rte_cryptodev_session_ctx session_ctx, uint8_t is_update)\n+{\n+\tdpaa_sec_session *sess;\n+\tstruct dpaa_sec_raw_dp_ctx *dp_ctx;\n+\tRTE_SET_USED(qp_id);\n+\n+\tif (!is_update) {\n+\t\tmemset(raw_dp_ctx, 0, sizeof(*raw_dp_ctx));\n+\t\traw_dp_ctx->qp_data = dev->data->queue_pairs[qp_id];\n+\t}\n+\n+\tif (sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)\n+\t\tsess = (dpaa_sec_session *)get_sec_session_private_data(\n+\t\t\t\tsession_ctx.sec_sess);\n+\telse if (sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n+\t\tsess = (dpaa_sec_session *)get_sym_session_private_data(\n+\t\t\tsession_ctx.crypto_sess, dpaa_cryptodev_driver_id);\n+\telse\n+\t\treturn -ENOTSUP;\n+\traw_dp_ctx->dequeue_burst = dpaa_sec_raw_dequeue_burst;\n+\traw_dp_ctx->dequeue = dpaa_sec_raw_dequeue;\n+\traw_dp_ctx->dequeue_done = dpaa_sec_raw_dequeue_done;\n+\traw_dp_ctx->enqueue_burst = dpaa_sec_raw_enqueue_burst;\n+\traw_dp_ctx->enqueue = dpaa_sec_raw_enqueue;\n+\traw_dp_ctx->enqueue_done = dpaa_sec_raw_enqueue_done;\n+\n+\tif (sess->ctxt == DPAA_SEC_CIPHER)\n+\t\tsess->build_raw_dp_fd = build_dpaa_raw_dp_cipher_fd;\n+\telse if (sess->ctxt == DPAA_SEC_AUTH)\n+\t\tsess->build_raw_dp_fd = build_dpaa_raw_dp_auth_fd;\n+\telse\n+\t\treturn -ENOTSUP;\n+\tdp_ctx = (struct dpaa_sec_raw_dp_ctx *)raw_dp_ctx->drv_ctx_data;\n+\tdp_ctx->session = sess;\n+\n+\treturn 0;\n+}\n+\n+int\n+dpaa_sec_get_dp_ctx_size(__rte_unused struct rte_cryptodev *dev)\n+{\n+\treturn sizeof(struct dpaa_sec_raw_dp_ctx);\n+}\ndiff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build\nindex 44fd60e5ae..f87ad6c7e7 100644\n--- a/drivers/crypto/dpaa_sec/meson.build\n+++ b/drivers/crypto/dpaa_sec/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright 2018 NXP\n+# Copyright 2018-2021 NXP\n \n if not is_linux\n build = false\n@@ -7,7 +7,7 @@ if not is_linux\n endif\n \n deps += ['bus_dpaa', 'mempool_dpaa', 'security']\n-sources = files('dpaa_sec.c')\n+sources = files('dpaa_sec.c', 'dpaa_sec_raw_dp.c')\n \n includes += include_directories('../../bus/dpaa/include')\n includes += include_directories('../../common/dpaax')\n", "prefixes": [ "RFC", "12/16" ] }