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GET /api/patches/95406/?format=api
{ "id": 95406, "url": "https://patches.dpdk.org/api/patches/95406/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210706133257.3353-20-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210706133257.3353-20-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210706133257.3353-20-suanmingm@nvidia.com", "date": "2021-07-06T13:32:50", "name": "[v4,19/26] common/mlx5: support list non-lcore operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fedba9165399b0d442901130db413969ea0a39b4", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210706133257.3353-20-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17668, "url": "https://patches.dpdk.org/api/series/17668/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17668", "date": "2021-07-06T13:32:31", "name": "net/mlx5: insertion rate optimization", "version": 4, "mbox": "https://patches.dpdk.org/series/17668/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95406/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95406/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3FD51A0C47;\n\tTue, 6 Jul 2021 15:36:05 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 18C034146B;\n\tTue, 6 Jul 2021 15:33:57 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2057.outbound.protection.outlook.com [40.107.220.57])\n by mails.dpdk.org (Postfix) with ESMTP id EC70F4145B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Tue, 6 Jul 2021 16:32:50 +0300", "Message-ID": "<20210706133257.3353-20-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210706133257.3353-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210706133257.3353-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "ba54b904-6f6d-4a8b-a36c-08d94082b1fb", "X-MS-TrafficTypeDiagnostic": "BN8PR12MB3537:", "X-Microsoft-Antispam-PRVS": "\n <BN8PR12MB353724407B967E219E0226F6C11B9@BN8PR12MB3537.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:51;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n VlYrjVaUx+cFWaBr0sfRswaXX8Y+wNUqbwRx1If3eunfADFDCfARK0acTzMM8zageEkAmT+dK7nMOruUQQ7rFX8CkhaUVvsN1MhpP07m6tX6U6YvTWPVu+co9YyOpnHFHlRK+POZATOSQrLTU/cKTs92RVAgSq39GWi8MWAryB3MFrkRHnhBvKE0QR9KHuS7cqUdXQm1JfFTndwgFl64yJ6g3GlZZkGZxwPK6XhQMz7fjLbnlGMEjNJZEC1FQsynXnYmi62WlFIkMCMNrpaHxv1APAWQWAGsFzbRqav7ujooAlvRJh/IP25cyjQ42QMwmBi2RoUErp8W/dhRfVVa3EgGKrRHVsonH60eOaSEjMEfl3bSkcIw+yZf45yT5aGeIXfgd4bNgFTVlP2REq+TZKI0U2gkkr72NdCqmt6NhVkcM787gu97eGYDQZpyEMCm57rXcUbnYw5Czo6E/n5G7dx9zr/U1oEvgmR3Kn9C8PiayM7mALooIStrqYolbKJ1QzWmuE1e/8gqgkbgj0wD2BzuEVnAujWxM3Lsu3Q3d6IlYBGpoOR+Jnip8p2Q/XM2C0QECYLHqi8RRbI35ldrExfMcSQ6SSlSD82I01/3GPFmqiJzF41HQS+YIGw3JSWkpyAuc9KUimuKPE95eD6N52NdeA0lB/cB7GZ++lgUhlBdjT+DFckLaeLcHrdw5etAIadt9aGl4roUxmF0HOjwTQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(396003)(136003)(346002)(376002)(36840700001)(46966006)(47076005)(8676002)(316002)(83380400001)(36756003)(2906002)(2616005)(36906005)(478600001)(86362001)(55016002)(186003)(356005)(7636003)(1076003)(426003)(7696005)(8936002)(82310400003)(36860700001)(16526019)(6286002)(5660300002)(82740400003)(6636002)(336012)(54906003)(4326008)(110136005)(26005)(70586007)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Jul 2021 13:33:52.3212 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ba54b904-6f6d-4a8b-a36c-08d94082b1fb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT056.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN8PR12MB3537", "Subject": "[dpdk-dev] [PATCH v4 19/26] common/mlx5: support list non-lcore\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit supports the list non-lcore operations with\nan extra sub-list and lock.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_utils.c | 92 +++++++++++++++++--------\n drivers/common/mlx5/mlx5_common_utils.h | 9 ++-\n 2 files changed, 71 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_utils.c b/drivers/common/mlx5/mlx5_common_utils.c\nindex 858c8d8164..c8b48f3afc 100644\n--- a/drivers/common/mlx5/mlx5_common_utils.c\n+++ b/drivers/common/mlx5/mlx5_common_utils.c\n@@ -20,8 +20,8 @@ mlx5_list_init(struct mlx5_list_inconst *l_inconst,\n {\n \trte_rwlock_init(&l_inconst->lock);\n \tif (l_const->lcores_share) {\n-\t\tl_inconst->cache[RTE_MAX_LCORE] = gc;\n-\t\tLIST_INIT(&l_inconst->cache[RTE_MAX_LCORE]->h);\n+\t\tl_inconst->cache[MLX5_LIST_GLOBAL] = gc;\n+\t\tLIST_INIT(&l_inconst->cache[MLX5_LIST_GLOBAL]->h);\n \t}\n \tDRV_LOG(DEBUG, \"mlx5 list %s initialized.\", l_const->name);\n \treturn 0;\n@@ -59,6 +59,7 @@ mlx5_list_create(const char *name, void *ctx, bool lcores_share,\n \tlist->l_const.cb_remove = cb_remove;\n \tlist->l_const.cb_clone = cb_clone;\n \tlist->l_const.cb_clone_free = cb_clone_free;\n+\trte_spinlock_init(&list->l_const.lcore_lock);\n \tif (lcores_share)\n \t\tgc = (struct mlx5_list_cache *)(list + 1);\n \tif (mlx5_list_init(&list->l_inconst, &list->l_const, gc) != 0) {\n@@ -85,11 +86,11 @@ __list_lookup(struct mlx5_list_inconst *l_inconst,\n \t\t\t\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p ref: %u.\",\n \t\t\t\t\tl_const->name, (void *)entry,\n \t\t\t\t\tentry->ref_cnt);\n-\t\t\t} else if (lcore_index < RTE_MAX_LCORE) {\n+\t\t\t} else if (lcore_index < MLX5_LIST_GLOBAL) {\n \t\t\t\tret = __atomic_load_n(&entry->ref_cnt,\n \t\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t\t}\n-\t\t\tif (likely(ret != 0 || lcore_index == RTE_MAX_LCORE))\n+\t\t\tif (likely(ret != 0 || lcore_index == MLX5_LIST_GLOBAL))\n \t\t\t\treturn entry;\n \t\t\tif (reuse && ret == 0)\n \t\t\t\tentry->ref_cnt--; /* Invalid entry. */\n@@ -107,10 +108,11 @@ _mlx5_list_lookup(struct mlx5_list_inconst *l_inconst,\n \tint i;\n \n \trte_rwlock_read_lock(&l_inconst->lock);\n-\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\tfor (i = 0; i < MLX5_LIST_GLOBAL; i++) {\n \t\tif (!l_inconst->cache[i])\n \t\t\tcontinue;\n-\t\tentry = __list_lookup(l_inconst, l_const, i, ctx, false);\n+\t\tentry = __list_lookup(l_inconst, l_const, i,\n+\t\t\t ctx, false);\n \t\tif (entry)\n \t\t\tbreak;\n \t}\n@@ -170,18 +172,11 @@ __list_cache_clean(struct mlx5_list_inconst *l_inconst,\n static inline struct mlx5_list_entry *\n _mlx5_list_register(struct mlx5_list_inconst *l_inconst,\n \t\t struct mlx5_list_const *l_const,\n-\t\t void *ctx)\n+\t\t void *ctx, int lcore_index)\n {\n \tstruct mlx5_list_entry *entry, *local_entry;\n \tvolatile uint32_t prev_gen_cnt = 0;\n-\tint lcore_index = rte_lcore_index(rte_lcore_id());\n-\n \tMLX5_ASSERT(l_inconst);\n-\tMLX5_ASSERT(lcore_index < RTE_MAX_LCORE);\n-\tif (unlikely(lcore_index == -1)) {\n-\t\trte_errno = ENOTSUP;\n-\t\treturn NULL;\n-\t}\n \tif (unlikely(!l_inconst->cache[lcore_index])) {\n \t\tl_inconst->cache[lcore_index] = mlx5_malloc(0,\n \t\t\t\t\tsizeof(struct mlx5_list_cache),\n@@ -202,7 +197,7 @@ _mlx5_list_register(struct mlx5_list_inconst *l_inconst,\n \tif (l_const->lcores_share) {\n \t\t/* 2. Lookup with read lock on global list, reuse if found. */\n \t\trte_rwlock_read_lock(&l_inconst->lock);\n-\t\tentry = __list_lookup(l_inconst, l_const, RTE_MAX_LCORE,\n+\t\tentry = __list_lookup(l_inconst, l_const, MLX5_LIST_GLOBAL,\n \t\t\t\t ctx, true);\n \t\tif (likely(entry)) {\n \t\t\trte_rwlock_read_unlock(&l_inconst->lock);\n@@ -241,7 +236,7 @@ _mlx5_list_register(struct mlx5_list_inconst *l_inconst,\n \tif (unlikely(prev_gen_cnt != l_inconst->gen_cnt)) {\n \t\tstruct mlx5_list_entry *oentry = __list_lookup(l_inconst,\n \t\t\t\t\t\t\t l_const,\n-\t\t\t\t\t\t\t RTE_MAX_LCORE,\n+\t\t\t\t\t\t\t MLX5_LIST_GLOBAL,\n \t\t\t\t\t\t\t ctx, true);\n \n \t\tif (unlikely(oentry)) {\n@@ -255,7 +250,7 @@ _mlx5_list_register(struct mlx5_list_inconst *l_inconst,\n \t\t}\n \t}\n \t/* 5. Update lists. */\n-\tLIST_INSERT_HEAD(&l_inconst->cache[RTE_MAX_LCORE]->h, entry, next);\n+\tLIST_INSERT_HEAD(&l_inconst->cache[MLX5_LIST_GLOBAL]->h, entry, next);\n \tl_inconst->gen_cnt++;\n \trte_rwlock_write_unlock(&l_inconst->lock);\n \tLIST_INSERT_HEAD(&l_inconst->cache[lcore_index]->h, local_entry, next);\n@@ -268,21 +263,30 @@ _mlx5_list_register(struct mlx5_list_inconst *l_inconst,\n struct mlx5_list_entry *\n mlx5_list_register(struct mlx5_list *list, void *ctx)\n {\n-\treturn _mlx5_list_register(&list->l_inconst, &list->l_const, ctx);\n+\tstruct mlx5_list_entry *entry;\n+\tint lcore_index = rte_lcore_index(rte_lcore_id());\n+\n+\tif (unlikely(lcore_index == -1)) {\n+\t\tlcore_index = MLX5_LIST_NLCORE;\n+\t\trte_spinlock_lock(&list->l_const.lcore_lock);\n+\t}\n+\tentry = _mlx5_list_register(&list->l_inconst, &list->l_const, ctx,\n+\t\t\t\t lcore_index);\n+\tif (unlikely(lcore_index == MLX5_LIST_NLCORE))\n+\t\trte_spinlock_unlock(&list->l_const.lcore_lock);\n+\treturn entry;\n }\n \n static inline int\n _mlx5_list_unregister(struct mlx5_list_inconst *l_inconst,\n \t\t struct mlx5_list_const *l_const,\n-\t\t struct mlx5_list_entry *entry)\n+\t\t struct mlx5_list_entry *entry,\n+\t\t int lcore_idx)\n {\n \tstruct mlx5_list_entry *gentry = entry->gentry;\n-\tint lcore_idx;\n \n \tif (__atomic_sub_fetch(&entry->ref_cnt, 1, __ATOMIC_RELAXED) != 0)\n \t\treturn 1;\n-\tlcore_idx = rte_lcore_index(rte_lcore_id());\n-\tMLX5_ASSERT(lcore_idx < RTE_MAX_LCORE);\n \tif (entry->lcore_idx == (uint32_t)lcore_idx) {\n \t\tLIST_REMOVE(entry, next);\n \t\tif (l_const->lcores_share)\n@@ -321,7 +325,19 @@ int\n mlx5_list_unregister(struct mlx5_list *list,\n \t\t struct mlx5_list_entry *entry)\n {\n-\treturn _mlx5_list_unregister(&list->l_inconst, &list->l_const, entry);\n+\tint ret;\n+\tint lcore_index = rte_lcore_index(rte_lcore_id());\n+\n+\tif (unlikely(lcore_index == -1)) {\n+\t\tlcore_index = MLX5_LIST_NLCORE;\n+\t\trte_spinlock_lock(&list->l_const.lcore_lock);\n+\t}\n+\tret = _mlx5_list_unregister(&list->l_inconst, &list->l_const, entry,\n+\t\t\t\t lcore_index);\n+\tif (unlikely(lcore_index == MLX5_LIST_NLCORE))\n+\t\trte_spinlock_unlock(&list->l_const.lcore_lock);\n+\treturn ret;\n+\n }\n \n static void\n@@ -332,13 +348,13 @@ mlx5_list_uninit(struct mlx5_list_inconst *l_inconst,\n \tint i;\n \n \tMLX5_ASSERT(l_inconst);\n-\tfor (i = 0; i <= RTE_MAX_LCORE; i++) {\n+\tfor (i = 0; i < MLX5_LIST_MAX; i++) {\n \t\tif (!l_inconst->cache[i])\n \t\t\tcontinue;\n \t\twhile (!LIST_EMPTY(&l_inconst->cache[i]->h)) {\n \t\t\tentry = LIST_FIRST(&l_inconst->cache[i]->h);\n \t\t\tLIST_REMOVE(entry, next);\n-\t\t\tif (i == RTE_MAX_LCORE) {\n+\t\t\tif (i == MLX5_LIST_GLOBAL) {\n \t\t\t\tl_const->cb_remove(l_const->ctx, entry);\n \t\t\t\tDRV_LOG(DEBUG, \"mlx5 list %s entry %p \"\n \t\t\t\t\t\"destroyed.\", l_const->name,\n@@ -347,7 +363,7 @@ mlx5_list_uninit(struct mlx5_list_inconst *l_inconst,\n \t\t\t\tl_const->cb_clone_free(l_const->ctx, entry);\n \t\t\t}\n \t\t}\n-\t\tif (i != RTE_MAX_LCORE)\n+\t\tif (i != MLX5_LIST_GLOBAL)\n \t\t\tmlx5_free(l_inconst->cache[i]);\n \t}\n }\n@@ -416,6 +432,7 @@ mlx5_hlist_create(const char *name, uint32_t size, bool direct_key,\n \th->l_const.cb_remove = cb_remove;\n \th->l_const.cb_clone = cb_clone;\n \th->l_const.cb_clone_free = cb_clone_free;\n+\trte_spinlock_init(&h->l_const.lcore_lock);\n \th->mask = act_size - 1;\n \th->direct_key = direct_key;\n \tgc = (struct mlx5_list_cache *)&h->buckets[act_size];\n@@ -449,28 +466,45 @@ mlx5_hlist_register(struct mlx5_hlist *h, uint64_t key, void *ctx)\n {\n \tuint32_t idx;\n \tstruct mlx5_list_entry *entry;\n+\tint lcore_index = rte_lcore_index(rte_lcore_id());\n \n \tif (h->direct_key)\n \t\tidx = (uint32_t)(key & h->mask);\n \telse\n \t\tidx = rte_hash_crc_8byte(key, 0) & h->mask;\n-\tentry = _mlx5_list_register(&h->buckets[idx].l, &h->l_const, ctx);\n+\tif (unlikely(lcore_index == -1)) {\n+\t\tlcore_index = MLX5_LIST_NLCORE;\n+\t\trte_spinlock_lock(&h->l_const.lcore_lock);\n+\t}\n+\tentry = _mlx5_list_register(&h->buckets[idx].l, &h->l_const, ctx,\n+\t\t\t\t lcore_index);\n \tif (likely(entry)) {\n \t\tif (h->l_const.lcores_share)\n \t\t\tentry->gentry->bucket_idx = idx;\n \t\telse\n \t\t\tentry->bucket_idx = idx;\n \t}\n+\tif (unlikely(lcore_index == MLX5_LIST_NLCORE))\n+\t\trte_spinlock_unlock(&h->l_const.lcore_lock);\n \treturn entry;\n }\n \n int\n mlx5_hlist_unregister(struct mlx5_hlist *h, struct mlx5_list_entry *entry)\n {\n+\tint lcore_index = rte_lcore_index(rte_lcore_id());\n+\tint ret;\n \tuint32_t idx = h->l_const.lcores_share ? entry->gentry->bucket_idx :\n \t\t\t\t\t\t\t entry->bucket_idx;\n-\n-\treturn _mlx5_list_unregister(&h->buckets[idx].l, &h->l_const, entry);\n+\tif (unlikely(lcore_index == -1)) {\n+\t\tlcore_index = MLX5_LIST_NLCORE;\n+\t\trte_spinlock_lock(&h->l_const.lcore_lock);\n+\t}\n+\tret = _mlx5_list_unregister(&h->buckets[idx].l, &h->l_const, entry,\n+\t\t\t\t lcore_index);\n+\tif (unlikely(lcore_index == MLX5_LIST_NLCORE))\n+\t\trte_spinlock_unlock(&h->l_const.lcore_lock);\n+\treturn ret;\n }\n \n void\ndiff --git a/drivers/common/mlx5/mlx5_common_utils.h b/drivers/common/mlx5/mlx5_common_utils.h\nindex 5718a21be0..613d29de0c 100644\n--- a/drivers/common/mlx5/mlx5_common_utils.h\n+++ b/drivers/common/mlx5/mlx5_common_utils.h\n@@ -11,6 +11,12 @@\n \n /** Maximum size of string for naming. */\n #define MLX5_NAME_SIZE\t\t\t32\n+/** Maximum size of list. */\n+#define MLX5_LIST_MAX\t\t\t(RTE_MAX_LCORE + 2)\n+/** Global list index. */\n+#define MLX5_LIST_GLOBAL\t\t((MLX5_LIST_MAX) - 1)\n+/** None rte core list index. */\n+#define MLX5_LIST_NLCORE\t\t((MLX5_LIST_MAX) - 2)\n \n struct mlx5_list;\n \n@@ -87,6 +93,7 @@ struct mlx5_list_const {\n \tchar name[MLX5_NAME_SIZE]; /**< Name of the mlx5 list. */\n \tvoid *ctx; /* user objects target to callback. */\n \tbool lcores_share; /* Whether to share objects between the lcores. */\n+\trte_spinlock_t lcore_lock; /* Lock for non-lcore list. */\n \tmlx5_list_create_cb cb_create; /**< entry create callback. */\n \tmlx5_list_match_cb cb_match; /**< entry match callback. */\n \tmlx5_list_remove_cb cb_remove; /**< entry remove callback. */\n@@ -102,7 +109,7 @@ struct mlx5_list_inconst {\n \trte_rwlock_t lock; /* read/write lock. */\n \tvolatile uint32_t gen_cnt; /* List modification may update it. */\n \tvolatile uint32_t count; /* number of entries in list. */\n-\tstruct mlx5_list_cache *cache[RTE_MAX_LCORE + 1];\n+\tstruct mlx5_list_cache *cache[MLX5_LIST_MAX];\n \t/* Lcore cache, last index is the global cache. */\n };\n \n", "prefixes": [ "v4", "19/26" ] }