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GET /api/patches/95110/?format=api
{ "id": 95110, "url": "https://patches.dpdk.org/api/patches/95110/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1625131769-31114-1-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1625131769-31114-1-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1625131769-31114-1-git-send-email-anoobj@marvell.com", "date": "2021-07-01T09:29:29", "name": "net/octeontx2: support non-ethernet L2 hdr", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3dd37960ed03e6124ca5d83c815dda49b48a2822", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1625131769-31114-1-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17572, "url": "https://patches.dpdk.org/api/series/17572/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17572", "date": "2021-07-01T09:29:29", "name": "net/octeontx2: support non-ethernet L2 hdr", "version": 1, "mbox": "https://patches.dpdk.org/series/17572/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95110/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/95110/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E9059A0A0C;\n\tThu, 1 Jul 2021 11:29:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4A87C40141;\n\tThu, 1 Jul 2021 11:29:46 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5AD0640040\n for <dev@dpdk.org>; Thu, 1 Jul 2021 11:29:44 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 1619BFE9030281 for <dev@dpdk.org>; Thu, 1 Jul 2021 02:29:43 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39gxj0jtmy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Jul 2021 02:29:43 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 1 Jul 2021 02:29:41 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 1 Jul 2021 02:29:41 -0700", "from HY-LT1002.marvell.com (unknown [10.193.70.1])\n by maili.marvell.com (Postfix) with ESMTP id BC7943F709F;\n Thu, 1 Jul 2021 02:29:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=mJWhNl59PExDOinJISgDf1r2m1ukwF8hvtdWUrsE6t4=;\n b=B8c91HvA/Fe3UPrW+VJ58zpEzq6m0bwsc4sDeDda+a0R06ywSC9Y3ydOqpbH7nCi20Ny\n ErWx6GiuVT+yYgOUfhfqQHG6O9ANZJ8gcybcFhIz0lf2Eva3/6ZIdln29rB3EgAEstYN\n hNQSv/Z/Qhi5nWEES7xF+VEK6XT1ii9Mg7vdi+4FI0F/boaA5bEBHdVD74d/w8+o8n1M\n dEW5ptnuQ6sVabgETxvKjpxgqAmcXAd4pO84DS7H3u72hPL7KBMjJ0XgKIaZfJPD/94l\n 6vEJOrzOtNF+Pbm99ZNFwzyB0EJyvWrP4vjrkEdBMxCEOVjdGHP7bG4rERtc2kyGT7q1 oQ==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Jerin Jacob <jerinj@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 1 Jul 2021 14:59:29 +0530", "Message-ID": "<1625131769-31114-1-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "C9Vt2jYlsNaFpGnrcmRZKGMlYRDbQK4R", "X-Proofpoint-ORIG-GUID": "C9Vt2jYlsNaFpGnrcmRZKGMlYRDbQK4R", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-07-01_06:2021-06-30,\n 2021-07-01 signatures=0", "Subject": "[dpdk-dev] [PATCH] net/octeontx2: support non-ethernet L2 hdr", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In the inline inound path, a custom header would be present at L3 which\nhas sequence number & SPI. L2 need to be adjusted such that the eventual\npacket would have L3 after L2. Remove assumption of L2 type in this\nhandling.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h | 9 ++---\n drivers/crypto/octeontx2/otx2_ipsec_fp.h | 13 +++----\n drivers/net/octeontx2/otx2_rx.h | 45 ++++++++++++++++-------\n 3 files changed, 42 insertions(+), 25 deletions(-)", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h b/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h\nindex b2b1f77..089a3d0 100644\n--- a/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h\n+++ b/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h\n@@ -166,8 +166,9 @@ anti_replay_check(struct otx2_ipsec_replay *replay, uint64_t seq,\n }\n \n static inline int\n-cpt_ipsec_ip_antireplay_check(struct otx2_ipsec_fp_in_sa *sa, char *data)\n+cpt_ipsec_ip_antireplay_check(struct otx2_ipsec_fp_in_sa *sa, void *l3_ptr)\n {\n+\tstruct otx2_ipsec_fp_res_hdr *hdr = l3_ptr;\n \tuint64_t seq_in_sa;\n \tuint32_t seqh = 0;\n \tuint32_t seql;\n@@ -176,14 +177,12 @@ cpt_ipsec_ip_antireplay_check(struct otx2_ipsec_fp_in_sa *sa, char *data)\n \tint ret;\n \n \tesn = sa->ctl.esn_en;\n-\tseql = rte_be_to_cpu_32(*((uint32_t *)(data +\n-\t\t\tOTX2_IPSEC_SEQNO_LO_INDEX)));\n+\tseql = rte_be_to_cpu_32(hdr->seq_no_lo);\n \n \tif (!esn)\n \t\tseq = (uint64_t)seql;\n \telse {\n-\t\tseqh = rte_be_to_cpu_32(*((uint32_t *)(data +\n-\t\t\t\tOTX2_IPSEC_SEQNO_HI_INDEX)));\n+\t\tseqh = rte_be_to_cpu_32(hdr->seq_no_hi);\n \t\tseq = ((uint64_t)seqh << 32) | seql;\n \t}\n \ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_fp.h b/drivers/crypto/octeontx2/otx2_ipsec_fp.h\nindex a33041d..4be22d4 100644\n--- a/drivers/crypto/octeontx2/otx2_ipsec_fp.h\n+++ b/drivers/crypto/octeontx2/otx2_ipsec_fp.h\n@@ -10,14 +10,13 @@\n \n /* Macros for anti replay and ESN */\n #define OTX2_IPSEC_MAX_REPLAY_WIN_SZ\t1024\n-#define OTX2_IPSEC_SAINDEX_SZ\t\t4\n-#define OTX2_IPSEC_SEQNO_LO\t\t4\n \n-#define OTX2_IPSEC_SEQNO_LO_INDEX\t(RTE_ETHER_HDR_LEN + \\\n-\t\t\t\t\t OTX2_IPSEC_SAINDEX_SZ)\n-\n-#define OTX2_IPSEC_SEQNO_HI_INDEX\t(OTX2_IPSEC_SEQNO_LO_INDEX + \\\n-\t\t\t\t\t OTX2_IPSEC_SEQNO_LO)\n+struct otx2_ipsec_fp_res_hdr {\n+\tuint32_t spi;\n+\tuint32_t seq_no_lo;\n+\tuint32_t seq_no_hi;\n+\tuint32_t rsvd;\n+};\n \n enum {\n \tOTX2_IPSEC_FP_SA_DIRECTION_INBOUND = 0,\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\nindex 257492a..ea29aec 100644\n--- a/drivers/net/octeontx2/otx2_rx.h\n+++ b/drivers/net/octeontx2/otx2_rx.h\n@@ -41,7 +41,6 @@\n \n /* Inline IPsec offsets */\n \n-#define INLINE_INB_RPTR_HDR\t\t16\n /* nix_cqe_hdr_s + nix_rx_parse_s + nix_rx_sg_s + nix_iova_s */\n #define INLINE_CPT_RESULT_OFFSET\t80\n \n@@ -239,14 +238,18 @@ nix_rx_sec_sa_get(const void * const lookup_mem, int spi, uint16_t port)\n }\n \n static __rte_always_inline uint64_t\n-nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m,\n+nix_rx_sec_mbuf_update(const struct nix_rx_parse_s *rx,\n+\t\t const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m,\n \t\t const void * const lookup_mem)\n {\n+\tuint8_t *l2_ptr, *l3_ptr, *l2_ptr_actual, *l3_ptr_actual;\n \tstruct otx2_ipsec_fp_in_sa *sa;\n-\tstruct rte_ipv4_hdr *ipv4;\n-\tuint16_t m_len;\n+\tuint16_t m_len, l2_len, ip_len;\n+\tstruct rte_ipv6_hdr *ip6h;\n+\tstruct rte_ipv4_hdr *iph;\n+\tuint16_t *ether_type;\n \tuint32_t spi;\n-\tchar *data;\n+\tint i;\n \n \tif (unlikely(nix_rx_sec_cptres_get(cq) != OTX2_SEC_COMP_GOOD))\n \t\treturn PKT_RX_SEC_OFFLOAD | PKT_RX_SEC_OFFLOAD_FAILED;\n@@ -257,22 +260,38 @@ nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m,\n \tsa = nix_rx_sec_sa_get(lookup_mem, spi, m->port);\n \t*rte_security_dynfield(m) = sa->udata64;\n \n-\tdata = rte_pktmbuf_mtod(m, char *);\n+\tl2_ptr = rte_pktmbuf_mtod(m, uint8_t *);\n+\tl2_len = rx->lcptr - rx->laptr;\n+\tl3_ptr = RTE_PTR_ADD(l2_ptr, l2_len);\n \n \tif (sa->replay_win_sz) {\n-\t\tif (cpt_ipsec_ip_antireplay_check(sa, data) < 0)\n+\t\tif (cpt_ipsec_ip_antireplay_check(sa, l3_ptr) < 0)\n \t\t\treturn PKT_RX_SEC_OFFLOAD | PKT_RX_SEC_OFFLOAD_FAILED;\n \t}\n \n-\tmemcpy(data + INLINE_INB_RPTR_HDR, data, RTE_ETHER_HDR_LEN);\n+\tl2_ptr_actual = RTE_PTR_ADD(l2_ptr,\n+\t\t\t\t sizeof(struct otx2_ipsec_fp_res_hdr));\n+\tl3_ptr_actual = RTE_PTR_ADD(l3_ptr,\n+\t\t\t\t sizeof(struct otx2_ipsec_fp_res_hdr));\n \n-\tm->data_off += INLINE_INB_RPTR_HDR;\n+\tfor (i = l2_len - RTE_ETHER_TYPE_LEN - 1; i >= 0; i--)\n+\t\tl2_ptr_actual[i] = l2_ptr[i];\n \n-\tipv4 = (struct rte_ipv4_hdr *)(data + INLINE_INB_RPTR_HDR +\n-\t\t\t\t RTE_ETHER_HDR_LEN);\n+\tm->data_off += sizeof(struct otx2_ipsec_fp_res_hdr);\n \n-\tm_len = rte_be_to_cpu_16(ipv4->total_length) + RTE_ETHER_HDR_LEN;\n+\tether_type = RTE_PTR_SUB(l3_ptr_actual, RTE_ETHER_TYPE_LEN);\n \n+\tiph = (struct rte_ipv4_hdr *)l3_ptr_actual;\n+\tif ((iph->version_ihl >> 4) == 4) {\n+\t\tip_len = rte_be_to_cpu_16(iph->total_length);\n+\t\t*ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);\n+\t} else {\n+\t\tip6h = (struct rte_ipv6_hdr *)iph;\n+\t\tip_len = rte_be_to_cpu_16(ip6h->payload_len);\n+\t\t*ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);\n+\t}\n+\n+\tm_len = ip_len + l2_len;\n \tm->data_len = m_len;\n \tm->pkt_len = m_len;\n \treturn PKT_RX_SEC_OFFLOAD;\n@@ -322,7 +341,7 @@ otx2_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \tif ((flag & NIX_RX_OFFLOAD_SECURITY_F) &&\n \t cq->cqe_type == NIX_XQE_TYPE_RX_IPSECH) {\n \t\t*(uint64_t *)(&mbuf->rearm_data) = val;\n-\t\tol_flags |= nix_rx_sec_mbuf_update(cq, mbuf, lookup_mem);\n+\t\tol_flags |= nix_rx_sec_mbuf_update(rx, cq, mbuf, lookup_mem);\n \t\tmbuf->ol_flags = ol_flags;\n \t\treturn;\n \t}\n", "prefixes": [] }