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GET /api/patches/94842/?format=api
{ "id": 94842, "url": "https://patches.dpdk.org/api/patches/94842/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-19-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-19-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-19-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:29", "name": "[v2,18/20] crypto/cnxk: add digest support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7a020b7049800dedbfc3c604fb7228b017bf8084", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-19-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94842/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94842/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 19893A0C40;\n\tFri, 25 Jun 2021 07:59:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 99018410EA;\n\tFri, 25 Jun 2021 07:58:34 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5981F40E09\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:58:33 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5vCcu018209; Thu, 24 Jun 2021 22:58:32 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241shxb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:58:32 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:58:30 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:58:30 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 239453F7041;\n Thu, 24 Jun 2021 22:58:26 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Bpcu3RK9n656dBx6SnkZEDbu35sIYNO/RFGvUhoib8w=;\n b=Jbfi6rrSGY5Dj2FVmzSQ1uby17otLdPNfoerG9yDLYH4+14ilHyDEAcObfEp0V67QvYP\n u1zTMBy/Ud4B7kId39iMmujqhH13i5Eqoz/q+7y72z/jKLm76TY8AgU8LA90DmibrwYE\n h0GcaT+NOdI4Vp/RkLuW+DGDSzDPKX8aX7of7z8QnexNTfbmTqyw9nCl0eS3fuLBd2Os\n AWQaBEtPWoVlGNd4J3ys3amUfWHtjjm7XOvcCwCeiFPk+DeMjiQEFguLpySJVmAs1VPb\n tEuz0nzOSoB2fhr1VXNlLKkBSjLHCqyApGzc4ek9B5iLpoN8QRovPELwUt6xhISksXhm BQ==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, <dev@dpdk.org>, Anoob Joseph\n <anoobj@marvell.com>, Archana Muniganti <marchana@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:29 +0530", "Message-ID": "<1624600591-29841-19-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "MwatBPkzaVMCc-mbM4E0mspefEVvoHE2", "X-Proofpoint-ORIG-GUID": "MwatBPkzaVMCc-mbM4E0mspefEVvoHE2", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 18/20] crypto/cnxk: add digest support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tejasree Kondoj <ktejasree@marvell.com>\n\nAdd support for digest support for various algorithms.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n doc/guides/cryptodevs/features/cn10k.ini | 17 ++\n doc/guides/cryptodevs/features/cn9k.ini | 17 ++\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 18 +-\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 17 +-\n drivers/crypto/cnxk/cnxk_se.h | 340 ++++++++++++++++++++++++++++++\n 5 files changed, 407 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex c611535..77c4a2d 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -38,6 +38,23 @@ ZUC EEA3 = Y\n ; Supported authentication algorithms of 'cn10k' crypto driver.\n ;\n [Auth]\n+NULL = Y\n+AES GMAC = Y\n+KASUMI F9 = Y\n+MD5 = Y\n+MD5 HMAC = Y\n+SHA1 = Y\n+SHA1 HMAC = Y\n+SHA224 = Y\n+SHA224 HMAC = Y\n+SHA256 = Y\n+SHA256 HMAC = Y\n+SHA384 = Y\n+SHA384 HMAC = Y\n+SHA512 = Y\n+SHA512 HMAC = Y\n+SNOW3G UIA2 = Y\n+ZUC EIA3 = Y\n \n ;\n ; Supported AEAD algorithms of 'cn10k' crypto driver.\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex e833dc0..7b310e6 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -38,6 +38,23 @@ ZUC EEA3 = Y\n ; Supported authentication algorithms of 'cn9k' crypto driver.\n ;\n [Auth]\n+NULL = Y\n+AES GMAC = Y\n+KASUMI F9 = Y\n+MD5 = Y\n+MD5 HMAC = Y\n+SHA1 = Y\n+SHA1 HMAC = Y\n+SHA224 = Y\n+SHA224 HMAC = Y\n+SHA256 = Y\n+SHA256 HMAC = Y\n+SHA384 = Y\n+SHA384 HMAC = Y\n+SHA512 = Y\n+SHA512 HMAC = Y\n+SNOW3G UIA2 = Y\n+ZUC EIA3 = Y\n \n ;\n ; Supported AEAD algorithms of 'cn9k' crypto driver.\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 8af2ce9..6207627 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -53,6 +53,9 @@ cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \n \tif (cpt_op & ROC_SE_OP_CIPHER_MASK)\n \t\tret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst);\n+\telse\n+\t\tret = fill_digest_params(op, sess, &qp->meta_info, infl_req,\n+\t\t\t\t\t inst);\n \n \treturn ret;\n }\n@@ -203,7 +206,10 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,\n \tif (likely(res->compcode == CPT_COMP_GOOD ||\n \t\t res->compcode == CPT_COMP_WARN)) {\n \t\tif (unlikely(res->uc_compcode)) {\n-\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\tif (res->uc_compcode == ROC_SE_ERR_GC_ICV_MISCOMPARE)\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n \n \t\t\tplt_dp_info(\"Request failed with microcode error\");\n \t\t\tplt_dp_info(\"MC completion code 0x%x\",\n@@ -212,6 +218,16 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,\n \t\t}\n \n \t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\n+\t\t\t/* Verify authentication data if required */\n+\t\t\tif (unlikely(infl_req->op_flags &\n+\t\t\t\t CPT_OP_FLAGS_AUTH_VERIFY)) {\n+\t\t\t\tuintptr_t *rsp = infl_req->mdata;\n+\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[0],\n+\t\t\t\t\t\t rsp[1]);\n+\t\t\t}\n+\t\t}\n \t} else {\n \t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n \t\tplt_dp_info(\"HW completion code 0x%x\", res->compcode);\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex e8189d0..da13c7d 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -24,6 +24,9 @@ cn9k_cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \n \tif (cpt_op & ROC_SE_OP_CIPHER_MASK)\n \t\tret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst);\n+\telse\n+\t\tret = fill_digest_params(op, sess, &qp->meta_info, infl_req,\n+\t\t\t\t\t inst);\n \n \treturn ret;\n }\n@@ -166,7 +169,10 @@ cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop,\n \n \tif (likely(res->compcode == CPT_COMP_GOOD)) {\n \t\tif (unlikely(res->uc_compcode)) {\n-\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\tif (res->uc_compcode == ROC_SE_ERR_GC_ICV_MISCOMPARE)\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n \n \t\t\tplt_dp_info(\"Request failed with microcode error\");\n \t\t\tplt_dp_info(\"MC completion code 0x%x\",\n@@ -175,6 +181,15 @@ cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop,\n \t\t}\n \n \t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\t\t/* Verify authentication data if required */\n+\t\t\tif (unlikely(infl_req->op_flags &\n+\t\t\t\t CPT_OP_FLAGS_AUTH_VERIFY)) {\n+\t\t\t\tuintptr_t *rsp = infl_req->mdata;\n+\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[0],\n+\t\t\t\t\t\t rsp[1]);\n+\t\t\t}\n+\t\t}\n \t} else {\n \t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n \t\tplt_dp_info(\"HW completion code 0x%x\", res->compcode);\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex b1337cc..d83910f 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -212,6 +212,137 @@ fill_sg_comp_from_iov(struct roc_se_sglist_comp *list, uint32_t i,\n }\n \n static __rte_always_inline int\n+cpt_digest_gen_prep(uint32_t flags, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *params, struct cpt_inst_s *inst)\n+{\n+\tvoid *m_vaddr = params->meta_buf.vaddr;\n+\tuint32_t size, i;\n+\tuint16_t data_len, mac_len, key_len;\n+\troc_se_auth_type hash_type;\n+\tstruct roc_se_ctx *ctx;\n+\tstruct roc_se_sglist_comp *gather_comp;\n+\tstruct roc_se_sglist_comp *scatter_comp;\n+\tuint8_t *in_buffer;\n+\tuint32_t g_size_bytes, s_size_bytes;\n+\tunion cpt_inst_w4 cpt_inst_w4;\n+\n+\tctx = params->ctx_buf.vaddr;\n+\n+\thash_type = ctx->hash_type;\n+\tmac_len = ctx->mac_len;\n+\tkey_len = ctx->auth_key_len;\n+\tdata_len = ROC_SE_AUTH_DLEN(d_lens);\n+\n+\t/*GP op header */\n+\tcpt_inst_w4.s.opcode_minor = 0;\n+\tcpt_inst_w4.s.param2 = ((uint16_t)hash_type << 8);\n+\tif (ctx->hmac) {\n+\t\tcpt_inst_w4.s.opcode_major =\n+\t\t\tROC_SE_MAJOR_OP_HMAC | ROC_SE_DMA_MODE;\n+\t\tcpt_inst_w4.s.param1 = key_len;\n+\t\tcpt_inst_w4.s.dlen = data_len + RTE_ALIGN_CEIL(key_len, 8);\n+\t} else {\n+\t\tcpt_inst_w4.s.opcode_major =\n+\t\t\tROC_SE_MAJOR_OP_HASH | ROC_SE_DMA_MODE;\n+\t\tcpt_inst_w4.s.param1 = 0;\n+\t\tcpt_inst_w4.s.dlen = data_len;\n+\t}\n+\n+\t/* Null auth only case enters the if */\n+\tif (unlikely(!hash_type && !ctx->enc_cipher)) {\n+\t\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_MISC;\n+\t\t/* Minor op is passthrough */\n+\t\tcpt_inst_w4.s.opcode_minor = 0x03;\n+\t\t/* Send out completion code only */\n+\t\tcpt_inst_w4.s.param2 = 0x1;\n+\t}\n+\n+\t/* DPTR has SG list */\n+\tin_buffer = m_vaddr;\n+\n+\t((uint16_t *)in_buffer)[0] = 0;\n+\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t/* TODO Add error check if space will be sufficient */\n+\tgather_comp = (struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);\n+\n+\t/*\n+\t * Input gather list\n+\t */\n+\n+\ti = 0;\n+\n+\tif (ctx->hmac) {\n+\t\tuint64_t k_vaddr = (uint64_t)params->ctx_buf.vaddr +\n+\t\t\t\t offsetof(struct roc_se_ctx, auth_key);\n+\t\t/* Key */\n+\t\ti = fill_sg_comp(gather_comp, i, k_vaddr,\n+\t\t\t\t RTE_ALIGN_CEIL(key_len, 8));\n+\t}\n+\n+\t/* input data */\n+\tsize = data_len;\n+\tif (size) {\n+\t\ti = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0,\n+\t\t\t\t\t &size, NULL, 0);\n+\t\tif (unlikely(size)) {\n+\t\t\tplt_dp_err(\"Insufficient dst IOV size, short by %dB\",\n+\t\t\t\t size);\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * Looks like we need to support zero data\n+\t\t * gather ptr in case of hash & hmac\n+\t\t */\n+\t\ti++;\n+\t}\n+\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t/*\n+\t * Output Gather list\n+\t */\n+\n+\ti = 0;\n+\tscatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n+\t\t\t\t\t\t g_size_bytes);\n+\n+\tif (flags & ROC_SE_VALID_MAC_BUF) {\n+\t\tif (unlikely(params->mac_buf.size < mac_len)) {\n+\t\t\tplt_dp_err(\"Insufficient MAC size\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tsize = mac_len;\n+\t\ti = fill_sg_comp_from_buf_min(scatter_comp, i, ¶ms->mac_buf,\n+\t\t\t\t\t &size);\n+\t} else {\n+\t\tsize = mac_len;\n+\t\ti = fill_sg_comp_from_iov(scatter_comp, i, params->src_iov,\n+\t\t\t\t\t data_len, &size, NULL, 0);\n+\t\tif (unlikely(size)) {\n+\t\t\tplt_dp_err(\"Insufficient dst IOV size, short by %dB\",\n+\t\t\t\t size);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\tsize = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;\n+\n+\t/* This is DPTR len in case of SG mode */\n+\tcpt_inst_w4.s.dlen = size;\n+\n+\tinst->dptr = (uint64_t)in_buffer;\n+\tinst->w4.u64 = cpt_inst_w4.u64;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t\t struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)\n {\n@@ -1624,6 +1755,13 @@ cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t} else if (fc_type == ROC_SE_KASUMI) {\n \t\tret = cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, inst);\n \t}\n+\n+\t/*\n+\t * For AUTH_ONLY case,\n+\t * MC only supports digest generation and verification\n+\t * should be done in software by memcmp()\n+\t */\n+\n \treturn ret;\n }\n \n@@ -1646,6 +1784,8 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t} else if (fc_type == ROC_SE_KASUMI) {\n \t\tret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params,\n \t\t\t\t\t inst);\n+\t} else if (fc_type == ROC_SE_HASH_HMAC) {\n+\t\tret = cpt_digest_gen_prep(flags, d_lens, fc_params, inst);\n \t}\n \n \treturn ret;\n@@ -2332,4 +2472,204 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n \treturn ret;\n }\n \n+static __rte_always_inline void\n+compl_auth_verify(struct rte_crypto_op *op, uint8_t *gen_mac, uint64_t mac_len)\n+{\n+\tuint8_t *mac;\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\n+\tif (sym_op->auth.digest.data)\n+\t\tmac = sym_op->auth.digest.data;\n+\telse\n+\t\tmac = rte_pktmbuf_mtod_offset(sym_op->m_src, uint8_t *,\n+\t\t\t\t\t sym_op->auth.data.length +\n+\t\t\t\t\t\t sym_op->auth.data.offset);\n+\tif (!mac) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn;\n+\t}\n+\n+\tif (memcmp(mac, gen_mac, mac_len))\n+\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\telse\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+}\n+\n+static __rte_always_inline void\n+find_kasumif9_direction_and_length(uint8_t *src, uint32_t counter_num_bytes,\n+\t\t\t\t uint32_t *addr_length_in_bits,\n+\t\t\t\t uint8_t *addr_direction)\n+{\n+\tuint8_t found = 0;\n+\tuint32_t pos;\n+\tuint8_t last_byte;\n+\twhile (!found && counter_num_bytes > 0) {\n+\t\tcounter_num_bytes--;\n+\t\tif (src[counter_num_bytes] == 0x00)\n+\t\t\tcontinue;\n+\t\tpos = rte_bsf32(src[counter_num_bytes]);\n+\t\tif (pos == 7) {\n+\t\t\tif (likely(counter_num_bytes > 0)) {\n+\t\t\t\tlast_byte = src[counter_num_bytes - 1];\n+\t\t\t\t*addr_direction = last_byte & 0x1;\n+\t\t\t\t*addr_length_in_bits =\n+\t\t\t\t\tcounter_num_bytes * 8 - 1;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tlast_byte = src[counter_num_bytes];\n+\t\t\t*addr_direction = (last_byte >> (pos + 1)) & 0x1;\n+\t\t\t*addr_length_in_bits =\n+\t\t\t\tcounter_num_bytes * 8 + (8 - (pos + 2));\n+\t\t}\n+\t\tfound = 1;\n+\t}\n+}\n+\n+/*\n+ * This handles all auth only except AES_GMAC\n+ */\n+static __rte_always_inline int\n+fill_digest_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n+\t\t struct cpt_qp_meta_info *m_info,\n+\t\t struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst)\n+{\n+\tuint32_t space = 0;\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tvoid *mdata;\n+\tuint32_t auth_range_off;\n+\tuint32_t flags = 0;\n+\tuint64_t d_offs = 0, d_lens;\n+\tstruct rte_mbuf *m_src, *m_dst;\n+\tuint16_t auth_op = sess->cpt_op & ROC_SE_OP_AUTH_MASK;\n+\tuint16_t mac_len = sess->mac_len;\n+\tstruct roc_se_fc_params params;\n+\tchar src[SRC_IOV_SIZE];\n+\tuint8_t iv_buf[16];\n+\tint ret;\n+\n+\tmemset(¶ms, 0, sizeof(struct roc_se_fc_params));\n+\n+\tm_src = sym_op->m_src;\n+\n+\tmdata = alloc_op_meta(¶ms.meta_buf, m_info->mlen, m_info->pool,\n+\t\t\t infl_req);\n+\tif (mdata == NULL) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_exit;\n+\t}\n+\n+\tauth_range_off = sym_op->auth.data.offset;\n+\n+\tflags = ROC_SE_VALID_MAC_BUF;\n+\tparams.src_iov = (void *)src;\n+\tif (unlikely(sess->zsk_flag)) {\n+\t\t/*\n+\t\t * Since for Zuc, Kasumi, Snow3g offsets are in bits\n+\t\t * we will send pass through even for auth only case,\n+\t\t * let MC handle it\n+\t\t */\n+\t\td_offs = auth_range_off;\n+\t\tauth_range_off = 0;\n+\t\tparams.auth_iv_buf = rte_crypto_op_ctod_offset(\n+\t\t\tcop, uint8_t *, sess->auth_iv_offset);\n+\t\tif (sess->zsk_flag == ROC_SE_K_F9) {\n+\t\t\tuint32_t length_in_bits, num_bytes;\n+\t\t\tuint8_t *src, direction = 0;\n+\n+\t\t\tmemcpy(iv_buf,\n+\t\t\t rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *), 8);\n+\t\t\t/*\n+\t\t\t * This is kasumi f9, take direction from\n+\t\t\t * source buffer\n+\t\t\t */\n+\t\t\tlength_in_bits = cop->sym->auth.data.length;\n+\t\t\tnum_bytes = (length_in_bits >> 3);\n+\t\t\tsrc = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);\n+\t\t\tfind_kasumif9_direction_and_length(\n+\t\t\t\tsrc, num_bytes, &length_in_bits, &direction);\n+\t\t\tlength_in_bits -= 64;\n+\t\t\tcop->sym->auth.data.offset += 64;\n+\t\t\td_offs = cop->sym->auth.data.offset;\n+\t\t\tauth_range_off = d_offs / 8;\n+\t\t\tcop->sym->auth.data.length = length_in_bits;\n+\n+\t\t\t/* Store it at end of auth iv */\n+\t\t\tiv_buf[8] = direction;\n+\t\t\tparams.auth_iv_buf = iv_buf;\n+\t\t}\n+\t}\n+\n+\td_lens = sym_op->auth.data.length;\n+\n+\tparams.ctx_buf.vaddr = &sess->roc_se_ctx;\n+\n+\tif (auth_op == ROC_SE_OP_AUTH_GENERATE) {\n+\t\tif (sym_op->auth.digest.data) {\n+\t\t\t/*\n+\t\t\t * Digest to be generated\n+\t\t\t * in separate buffer\n+\t\t\t */\n+\t\t\tparams.mac_buf.size = sess->mac_len;\n+\t\t\tparams.mac_buf.vaddr = sym_op->auth.digest.data;\n+\t\t} else {\n+\t\t\tuint32_t off = sym_op->auth.data.offset +\n+\t\t\t\t sym_op->auth.data.length;\n+\t\t\tint32_t dlen, space;\n+\n+\t\t\tm_dst = sym_op->m_dst ? sym_op->m_dst : sym_op->m_src;\n+\t\t\tdlen = rte_pktmbuf_pkt_len(m_dst);\n+\n+\t\t\tspace = off + mac_len - dlen;\n+\t\t\tif (space > 0)\n+\t\t\t\tif (!rte_pktmbuf_append(m_dst, space)) {\n+\t\t\t\t\tplt_dp_err(\"Failed to extend \"\n+\t\t\t\t\t\t \"mbuf by %uB\",\n+\t\t\t\t\t\t space);\n+\t\t\t\t\tret = -EINVAL;\n+\t\t\t\t\tgoto free_mdata_and_exit;\n+\t\t\t\t}\n+\n+\t\t\tparams.mac_buf.vaddr =\n+\t\t\t\trte_pktmbuf_mtod_offset(m_dst, void *, off);\n+\t\t\tparams.mac_buf.size = mac_len;\n+\t\t}\n+\t} else {\n+\t\tuint64_t *op = mdata;\n+\n+\t\t/* Need space for storing generated mac */\n+\t\tspace += 2 * sizeof(uint64_t);\n+\n+\t\tparams.mac_buf.vaddr = (uint8_t *)mdata + space;\n+\t\tparams.mac_buf.size = mac_len;\n+\t\tspace += RTE_ALIGN_CEIL(mac_len, 8);\n+\t\top[0] = (uintptr_t)params.mac_buf.vaddr;\n+\t\top[1] = mac_len;\n+\t\tinfl_req->op_flags |= CPT_OP_FLAGS_AUTH_VERIFY;\n+\t}\n+\n+\tparams.meta_buf.vaddr = (uint8_t *)mdata + space;\n+\tparams.meta_buf.size -= space;\n+\n+\t/* Out of place processing */\n+\tparams.src_iov = (void *)src;\n+\n+\t/*Store SG I/O in the api for reuse */\n+\tif (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {\n+\t\tplt_dp_err(\"Prepare src iov failed\");\n+\t\tret = -EINVAL;\n+\t\tgoto free_mdata_and_exit;\n+\t}\n+\n+\tret = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, ¶ms, inst);\n+\tif (ret)\n+\t\tgoto free_mdata_and_exit;\n+\n+\treturn 0;\n+\n+free_mdata_and_exit:\n+\tif (infl_req->op_flags & CPT_OP_FLAGS_METABUF)\n+\t\trte_mempool_put(m_info->pool, infl_req->mdata);\n+err_exit:\n+\treturn ret;\n+}\n #endif /*_CNXK_SE_H_ */\n", "prefixes": [ "v2", "18/20" ] }