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GET /api/patches/94836/?format=api
{ "id": 94836, "url": "https://patches.dpdk.org/api/patches/94836/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-13-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-13-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-13-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:23", "name": "[v2,12/20] crypto/cnxk: add flexi crypto cipher encrypt", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "993d15101a06589662aef1cfb4cb3a6263761e8a", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-13-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94836/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94836/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C5BFA0C40;\n\tFri, 25 Jun 2021 07:58:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D3F34410E9;\n\tFri, 25 Jun 2021 07:58:05 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6E73D40E0F\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:58:04 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5vH78018411; Thu, 24 Jun 2021 22:58:03 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241shve-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:58:03 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:58:01 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:58:01 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 016B43F7041;\n Thu, 24 Jun 2021 22:57:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=wjS++u++TVZ2BlGjwEl0omaUh7hDGiz9NmktjgbMpdc=;\n b=IQkSxIsBJEil6TCxzC8HAmIZkpgK9zQI2HcQ5POKCk+KbAmd0GY4ClKdcI+3pNCmZgVn\n XMgDy27Z5NKrP0bEwnqYTbv/v7RMFKLspB/89UmgcOX1Gb8jSsPcHYZV4cexPpkg4o44\n WF0vaRPPm7sFXVrlSsrkeRULGaYqhICaFKS0toMAygxGxi/fNgosaj5aLSbiF7Aw/+B+\n pWtjUrUbDDlBh1iayzYO/g+unlTVgkAzXdmzfmx/tkCpuUsh+9BCzmLlELIpxr6KeMud\n 6gRXq5hZldBC0bnLHuUo08vYVs5RYJQXe0aM3upJVHE8MGlitwjGlCVDQZjdOo4sxQca Kw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Archana Muniganti <marchana@marvell.com>,\n Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph <anoobj@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:23 +0530", "Message-ID": "<1624600591-29841-13-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ydZ4kqpEJWtbHFKRZslCXnEWIWm9bS2_", "X-Proofpoint-ORIG-GUID": "ydZ4kqpEJWtbHFKRZslCXnEWIWm9bS2_", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 12/20] crypto/cnxk: add flexi crypto cipher\n encrypt", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Archana Muniganti <marchana@marvell.com>\n\nAdd flexi crypto cipher encrypt in enqueue API. Flexi crypto\nopcode covers a broad set of ciphers including variants of AES.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 14 +-\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 14 +-\n drivers/crypto/cnxk/cnxk_se.h | 818 +++++++++++++++++++++++++++++-\n 3 files changed, 833 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex ec301f4..8af2ce9 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -46,13 +46,15 @@ cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \t\t struct cnxk_se_sess *sess, struct cpt_inflight_req *infl_req,\n \t\t struct cpt_inst_s *inst)\n {\n-\tRTE_SET_USED(qp);\n-\tRTE_SET_USED(op);\n-\tRTE_SET_USED(sess);\n-\tRTE_SET_USED(infl_req);\n-\tRTE_SET_USED(inst);\n+\tuint64_t cpt_op;\n+\tint ret;\n+\n+\tcpt_op = sess->cpt_op;\n+\n+\tif (cpt_op & ROC_SE_OP_CIPHER_MASK)\n+\t\tret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst);\n \n-\treturn -ENOTSUP;\n+\treturn ret;\n }\n \n static inline int\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex 27076a8..e8189d0 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -17,13 +17,15 @@ cn9k_cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \t\t struct cpt_inflight_req *infl_req,\n \t\t struct cpt_inst_s *inst)\n {\n-\tRTE_SET_USED(qp);\n-\tRTE_SET_USED(op);\n-\tRTE_SET_USED(sess);\n-\tRTE_SET_USED(infl_req);\n-\tRTE_SET_USED(inst);\n+\tuint64_t cpt_op;\n+\tint ret;\n+\n+\tcpt_op = sess->cpt_op;\n+\n+\tif (cpt_op & ROC_SE_OP_CIPHER_MASK)\n+\t\tret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst);\n \n-\treturn -ENOTSUP;\n+\treturn ret;\n }\n \n static inline struct cnxk_se_sess *\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 57bbd70..2110f49 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -6,7 +6,15 @@\n #define _CNXK_SE_H_\n #include <stdbool.h>\n \n-#include \"roc_se.h\"\n+#include \"cnxk_cryptodev.h\"\n+#include \"cnxk_cryptodev_ops.h\"\n+\n+#define SRC_IOV_SIZE \\\n+\t(sizeof(struct roc_se_iov_ptr) + \\\n+\t (sizeof(struct roc_se_buf_ptr) * ROC_SE_MAX_SG_CNT))\n+#define DST_IOV_SIZE \\\n+\t(sizeof(struct roc_se_iov_ptr) + \\\n+\t (sizeof(struct roc_se_buf_ptr) * ROC_SE_MAX_SG_CNT))\n \n struct cnxk_se_sess {\n \tuint16_t cpt_op : 4;\n@@ -69,6 +77,457 @@ cpt_mac_len_verify(struct rte_crypto_auth_xform *auth)\n \treturn ret;\n }\n \n+static __rte_always_inline void\n+cpt_fc_salt_update(struct roc_se_ctx *se_ctx, uint8_t *salt)\n+{\n+\tstruct roc_se_context *fctx = &se_ctx->se_ctx.fctx;\n+\tmemcpy(fctx->enc.encr_iv, salt, 4);\n+}\n+\n+static __rte_always_inline uint32_t\n+fill_sg_comp(struct roc_se_sglist_comp *list, uint32_t i, phys_addr_t dma_addr,\n+\t uint32_t size)\n+{\n+\tstruct roc_se_sglist_comp *to = &list[i >> 2];\n+\n+\tto->u.s.len[i % 4] = rte_cpu_to_be_16(size);\n+\tto->ptr[i % 4] = rte_cpu_to_be_64(dma_addr);\n+\ti++;\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+fill_sg_comp_from_buf(struct roc_se_sglist_comp *list, uint32_t i,\n+\t\t struct roc_se_buf_ptr *from)\n+{\n+\tstruct roc_se_sglist_comp *to = &list[i >> 2];\n+\n+\tto->u.s.len[i % 4] = rte_cpu_to_be_16(from->size);\n+\tto->ptr[i % 4] = rte_cpu_to_be_64((uint64_t)from->vaddr);\n+\ti++;\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+fill_sg_comp_from_buf_min(struct roc_se_sglist_comp *list, uint32_t i,\n+\t\t\t struct roc_se_buf_ptr *from, uint32_t *psize)\n+{\n+\tstruct roc_se_sglist_comp *to = &list[i >> 2];\n+\tuint32_t size = *psize;\n+\tuint32_t e_len;\n+\n+\te_len = (size > from->size) ? from->size : size;\n+\tto->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);\n+\tto->ptr[i % 4] = rte_cpu_to_be_64((uint64_t)from->vaddr);\n+\t*psize -= e_len;\n+\ti++;\n+\treturn i;\n+}\n+\n+/*\n+ * This fills the MC expected SGIO list\n+ * from IOV given by user.\n+ */\n+static __rte_always_inline uint32_t\n+fill_sg_comp_from_iov(struct roc_se_sglist_comp *list, uint32_t i,\n+\t\t struct roc_se_iov_ptr *from, uint32_t from_offset,\n+\t\t uint32_t *psize, struct roc_se_buf_ptr *extra_buf,\n+\t\t uint32_t extra_offset)\n+{\n+\tint32_t j;\n+\tuint32_t extra_len = extra_buf ? extra_buf->size : 0;\n+\tuint32_t size = *psize;\n+\tstruct roc_se_buf_ptr *bufs;\n+\n+\tbufs = from->bufs;\n+\tfor (j = 0; (j < from->buf_cnt) && size; j++) {\n+\t\tuint64_t e_vaddr;\n+\t\tuint32_t e_len;\n+\t\tstruct roc_se_sglist_comp *to = &list[i >> 2];\n+\n+\t\tif (unlikely(from_offset)) {\n+\t\t\tif (from_offset >= bufs[j].size) {\n+\t\t\t\tfrom_offset -= bufs[j].size;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\te_vaddr = (uint64_t)bufs[j].vaddr + from_offset;\n+\t\t\te_len = (size > (bufs[j].size - from_offset)) ?\n+\t\t\t\t\t(bufs[j].size - from_offset) :\n+\t\t\t\t\tsize;\n+\t\t\tfrom_offset = 0;\n+\t\t} else {\n+\t\t\te_vaddr = (uint64_t)bufs[j].vaddr;\n+\t\t\te_len = (size > bufs[j].size) ? bufs[j].size : size;\n+\t\t}\n+\n+\t\tto->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);\n+\t\tto->ptr[i % 4] = rte_cpu_to_be_64(e_vaddr);\n+\n+\t\tif (extra_len && (e_len >= extra_offset)) {\n+\t\t\t/* Break the data at given offset */\n+\t\t\tuint32_t next_len = e_len - extra_offset;\n+\t\t\tuint64_t next_vaddr = e_vaddr + extra_offset;\n+\n+\t\t\tif (!extra_offset) {\n+\t\t\t\ti--;\n+\t\t\t} else {\n+\t\t\t\te_len = extra_offset;\n+\t\t\t\tsize -= e_len;\n+\t\t\t\tto->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);\n+\t\t\t}\n+\n+\t\t\textra_len = RTE_MIN(extra_len, size);\n+\t\t\t/* Insert extra data ptr */\n+\t\t\tif (extra_len) {\n+\t\t\t\ti++;\n+\t\t\t\tto = &list[i >> 2];\n+\t\t\t\tto->u.s.len[i % 4] =\n+\t\t\t\t\trte_cpu_to_be_16(extra_len);\n+\t\t\t\tto->ptr[i % 4] = rte_cpu_to_be_64(\n+\t\t\t\t\t(uint64_t)extra_buf->vaddr);\n+\t\t\t\tsize -= extra_len;\n+\t\t\t}\n+\n+\t\t\tnext_len = RTE_MIN(next_len, size);\n+\t\t\t/* insert the rest of the data */\n+\t\t\tif (next_len) {\n+\t\t\t\ti++;\n+\t\t\t\tto = &list[i >> 2];\n+\t\t\t\tto->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);\n+\t\t\t\tto->ptr[i % 4] = rte_cpu_to_be_64(next_vaddr);\n+\t\t\t\tsize -= next_len;\n+\t\t\t}\n+\t\t\textra_len = 0;\n+\n+\t\t} else {\n+\t\t\tsize -= e_len;\n+\t\t}\n+\t\tif (extra_offset)\n+\t\t\textra_offset -= size;\n+\t\ti++;\n+\t}\n+\n+\t*psize = size;\n+\treturn (uint32_t)i;\n+}\n+\n+static __rte_always_inline int\n+cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)\n+{\n+\tuint32_t iv_offset = 0;\n+\tint32_t inputlen, outputlen, enc_dlen, auth_dlen;\n+\tstruct roc_se_ctx *se_ctx;\n+\tuint32_t cipher_type, hash_type;\n+\tuint32_t mac_len, size;\n+\tuint8_t iv_len = 16;\n+\tstruct roc_se_buf_ptr *aad_buf = NULL;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len, aad_len = 0;\n+\tuint32_t passthrough_len = 0;\n+\tunion cpt_inst_w4 cpt_inst_w4;\n+\tvoid *offset_vaddr;\n+\tuint8_t op_minor;\n+\n+\tencr_offset = ROC_SE_ENCR_OFFSET(d_offs);\n+\tauth_offset = ROC_SE_AUTH_OFFSET(d_offs);\n+\tencr_data_len = ROC_SE_ENCR_DLEN(d_lens);\n+\tauth_data_len = ROC_SE_AUTH_DLEN(d_lens);\n+\tif (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {\n+\t\t/* We don't support both AAD and auth data separately */\n+\t\tauth_data_len = 0;\n+\t\tauth_offset = 0;\n+\t\taad_len = fc_params->aad_buf.size;\n+\t\taad_buf = &fc_params->aad_buf;\n+\t}\n+\tse_ctx = fc_params->ctx_buf.vaddr;\n+\tcipher_type = se_ctx->enc_cipher;\n+\thash_type = se_ctx->hash_type;\n+\tmac_len = se_ctx->mac_len;\n+\top_minor = se_ctx->template_w4.s.opcode_minor;\n+\n+\tif (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {\n+\t\tiv_len = 0;\n+\t\tiv_offset = ROC_SE_ENCR_IV_OFFSET(d_offs);\n+\t}\n+\n+\tif (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * When AAD is given, data above encr_offset is pass through\n+\t\t * Since AAD is given as separate pointer and not as offset,\n+\t\t * this is a special case as we need to fragment input data\n+\t\t * into passthrough + encr_data and then insert AAD in between.\n+\t\t */\n+\t\tif (hash_type != ROC_SE_GMAC_TYPE) {\n+\t\t\tpassthrough_len = encr_offset;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tencr_offset = passthrough_len + aad_len + iv_len;\n+\t\t\tauth_data_len = aad_len + encr_data_len;\n+\t\t} else {\n+\t\t\tpassthrough_len = 16 + aad_len;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tauth_data_len = aad_len;\n+\t\t}\n+\t} else {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/* Encryption */\n+\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;\n+\tcpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_ENCRYPT;\n+\tcpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;\n+\n+\tif (hash_type == ROC_SE_GMAC_TYPE) {\n+\t\tencr_offset = 0;\n+\t\tencr_data_len = 0;\n+\t}\n+\n+\tauth_dlen = auth_offset + auth_data_len;\n+\tenc_dlen = encr_data_len + encr_offset;\n+\tif (unlikely(encr_data_len & 0xf)) {\n+\t\tif ((cipher_type == ROC_SE_DES3_CBC) ||\n+\t\t (cipher_type == ROC_SE_DES3_ECB))\n+\t\t\tenc_dlen =\n+\t\t\t\tRTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;\n+\t\telse if (likely((cipher_type == ROC_SE_AES_CBC) ||\n+\t\t\t\t(cipher_type == ROC_SE_AES_ECB)))\n+\t\t\tenc_dlen =\n+\t\t\t\tRTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;\n+\t}\n+\n+\tif (unlikely(auth_dlen > enc_dlen)) {\n+\t\tinputlen = auth_dlen;\n+\t\toutputlen = auth_dlen + mac_len;\n+\t} else {\n+\t\tinputlen = enc_dlen;\n+\t\toutputlen = enc_dlen + mac_len;\n+\t}\n+\n+\tif (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)\n+\t\toutputlen = enc_dlen;\n+\n+\t/* GP op header */\n+\tcpt_inst_w4.s.param1 = encr_data_len;\n+\tcpt_inst_w4.s.param2 = auth_data_len;\n+\n+\t/*\n+\t * In cn9k, cn10k since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) &&\n+\t\t (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\n+\t\t/* Use Direct mode */\n+\n+\t\toffset_vaddr =\n+\t\t\t(uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - iv_len;\n+\n+\t\t/* DPTR */\n+\t\tinst->dptr = (uint64_t)offset_vaddr;\n+\n+\t\t/* RPTR should just exclude offset control word */\n+\t\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n+\n+\t\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t} else {\n+\t\tvoid *m_vaddr = fc_params->meta_buf.vaddr;\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tstruct roc_se_sglist_comp *gather_comp;\n+\t\tstruct roc_se_sglist_comp *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\n+\t\t/* This falls under strict SG mode */\n+\t\toffset_vaddr = m_vaddr;\n+\t\tsize = ROC_SE_OFF_CTRL_LEN + iv_len;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\n+\t\tcpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\n+\t\ti = 0;\n+\n+\t\t/* Offset control word that includes iv */\n+\t\ti = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,\n+\t\t\t\t ROC_SE_OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* Add input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (likely(size)) {\n+\t\t\tuint32_t aad_offset = aad_len ? passthrough_len : 0;\n+\n+\t\t\tif (unlikely(flags & ROC_SE_SINGLE_BUF_INPLACE)) {\n+\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\tgather_comp, i, fc_params->bufs, &size);\n+\t\t\t} else {\n+\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\tgather_comp, i, fc_params->src_iov, 0,\n+\t\t\t\t\t&size, aad_buf, aad_offset);\n+\t\t\t}\n+\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d needed\",\n+\t\t\t\t\t size);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\t/*\n+\t\t * Output Scatter list\n+\t\t */\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n+\t\t\t\t\t\t g_size_bytes);\n+\n+\t\t/* Add IV */\n+\t\tif (likely(iv_len)) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t (uint64_t)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* output data or output data + digest*/\n+\t\tif (unlikely(flags & ROC_SE_VALID_MAC_BUF)) {\n+\t\t\tsize = outputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(flags &\n+\t\t\t\t\t ROC_SE_SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\tscatter_comp, i,\n+\t\t\t\t\t\tfc_params->bufs, &size);\n+\t\t\t\t} else {\n+\t\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\t\tscatter_comp, i,\n+\t\t\t\t\t\tfc_params->dst_iov, 0, &size,\n+\t\t\t\t\t\taad_buf, aad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (unlikely(size)) {\n+\t\t\t\t\tplt_dp_err(\"Insufficient buffer\"\n+\t\t\t\t\t\t \" space, size %d needed\",\n+\t\t\t\t\t\t size);\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\t/* mac_data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(scatter_comp, i,\n+\t\t\t\t\t\t\t &fc_params->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Output including mac */\n+\t\t\tsize = outputlen - iv_len;\n+\t\t\tif (likely(size)) {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(flags &\n+\t\t\t\t\t ROC_SE_SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\tscatter_comp, i,\n+\t\t\t\t\t\tfc_params->bufs, &size);\n+\t\t\t\t} else {\n+\t\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\t\tscatter_comp, i,\n+\t\t\t\t\t\tfc_params->dst_iov, 0, &size,\n+\t\t\t\t\t\taad_buf, aad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (unlikely(size)) {\n+\t\t\t\t\tplt_dp_err(\"Insufficient buffer\"\n+\t\t\t\t\t\t \" space, size %d needed\",\n+\t\t\t\t\t\t size);\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len in case of SG mode */\n+\t\tcpt_inst_w4.s.dlen = size;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t}\n+\n+\tif (unlikely((encr_offset >> 16) || (iv_offset >> 8) ||\n+\t\t (auth_offset >> 8))) {\n+\t\tplt_dp_err(\"Offset not supported\");\n+\t\tplt_dp_err(\"enc_offset: %d\", encr_offset);\n+\t\tplt_dp_err(\"iv_offset : %d\", iv_offset);\n+\t\tplt_dp_err(\"auth_offset: %d\", auth_offset);\n+\t\treturn -1;\n+\t}\n+\n+\t*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(\n+\t\t((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) |\n+\t\t((uint64_t)auth_offset));\n+\n+\tinst->w4.u64 = cpt_inst_w4.u64;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *fc_params,\n+\t\t struct cpt_inst_s *inst)\n+{\n+\tstruct roc_se_ctx *ctx = fc_params->ctx_buf.vaddr;\n+\tuint8_t fc_type;\n+\tint ret = -1;\n+\n+\tfc_type = ctx->fc_type;\n+\n+\tif (likely(fc_type == ROC_SE_FC_GEN))\n+\t\tret = cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, inst);\n+\n+\treturn ret;\n+}\n+\n static __rte_always_inline int\n fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n {\n@@ -392,4 +851,361 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \treturn 0;\n }\n \n+static __rte_always_inline void *\n+alloc_op_meta(struct roc_se_buf_ptr *buf, int32_t len,\n+\t struct rte_mempool *cpt_meta_pool,\n+\t struct cpt_inflight_req *infl_req)\n+{\n+\tuint8_t *mdata;\n+\n+\tif (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))\n+\t\treturn NULL;\n+\n+\tbuf->vaddr = mdata;\n+\tbuf->size = len;\n+\n+\tinfl_req->mdata = mdata;\n+\tinfl_req->op_flags |= CPT_OP_FLAGS_METABUF;\n+\n+\treturn mdata;\n+}\n+\n+static __rte_always_inline uint32_t\n+prepare_iov_from_pkt(struct rte_mbuf *pkt, struct roc_se_iov_ptr *iovec,\n+\t\t uint32_t start_offset)\n+{\n+\tuint16_t index = 0;\n+\tvoid *seg_data = NULL;\n+\tint32_t seg_size = 0;\n+\n+\tif (!pkt) {\n+\t\tiovec->buf_cnt = 0;\n+\t\treturn 0;\n+\t}\n+\n+\tif (!start_offset) {\n+\t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\t\tseg_size = pkt->data_len;\n+\t} else {\n+\t\twhile (start_offset >= pkt->data_len) {\n+\t\t\tstart_offset -= pkt->data_len;\n+\t\t\tpkt = pkt->next;\n+\t\t}\n+\n+\t\tseg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);\n+\t\tseg_size = pkt->data_len - start_offset;\n+\t\tif (!seg_size)\n+\t\t\treturn 1;\n+\t}\n+\n+\t/* first seg */\n+\tiovec->bufs[index].vaddr = seg_data;\n+\tiovec->bufs[index].size = seg_size;\n+\tindex++;\n+\tpkt = pkt->next;\n+\n+\twhile (unlikely(pkt != NULL)) {\n+\t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\t\tseg_size = pkt->data_len;\n+\t\tif (!seg_size)\n+\t\t\tbreak;\n+\n+\t\tiovec->bufs[index].vaddr = seg_data;\n+\t\tiovec->bufs[index].size = seg_size;\n+\n+\t\tindex++;\n+\n+\t\tpkt = pkt->next;\n+\t}\n+\n+\tiovec->buf_cnt = index;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline uint32_t\n+prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,\n+\t\t\t struct roc_se_fc_params *param, uint32_t *flags)\n+{\n+\tuint16_t index = 0;\n+\tvoid *seg_data = NULL;\n+\tuint32_t seg_size = 0;\n+\tstruct roc_se_iov_ptr *iovec;\n+\n+\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\tseg_size = pkt->data_len;\n+\n+\t/* first seg */\n+\tif (likely(!pkt->next)) {\n+\t\tuint32_t headroom;\n+\n+\t\t*flags |= ROC_SE_SINGLE_BUF_INPLACE;\n+\t\theadroom = rte_pktmbuf_headroom(pkt);\n+\t\tif (likely(headroom >= 24))\n+\t\t\t*flags |= ROC_SE_SINGLE_BUF_HEADROOM;\n+\n+\t\tparam->bufs[0].vaddr = seg_data;\n+\t\tparam->bufs[0].size = seg_size;\n+\t\treturn 0;\n+\t}\n+\tiovec = param->src_iov;\n+\tiovec->bufs[index].vaddr = seg_data;\n+\tiovec->bufs[index].size = seg_size;\n+\tindex++;\n+\tpkt = pkt->next;\n+\n+\twhile (unlikely(pkt != NULL)) {\n+\t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\t\tseg_size = pkt->data_len;\n+\n+\t\tif (!seg_size)\n+\t\t\tbreak;\n+\n+\t\tiovec->bufs[index].vaddr = seg_data;\n+\t\tiovec->bufs[index].size = seg_size;\n+\n+\t\tindex++;\n+\n+\t\tpkt = pkt->next;\n+\t}\n+\n+\tiovec->buf_cnt = index;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n+\t struct cpt_qp_meta_info *m_info,\n+\t struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst)\n+{\n+\tstruct roc_se_ctx *ctx = &sess->roc_se_ctx;\n+\tuint8_t op_minor = ctx->template_w4.s.opcode_minor;\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tvoid *mdata = NULL;\n+\tuint32_t mc_hash_off;\n+\tuint32_t flags = 0;\n+\tuint64_t d_offs, d_lens;\n+\tstruct rte_mbuf *m_src, *m_dst;\n+\tuint8_t cpt_op = sess->cpt_op;\n+#ifdef CPT_ALWAYS_USE_SG_MODE\n+\tuint8_t inplace = 0;\n+#else\n+\tuint8_t inplace = 1;\n+#endif\n+\tstruct roc_se_fc_params fc_params;\n+\tchar src[SRC_IOV_SIZE];\n+\tchar dst[SRC_IOV_SIZE];\n+\tuint32_t iv_buf[4];\n+\tint ret;\n+\n+\tif (likely(sess->iv_length)) {\n+\t\tflags |= ROC_SE_VALID_IV_BUF;\n+\t\tfc_params.iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *,\n+\t\t\t\t\t\t\t sess->iv_offset);\n+\t\tif (sess->aes_ctr && unlikely(sess->iv_length != 16)) {\n+\t\t\tmemcpy((uint8_t *)iv_buf,\n+\t\t\t rte_crypto_op_ctod_offset(cop, uint8_t *,\n+\t\t\t\t\t\t\t sess->iv_offset),\n+\t\t\t 12);\n+\t\t\tiv_buf[3] = rte_cpu_to_be_32(0x1);\n+\t\t\tfc_params.iv_buf = iv_buf;\n+\t\t}\n+\t}\n+\n+\tif (sess->zsk_flag) {\n+\t\tfc_params.auth_iv_buf = rte_crypto_op_ctod_offset(\n+\t\t\tcop, uint8_t *, sess->auth_iv_offset);\n+\t\tif (sess->zsk_flag != ROC_SE_ZS_EA)\n+\t\t\tinplace = 0;\n+\t}\n+\tm_src = sym_op->m_src;\n+\tm_dst = sym_op->m_dst;\n+\n+\tif (sess->aes_gcm || sess->chacha_poly) {\n+\t\tuint8_t *salt;\n+\t\tuint8_t *aad_data;\n+\t\tuint16_t aad_len;\n+\n+\t\td_offs = sym_op->aead.data.offset;\n+\t\td_lens = sym_op->aead.data.length;\n+\t\tmc_hash_off =\n+\t\t\tsym_op->aead.data.offset + sym_op->aead.data.length;\n+\n+\t\taad_data = sym_op->aead.aad.data;\n+\t\taad_len = sess->aad_length;\n+\t\tif (likely((aad_data + aad_len) ==\n+\t\t\t rte_pktmbuf_mtod_offset(m_src, uint8_t *,\n+\t\t\t\t\t\t sym_op->aead.data.offset))) {\n+\t\t\td_offs = (d_offs - aad_len) | (d_offs << 16);\n+\t\t\td_lens = (d_lens + aad_len) | (d_lens << 32);\n+\t\t} else {\n+\t\t\tfc_params.aad_buf.vaddr = sym_op->aead.aad.data;\n+\t\t\tfc_params.aad_buf.size = aad_len;\n+\t\t\tflags |= ROC_SE_VALID_AAD_BUF;\n+\t\t\tinplace = 0;\n+\t\t\td_offs = d_offs << 16;\n+\t\t\td_lens = d_lens << 32;\n+\t\t}\n+\n+\t\tsalt = fc_params.iv_buf;\n+\t\tif (unlikely(*(uint32_t *)salt != sess->salt)) {\n+\t\t\tcpt_fc_salt_update(&sess->roc_se_ctx, salt);\n+\t\t\tsess->salt = *(uint32_t *)salt;\n+\t\t}\n+\t\tfc_params.iv_buf = salt + 4;\n+\t\tif (likely(sess->mac_len)) {\n+\t\t\tstruct rte_mbuf *m =\n+\t\t\t\t(cpt_op & ROC_SE_OP_ENCODE) ? m_dst : m_src;\n+\n+\t\t\tif (!m)\n+\t\t\t\tm = m_src;\n+\n+\t\t\t/* hmac immediately following data is best case */\n+\t\t\tif (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +\n+\t\t\t\t\t mc_hash_off !=\n+\t\t\t\t (uint8_t *)sym_op->aead.digest.data)) {\n+\t\t\t\tflags |= ROC_SE_VALID_MAC_BUF;\n+\t\t\t\tfc_params.mac_buf.size = sess->mac_len;\n+\t\t\t\tfc_params.mac_buf.vaddr =\n+\t\t\t\t\tsym_op->aead.digest.data;\n+\t\t\t\tinplace = 0;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\td_offs = sym_op->cipher.data.offset;\n+\t\td_lens = sym_op->cipher.data.length;\n+\t\tmc_hash_off =\n+\t\t\tsym_op->cipher.data.offset + sym_op->cipher.data.length;\n+\t\td_offs = (d_offs << 16) | sym_op->auth.data.offset;\n+\t\td_lens = (d_lens << 32) | sym_op->auth.data.length;\n+\n+\t\tif (mc_hash_off <\n+\t\t (sym_op->auth.data.offset + sym_op->auth.data.length)) {\n+\t\t\tmc_hash_off = (sym_op->auth.data.offset +\n+\t\t\t\t sym_op->auth.data.length);\n+\t\t}\n+\t\t/* for gmac, salt should be updated like in gcm */\n+\t\tif (unlikely(sess->is_gmac)) {\n+\t\t\tuint8_t *salt;\n+\t\t\tsalt = fc_params.iv_buf;\n+\t\t\tif (unlikely(*(uint32_t *)salt != sess->salt)) {\n+\t\t\t\tcpt_fc_salt_update(&sess->roc_se_ctx, salt);\n+\t\t\t\tsess->salt = *(uint32_t *)salt;\n+\t\t\t}\n+\t\t\tfc_params.iv_buf = salt + 4;\n+\t\t}\n+\t\tif (likely(sess->mac_len)) {\n+\t\t\tstruct rte_mbuf *m;\n+\n+\t\t\tm = (cpt_op & ROC_SE_OP_ENCODE) ? m_dst : m_src;\n+\t\t\tif (!m)\n+\t\t\t\tm = m_src;\n+\n+\t\t\t/* hmac immediately following data is best case */\n+\t\t\tif (!(op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST) &&\n+\t\t\t (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +\n+\t\t\t\t\t mc_hash_off !=\n+\t\t\t\t (uint8_t *)sym_op->auth.digest.data))) {\n+\t\t\t\tflags |= ROC_SE_VALID_MAC_BUF;\n+\t\t\t\tfc_params.mac_buf.size = sess->mac_len;\n+\t\t\t\tfc_params.mac_buf.vaddr =\n+\t\t\t\t\tsym_op->auth.digest.data;\n+\t\t\t\tinplace = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tfc_params.ctx_buf.vaddr = &sess->roc_se_ctx;\n+\n+\tif (!(op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST) &&\n+\t unlikely(sess->is_null || sess->cpt_op == ROC_SE_OP_DECODE))\n+\t\tinplace = 0;\n+\n+\tif (likely(!m_dst && inplace)) {\n+\t\t/* Case of single buffer without AAD buf or\n+\t\t * separate mac buf in place and\n+\t\t * not air crypto\n+\t\t */\n+\t\tfc_params.dst_iov = fc_params.src_iov = (void *)src;\n+\n+\t\tif (unlikely(prepare_iov_from_pkt_inplace(m_src, &fc_params,\n+\t\t\t\t\t\t\t &flags))) {\n+\t\t\tplt_dp_err(\"Prepare inplace src iov failed\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t} else {\n+\t\t/* Out of place processing */\n+\t\tfc_params.src_iov = (void *)src;\n+\t\tfc_params.dst_iov = (void *)dst;\n+\n+\t\t/* Store SG I/O in the api for reuse */\n+\t\tif (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {\n+\t\t\tplt_dp_err(\"Prepare src iov failed\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t\tif (unlikely(m_dst != NULL)) {\n+\t\t\tuint32_t pkt_len;\n+\n+\t\t\t/* Try to make room as much as src has */\n+\t\t\tpkt_len = rte_pktmbuf_pkt_len(m_dst);\n+\n+\t\t\tif (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {\n+\t\t\t\tpkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;\n+\t\t\t\tif (!rte_pktmbuf_append(m_dst, pkt_len)) {\n+\t\t\t\t\tplt_dp_err(\"Not enough space in \"\n+\t\t\t\t\t\t \"m_dst %p, need %u\"\n+\t\t\t\t\t\t \" more\",\n+\t\t\t\t\t\t m_dst, pkt_len);\n+\t\t\t\t\tret = -EINVAL;\n+\t\t\t\t\tgoto err_exit;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {\n+\t\t\t\tplt_dp_err(\"Prepare dst iov failed for \"\n+\t\t\t\t\t \"m_dst %p\",\n+\t\t\t\t\t m_dst);\n+\t\t\t\tret = -EINVAL;\n+\t\t\t\tgoto err_exit;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfc_params.dst_iov = (void *)src;\n+\t\t}\n+\t}\n+\n+\tif (unlikely(!((flags & ROC_SE_SINGLE_BUF_INPLACE) &&\n+\t\t (flags & ROC_SE_SINGLE_BUF_HEADROOM) &&\n+\t\t ((ctx->fc_type == ROC_SE_FC_GEN) ||\n+\t\t\t(ctx->fc_type == ROC_SE_PDCP))))) {\n+\t\tmdata = alloc_op_meta(&fc_params.meta_buf, m_info->mlen,\n+\t\t\t\t m_info->pool, infl_req);\n+\t\tif (mdata == NULL) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\t/* Finally prepare the instruction */\n+\tif (cpt_op & ROC_SE_OP_ENCODE)\n+\t\tret = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, &fc_params,\n+\t\t\t\t\t inst);\n+\telse\n+\t\tret = ENOTSUP;\n+\n+\tif (unlikely(ret)) {\n+\t\tplt_dp_err(\"Preparing request failed due to bad input arg\");\n+\t\tgoto free_mdata_and_exit;\n+\t}\n+\n+\treturn 0;\n+\n+free_mdata_and_exit:\n+\tif (infl_req->op_flags & CPT_OP_FLAGS_METABUF)\n+\t\trte_mempool_put(m_info->pool, infl_req->mdata);\n+err_exit:\n+\treturn ret;\n+}\n+\n #endif /*_CNXK_SE_H_ */\n", "prefixes": [ "v2", "12/20" ] }