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GET /api/patches/94831/?format=api
{ "id": 94831, "url": "https://patches.dpdk.org/api/patches/94831/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-8-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-8-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-8-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:18", "name": "[v2,07/20] crypto/cnxk: add dequeue burst op", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "370a512000de384327025d0684df8e51cdb43298", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-8-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94831/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94831/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 196E7A0C40;\n\tFri, 25 Jun 2021 07:58:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AE12B41102;\n\tFri, 25 Jun 2021 07:57:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 2D42340E25\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:57:39 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5nxkH007987; Thu, 24 Jun 2021 22:57:38 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39d24dhk1r-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:57:38 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:57:36 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:57:36 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 917DE3F7041;\n Thu, 24 Jun 2021 22:57:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ckwI5lqdupf0gsEHTKL9GeWdZVdox2rsTC5luoVcDrs=;\n b=Tf+IchrEZ2nvUqJoFuicwXwiwh35WnCjaIOScbTrjpLwDMUTbrgH7BttDQc0hEDI3hs2\n tkhJgHJ7gzKs8ocMTpkQKqzkyF1jyW/hhTjfIO2EjCkGPUBX0wHx24lEl0aqPp3PUObD\n ZFgo31jPFPmJ+6zVIWwxd1Cm1upqZ4mJismBLef/ZiCdF6NHk+1fPuOdrHt4An9fNNdp\n /Ny0PIMI7BR9Dp27ImEQIz5DAsfltRMCo30J+lC3TVlN8H+rvLgj4jgS6Bk7nN2rlyHb\n UNuEkRllWkZKgA1N5As1BtAs7RGY+TgMhya4Dz+MkjJD2+iC6cM4usxgQBrkiAFSjoSb hw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n \"Ankur Dwivedi\" <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Archana Muniganti\n <marchana@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:18 +0530", "Message-ID": "<1624600591-29841-8-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "eay93H_mC08NKPauM9vgrCt9qKFqX7Gn", "X-Proofpoint-ORIG-GUID": "eay93H_mC08NKPauM9vgrCt9qKFqX7Gn", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 07/20] crypto/cnxk: add dequeue burst op", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add dequeue_burst op in cn9k & cn10k.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n doc/guides/cryptodevs/features/cn10k.ini | 3 +\n doc/guides/cryptodevs/features/cn9k.ini | 3 +\n drivers/crypto/cnxk/cn10k_cryptodev.c | 4 ++\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 105 ++++++++++++++++++++++++++++++\n drivers/crypto/cnxk/cn9k_cryptodev.c | 4 ++\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 103 +++++++++++++++++++++++++++++\n 6 files changed, 222 insertions(+)", "diff": "diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex 0aa097d..7f433fa 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -4,6 +4,9 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Symmetric crypto = Y\n+HW Accelerated = Y\n+Symmetric sessionless = Y\n \n ;\n ; Supported crypto algorithms of 'cn10k' crypto driver.\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex 64ee929..9c9d54d 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -4,6 +4,9 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Symmetric crypto = Y\n+HW Accelerated = Y\n+Symmetric sessionless = Y\n \n ;\n ; Supported crypto algorithms of 'cn9k' crypto driver.\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c\nindex 53f7a94..31addc0 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c\n@@ -80,6 +80,10 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->dev_ops = &cn10k_cpt_ops;\n \tdev->driver_id = cn10k_cryptodev_driver_id;\n \n+\tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\t RTE_CRYPTODEV_FF_SYM_SESSIONLESS;\n+\n \tcn10k_cpt_set_enqdeq_fns(dev);\n \n \treturn 0;\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 5dd2cd2..ec301f4 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -190,10 +190,115 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \treturn count + i;\n }\n \n+static inline void\n+cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,\n+\t\t\t struct rte_crypto_op *cop,\n+\t\t\t struct cpt_inflight_req *infl_req)\n+{\n+\tstruct cpt_cn10k_res_s *res = (struct cpt_cn10k_res_s *)&infl_req->res;\n+\tunsigned int sz;\n+\n+\tif (likely(res->compcode == CPT_COMP_GOOD ||\n+\t\t res->compcode == CPT_COMP_WARN)) {\n+\t\tif (unlikely(res->uc_compcode)) {\n+\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\n+\t\t\tplt_dp_info(\"Request failed with microcode error\");\n+\t\t\tplt_dp_info(\"MC completion code 0x%x\",\n+\t\t\t\t res->uc_compcode);\n+\t\t\tgoto temp_sess_free;\n+\t\t}\n+\n+\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t} else {\n+\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\tplt_dp_info(\"HW completion code 0x%x\", res->compcode);\n+\n+\t\tswitch (res->compcode) {\n+\t\tcase CPT_COMP_INSTERR:\n+\t\t\tplt_dp_err(\"Request failed with instruction error\");\n+\t\t\tbreak;\n+\t\tcase CPT_COMP_FAULT:\n+\t\t\tplt_dp_err(\"Request failed with DMA fault\");\n+\t\t\tbreak;\n+\t\tcase CPT_COMP_HWERR:\n+\t\t\tplt_dp_err(\"Request failed with hardware error\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tplt_dp_err(\n+\t\t\t\t\"Request failed with unknown completion code\");\n+\t\t}\n+\t}\n+\n+temp_sess_free:\n+\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\t\tsym_session_clear(cn10k_cryptodev_driver_id,\n+\t\t\t\t\t cop->sym->session);\n+\t\t\tsz = rte_cryptodev_sym_get_existing_header_session_size(\n+\t\t\t\tcop->sym->session);\n+\t\t\tmemset(cop->sym->session, 0, sz);\n+\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n+\t\t\tcop->sym->session = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static uint16_t\n+cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct cpt_inflight_req *infl_req;\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tstruct cpt_cn10k_res_s *res;\n+\tstruct rte_crypto_op *cop;\n+\tint i, nb_pending;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tnb_pending = pend_q->pending_count;\n+\n+\tif (nb_ops > nb_pending)\n+\t\tnb_ops = nb_pending;\n+\n+\tfor (i = 0; i < nb_ops; i++) {\n+\t\tinfl_req = &pend_q->req_queue[pend_q->deq_head];\n+\n+\t\tres = (struct cpt_cn10k_res_s *)&infl_req->res;\n+\n+\t\tif (unlikely(res->compcode == CPT_COMP_NOT_DONE)) {\n+\t\t\tif (unlikely(rte_get_timer_cycles() >\n+\t\t\t\t pend_q->time_out)) {\n+\t\t\t\tplt_err(\"Request timed out\");\n+\t\t\t\tpend_q->time_out = rte_get_timer_cycles() +\n+\t\t\t\t\t\t DEFAULT_COMMAND_TIMEOUT *\n+\t\t\t\t\t\t\t rte_get_timer_hz();\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tMOD_INC(pend_q->deq_head, qp->lf.nb_desc);\n+\n+\t\tcop = infl_req->cop;\n+\n+\t\tops[i] = cop;\n+\n+\t\tcn10k_cpt_dequeue_post_process(qp, cop, infl_req);\n+\n+\t\tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))\n+\t\t\trte_mempool_put(qp->meta_info.pool, infl_req->mdata);\n+\t}\n+\n+\tpend_q->pending_count -= i;\n+\n+\treturn i;\n+}\n+\n void\n cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)\n {\n \tdev->enqueue_burst = cn10k_cpt_enqueue_burst;\n+\tdev->dequeue_burst = cn10k_cpt_dequeue_burst;\n \n \trte_mb();\n }\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c\nindex 4dbb40d..7908896 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c\n@@ -78,6 +78,10 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->dev_ops = &cn9k_cpt_ops;\n \tdev->driver_id = cn9k_cryptodev_driver_id;\n \n+\tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\t RTE_CRYPTODEV_FF_SYM_SESSIONLESS;\n+\n \tcn9k_cpt_set_enqdeq_fns(dev);\n \n \treturn 0;\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex f09f9ee..27076a8 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -155,10 +155,113 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \treturn count;\n }\n \n+static inline void\n+cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop,\n+\t\t\t struct cpt_inflight_req *infl_req)\n+{\n+\tstruct cpt_cn9k_res_s *res = (struct cpt_cn9k_res_s *)&infl_req->res;\n+\tunsigned int sz;\n+\n+\tif (likely(res->compcode == CPT_COMP_GOOD)) {\n+\t\tif (unlikely(res->uc_compcode)) {\n+\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\n+\t\t\tplt_dp_info(\"Request failed with microcode error\");\n+\t\t\tplt_dp_info(\"MC completion code 0x%x\",\n+\t\t\t\t res->uc_compcode);\n+\t\t\tgoto temp_sess_free;\n+\t\t}\n+\n+\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t} else {\n+\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\tplt_dp_info(\"HW completion code 0x%x\", res->compcode);\n+\n+\t\tswitch (res->compcode) {\n+\t\tcase CPT_COMP_INSTERR:\n+\t\t\tplt_dp_err(\"Request failed with instruction error\");\n+\t\t\tbreak;\n+\t\tcase CPT_COMP_FAULT:\n+\t\t\tplt_dp_err(\"Request failed with DMA fault\");\n+\t\t\tbreak;\n+\t\tcase CPT_COMP_HWERR:\n+\t\t\tplt_dp_err(\"Request failed with hardware error\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tplt_dp_err(\n+\t\t\t\t\"Request failed with unknown completion code\");\n+\t\t}\n+\t}\n+\n+temp_sess_free:\n+\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\t\tsym_session_clear(cn9k_cryptodev_driver_id,\n+\t\t\t\t\t cop->sym->session);\n+\t\t\tsz = rte_cryptodev_sym_get_existing_header_session_size(\n+\t\t\t\tcop->sym->session);\n+\t\t\tmemset(cop->sym->session, 0, sz);\n+\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n+\t\t\tcop->sym->session = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static uint16_t\n+cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tstruct cpt_inflight_req *infl_req;\n+\tstruct cpt_cn9k_res_s *res;\n+\tstruct rte_crypto_op *cop;\n+\tuint32_t pq_deq_head;\n+\tint i;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tnb_ops = RTE_MIN(nb_ops, pend_q->pending_count);\n+\n+\tpq_deq_head = pend_q->deq_head;\n+\n+\tfor (i = 0; i < nb_ops; i++) {\n+\t\tinfl_req = &pend_q->req_queue[pq_deq_head];\n+\n+\t\tres = (struct cpt_cn9k_res_s *)&infl_req->res;\n+\n+\t\tif (unlikely(res->compcode == CPT_COMP_NOT_DONE)) {\n+\t\t\tif (unlikely(rte_get_timer_cycles() >\n+\t\t\t\t pend_q->time_out)) {\n+\t\t\t\tplt_err(\"Request timed out\");\n+\t\t\t\tpend_q->time_out = rte_get_timer_cycles() +\n+\t\t\t\t\t\t DEFAULT_COMMAND_TIMEOUT *\n+\t\t\t\t\t\t\t rte_get_timer_hz();\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tMOD_INC(pq_deq_head, qp->lf.nb_desc);\n+\n+\t\tcop = infl_req->cop;\n+\n+\t\tops[i] = cop;\n+\n+\t\tcn9k_cpt_dequeue_post_process(qp, cop, infl_req);\n+\n+\t\tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))\n+\t\t\trte_mempool_put(qp->meta_info.pool, infl_req->mdata);\n+\t}\n+\n+\tpend_q->pending_count -= i;\n+\tpend_q->deq_head = pq_deq_head;\n+\n+\treturn i;\n+}\n void\n cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)\n {\n \tdev->enqueue_burst = cn9k_cpt_enqueue_burst;\n+\tdev->dequeue_burst = cn9k_cpt_dequeue_burst;\n \n \trte_mb();\n }\n", "prefixes": [ "v2", "07/20" ] }