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GET /api/patches/94825/?format=api
{ "id": 94825, "url": "https://patches.dpdk.org/api/patches/94825/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-2-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-2-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-2-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:12", "name": "[v2,01/20] crypto/cnxk: add driver skeleton", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a1d212df68a01e5289857d8b1a342a2981ea220c", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-2-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94825/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/94825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D40A7A0C40;\n\tFri, 25 Jun 2021 07:57:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DF32740E5A;\n\tFri, 25 Jun 2021 07:57:16 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5AD2E40698\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:57:13 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5vCah018115; Thu, 24 Jun 2021 22:57:12 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241shnv-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:57:12 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:57:07 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:57:07 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id B13063F7041;\n Thu, 24 Jun 2021 22:57:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ZrkikovJUwIjSD5t5EInBUGW6bJwD/1z7cKO3XeFFWA=;\n b=POKUsdu1ht+HvMmjKpnqq+6QvjDKdoFol7BzztYDq4k/mrEKtCFDY9JM/jHENSJcjgJe\n yQqRzAb3t3gtRBhisZvS7McbJ0l0u2rUW4M4KoxNRZ19irk1ksjVYZUWqqkGs0kUoOBm\n SqimFztbm0iEI5+MNu/K5Fe3IXgJge354314udMpeRcRQIbcg5df41ngq5hiW5iYvayj\n T+K2+HWCXefq9Qzy7A5hQlGKScdR2ovmDVQy+dEFr/vq6EPnxtLYW8tReyeqpUxVZbKj\n ZkNQu2ddNWQqOFV5kPU4OaIkhnppveGbRv0uIV9npV/SFOOvuDYAWfjP15M1D3y0RX4j oA==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Ankur Dwivedi <adwivedi@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph\n <anoobj@marvell.com>, Archana Muniganti <marchana@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:12 +0530", "Message-ID": "<1624600591-29841-2-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "35MQEnr7Zyc8jLHjJu-vV3NpEt35VtDT", "X-Proofpoint-ORIG-GUID": "35MQEnr7Zyc8jLHjJu-vV3NpEt35VtDT", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 01/20] crypto/cnxk: add driver skeleton", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <adwivedi@marvell.com>\n\nAdd driver skeleton for crypto_cn9k & crypto_cn10k PMDs leveraging cnxk\ncommon framework.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n MAINTAINERS | 9 +++\n doc/guides/cryptodevs/cnxk.rst | 126 +++++++++++++++++++++++++++++++\n doc/guides/cryptodevs/features/cn10k.ini | 21 ++++++\n doc/guides/cryptodevs/features/cn9k.ini | 21 ++++++\n drivers/crypto/cnxk/cn10k_cryptodev.c | 42 +++++++++++\n drivers/crypto/cnxk/cn10k_cryptodev.h | 13 ++++\n drivers/crypto/cnxk/cn9k_cryptodev.c | 40 ++++++++++\n drivers/crypto/cnxk/cn9k_cryptodev.h | 13 ++++\n drivers/crypto/cnxk/meson.build | 16 ++++\n drivers/crypto/cnxk/version.map | 3 +\n drivers/crypto/meson.build | 1 +\n 11 files changed, 305 insertions(+)\n create mode 100644 doc/guides/cryptodevs/cnxk.rst\n create mode 100644 doc/guides/cryptodevs/features/cn10k.ini\n create mode 100644 doc/guides/cryptodevs/features/cn9k.ini\n create mode 100644 drivers/crypto/cnxk/cn10k_cryptodev.c\n create mode 100644 drivers/crypto/cnxk/cn10k_cryptodev.h\n create mode 100644 drivers/crypto/cnxk/cn9k_cryptodev.c\n create mode 100644 drivers/crypto/cnxk/cn9k_cryptodev.h\n create mode 100644 drivers/crypto/cnxk/meson.build\n create mode 100644 drivers/crypto/cnxk/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 5877a16..851b408 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1080,6 +1080,15 @@ F: drivers/crypto/octeontx2/\n F: doc/guides/cryptodevs/octeontx2.rst\n F: doc/guides/cryptodevs/features/octeontx2.ini\n \n+Marvell cnxk crypto\n+M: Ankur Dwivedi <adwivedi@marvell.com>\n+M: Anoob Joseph <anoobj@marvell.com>\n+M: Tejasree Kondoj <ktejasree@marvell.com>\n+F: drivers/crypto/cnxk/\n+F: doc/guides/cryptodevs/cnxk.rst\n+F: doc/guides/cryptodevs/features/cn9k.ini\n+F: doc/guides/cryptodevs/features/cn10k.ini\n+\n Null Crypto\n M: Declan Doherty <declan.doherty@intel.com>\n F: drivers/crypto/null/\ndiff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst\nnew file mode 100644\nindex 0000000..8bac539\n--- /dev/null\n+++ b/doc/guides/cryptodevs/cnxk.rst\n@@ -0,0 +1,126 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2021 Marvell.\n+\n+Marvell cnxk Crypto Poll Mode Driver\n+====================================\n+\n+The cnxk crypto poll mode driver provides support for offloading\n+cryptographic operations to cryptographic accelerator units on the\n+**Marvell OCTEON cnxk** SoC family.\n+\n+The cnxk crypto PMD code is organized into different sets of files.\n+The file names starting with cn9k and cn10k provides support for CN9XX\n+and CN10XX respectively. The common code between the SoCs is present\n+in file names starting with cnxk.\n+\n+More information about OCTEON cnxk SoCs may be obtained from `<https://www.marvell.com>`_\n+\n+Supported OCTEON cnxk SoCs\n+--------------------------\n+\n+- CN9XX\n+- CN10XX\n+\n+Installation\n+------------\n+\n+The OCTEON cnxk crypto PMD may be compiled natively on an OCTEON cnxk platform\n+or cross-compiled on an x86 platform.\n+\n+Refer to :doc:`../platform/cnxk` for instructions to build your DPDK\n+application.\n+\n+.. note::\n+\n+ The OCTEON cnxk crypto PMD uses services from the kernel mode OCTEON cnxk\n+ crypto PF driver in linux. This driver is included in the OCTEON TX SDK.\n+\n+Initialization\n+--------------\n+\n+``CN9K Initialization``\n+\n+List the CPT PF devices available on cn9k platform:\n+\n+.. code-block:: console\n+\n+ lspci -d:a0fd\n+\n+``a0fd`` is the CPT PF device id. You should see output similar to:\n+\n+.. code-block:: console\n+\n+ 0002:10:00.0 Class 1080: Device 177d:a0fd\n+\n+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:\n+\n+.. code-block:: console\n+\n+ echo 1 > /sys/bus/pci/devices/0002:10:00.0/sriov_numvfs\n+\n+Bind the CPT VF device to the vfio_pci driver:\n+\n+.. code-block:: console\n+\n+ cd <dpdk directory>\n+ ./usertools/dpdk-devbind.py -u 0002:10:00.1\n+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1\n+\n+.. note::\n+\n+ * For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve\n+ higher performance as even VF uses one crypto engine and odd one uses\n+ another crypto engine.\n+\n+ * Ensure that sufficient huge pages are available for your application::\n+\n+ dpdk-hugepages.py --setup 4G --pagesize 512M\n+\n+ Refer to :ref:`linux_gsg_hugepages` for more details.\n+\n+``CN10K Initialization``\n+\n+List the CPT PF devices available on cn10k platform:\n+\n+.. code-block:: console\n+\n+ lspci -d:a0f2\n+\n+``a0f2`` is the CPT PF device id. You should see output similar to:\n+\n+.. code-block:: console\n+\n+ 0002:20:00.0 Class 1080: Device 177d:a0f2\n+\n+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:\n+\n+.. code-block:: console\n+\n+ echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs\n+\n+Bind the CPT VF device to the vfio_pci driver:\n+\n+.. code-block:: console\n+\n+ cd <dpdk directory>\n+ ./usertools/dpdk-devbind.py -u 0002:20:00.1\n+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1\n+\n+Debugging Options\n+-----------------\n+\n+.. _table_octeon_cnxk_crypto_debug_options:\n+\n+.. table:: OCTEON cnxk crypto PMD debug options\n+\n+ +---+------------+-------------------------------------------------------+\n+ | # | Component | EAL log command |\n+ +===+============+=======================================================+\n+ | 1 | CPT | --log-level='pmd\\.crypto\\.cnxk,8' |\n+ +---+------------+-------------------------------------------------------+\n+\n+Limitations\n+-----------\n+\n+Multiple lcores may not operate on the same crypto queue pair. The lcore that\n+enqueues to a queue pair is the one that must dequeue from it.\ndiff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nnew file mode 100644\nindex 0000000..0aa097d\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -0,0 +1,21 @@\n+;\n+; Supported features of the 'cn10k' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+\n+;\n+; Supported crypto algorithms of 'cn10k' crypto driver.\n+;\n+[Cipher]\n+\n+;\n+; Supported authentication algorithms of 'cn10k' crypto driver.\n+;\n+[Auth]\n+\n+;\n+; Supported AEAD algorithms of 'cn10k' crypto driver.\n+;\n+[AEAD]\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nnew file mode 100644\nindex 0000000..64ee929\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -0,0 +1,21 @@\n+;\n+; Supported features of the 'cn9k' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+\n+;\n+; Supported crypto algorithms of 'cn9k' crypto driver.\n+;\n+[Cipher]\n+\n+;\n+; Supported authentication algorithms of 'cn9k' crypto driver.\n+;\n+[Auth]\n+\n+;\n+; Supported AEAD algorithms of 'cn9k' crypto driver.\n+;\n+[AEAD]\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c\nnew file mode 100644\nindex 0000000..4d2140c\n--- /dev/null\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_dev.h>\n+#include <rte_pci.h>\n+\n+#include \"cn10k_cryptodev.h\"\n+#include \"roc_api.h\"\n+\n+uint8_t cn10k_cryptodev_driver_id;\n+\n+static struct rte_pci_id pci_id_cpt_table[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t PCI_DEVID_CN10K_RVU_CPT_VF)\n+\t},\n+\t/* sentinel */\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+static struct rte_pci_driver cn10k_cryptodev_pmd = {\n+\t.id_table = pci_id_cpt_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n+\t.probe = NULL,\n+\t.remove = NULL,\n+};\n+\n+static struct cryptodev_driver cn10k_cryptodev_drv;\n+\n+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CN10K_PMD, cn10k_cryptodev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CN10K_PMD, pci_id_cpt_table);\n+RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_CN10K_PMD, \"vfio-pci\");\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(cn10k_cryptodev_drv, cn10k_cryptodev_pmd.driver,\n+\t\t\t cn10k_cryptodev_driver_id);\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev.h b/drivers/crypto/cnxk/cn10k_cryptodev.h\nnew file mode 100644\nindex 0000000..61f62ef\n--- /dev/null\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CN10K_CRYPTODEV_H_\n+#define _CN10K_CRYPTODEV_H_\n+\n+/* Marvell OCTEON CN10K Crypto PMD device name */\n+#define CRYPTODEV_NAME_CN10K_PMD crypto_cn10k\n+\n+extern uint8_t cn10k_cryptodev_driver_id;\n+\n+#endif /* _CN10K_CRYPTODEV_H_ */\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c\nnew file mode 100644\nindex 0000000..7654c53\n--- /dev/null\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_dev.h>\n+#include <rte_pci.h>\n+\n+#include \"cn9k_cryptodev.h\"\n+#include \"roc_api.h\"\n+\n+uint8_t cn9k_cryptodev_driver_id;\n+\n+static struct rte_pci_id pci_id_cpt_table[] = {\n+\t{\n+\t},\n+\t/* sentinel */\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+static struct rte_pci_driver cn9k_cryptodev_pmd = {\n+\t.id_table = pci_id_cpt_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n+\t.probe = NULL,\n+\t.remove = NULL,\n+};\n+\n+static struct cryptodev_driver cn9k_cryptodev_drv;\n+\n+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CN9K_PMD, cn9k_cryptodev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CN9K_PMD, pci_id_cpt_table);\n+RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_CN9K_PMD, \"vfio-pci\");\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(cn9k_cryptodev_drv, cn9k_cryptodev_pmd.driver,\n+\t\t\t cn9k_cryptodev_driver_id);\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.h b/drivers/crypto/cnxk/cn9k_cryptodev.h\nnew file mode 100644\nindex 0000000..f6e7965\n--- /dev/null\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CN9K_CRYPTODEV_H_\n+#define _CN9K_CRYPTODEV_H_\n+\n+/* Marvell OCTEON CN9K Crypto PMD device name */\n+#define CRYPTODEV_NAME_CN9K_PMD crypto_cn9k\n+\n+extern uint8_t cn9k_cryptodev_driver_id;\n+\n+#endif /* _CN9K_CRYPTODEV_H_ */\ndiff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build\nnew file mode 100644\nindex 0000000..197b94c\n--- /dev/null\n+++ b/drivers/crypto/cnxk/meson.build\n@@ -0,0 +1,16 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2021 Marvell.\n+#\n+\n+if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n+\tbuild = false\n+\treason = 'only supported on 64-bit Linux'\n+\tsubdir_done()\n+endif\n+\n+sources = files(\n+ 'cn9k_cryptodev.c',\n+ 'cn10k_cryptodev.c',\n+)\n+\n+deps += ['bus_pci', 'common_cnxk']\ndiff --git a/drivers/crypto/cnxk/version.map b/drivers/crypto/cnxk/version.map\nnew file mode 100644\nindex 0000000..ee80c51\n--- /dev/null\n+++ b/drivers/crypto/cnxk/version.map\n@@ -0,0 +1,3 @@\n+INTERNAL {\n+\tlocal: *;\n+};\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex b9fdf93..cb865aa 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -12,6 +12,7 @@ drivers = [\n 'bcmfs',\n 'caam_jr',\n 'ccp',\n+ 'cnxk',\n 'dpaa_sec',\n 'dpaa2_sec',\n 'kasumi',\n", "prefixes": [ "v2", "01/20" ] }