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GET /api/patches/94817/?format=api
{ "id": 94817, "url": "https://patches.dpdk.org/api/patches/94817/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-12-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624599410-29689-12-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624599410-29689-12-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:36:43", "name": "[v2,11/17] common/cnxk: add IE microcode defines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2d2fa40231f0e261828d3bd7a67054a8f94e9e1c", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-12-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17482, "url": "https://patches.dpdk.org/api/series/17482/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17482", "date": "2021-06-25T05:36:32", "name": "Add CPT in Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/17482/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94817/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94817/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BD73EA0C40;\n\tFri, 25 Jun 2021 07:38:24 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1D164410FF;\n\tFri, 25 Jun 2021 07:38:09 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id AC65C410F8\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:38:07 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5ZbQA015855; Thu, 24 Jun 2021 22:38:07 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241sg6h-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:38:06 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:38:04 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:38:05 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id A28873F7041;\n Thu, 24 Jun 2021 22:38:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=XKgPCFYkkV/4PpHgaDsfvt7MIoQtueL9DeIyGAwOUDA=;\n b=lZiPyjTcAbfyi7vf7190FPMMjknC5rwp+80nsXEmMQNDw/uAQnZg/j5bcosDxiGkWRcf\n yreIZ4VjNnmXQITGBtm46ZwLnRNeHS0WyBzOPyItI8/EZ0wTBWZM5mNYQV2JVbl1/knS\n 2eIL9I+TOhw6YqKxUlxJS7p/N2mHpeluuvPmhq1js2TUxwgajctvO/Ljt2Rhxx61Q5IM\n vLqK01Go3C93BNCLdSu2BlW2UAJzQm/gzr9TxrmOB0w97Wgtdmx5VK1XfADa7cEPjzBR\n a8o4i3iZZL1o48XC3Ok+jJs9Hzbt3XJb5t8r5cde8ND9TRqsGIFyl4MuWKIIv5x7nOwg Jw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Srujana Challa <schalla@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph <anoobj@marvell.com>", "Date": "Fri, 25 Jun 2021 11:06:43 +0530", "Message-ID": "<1624599410-29689-12-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624599410-29689-1-git-send-email-anoobj@marvell.com>", "References": "\n <patches.dpdk.org/project/dpdk/patch/1622649385-22652-1-git-send-email-anoobj@marvell.com/>\n <1624599410-29689-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "hJwqevkGN0cEPRi8rRWPZBT0RUImSzLu", "X-Proofpoint-ORIG-GUID": "hJwqevkGN0cEPRi8rRWPZBT0RUImSzLu", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_01:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 11/17] common/cnxk: add IE microcode defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Srujana Challa <schalla@marvell.com>\n\nMicrocode IE opcodes support IPsec operations. Add defines\nand structs defined by microcode.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Srujana Challa <schalla@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/common/cnxk/roc_api.h | 2 +\n drivers/common/cnxk/roc_ie.h | 19 ++\n drivers/common/cnxk/roc_ie_on.h | 152 +++++++++++\n drivers/common/cnxk/roc_ie_ot.h | 534 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_platform.h | 1 +\n 5 files changed, 708 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_ie.h\n create mode 100644 drivers/common/cnxk/roc_ie_on.h\n create mode 100644 drivers/common/cnxk/roc_ie_ot.h", "diff": "diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 6511614..d545bb9 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -110,6 +110,8 @@\n #include \"roc_cpt.h\"\n \n /* CPT microcode */\n+#include \"roc_ie_on.h\"\n+#include \"roc_ie_ot.h\"\n #include \"roc_se.h\"\n \n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_ie.h b/drivers/common/cnxk/roc_ie.h\nnew file mode 100644\nindex 0000000..a330ea1\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ie.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __ROC_IE_H__\n+#define __ROC_IE_H__\n+\n+/* CNXK IPSEC helper macros */\n+#define ROC_IE_AH_HDR_LEN 12\n+#define ROC_IE_AES_GCM_IV_LEN 8\n+#define ROC_IE_AES_GCM_MAC_LEN 16\n+#define ROC_IE_AES_CBC_IV_LEN 16\n+#define ROC_IE_SHA1_HMAC_LEN 12\n+#define ROC_IE_AUTH_KEY_LEN_MAX 64\n+\n+#define ROC_IE_AES_GCM_ROUNDUP_BYTE_LEN 4\n+#define ROC_IE_AES_CBC_ROUNDUP_BYTE_LEN 16\n+\n+#endif /* __ROC_IE_H__ */\ndiff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h\nnew file mode 100644\nindex 0000000..508654a\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ie_on.h\n@@ -0,0 +1,152 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __ROC_IE_ON_H__\n+#define __ROC_IE_ON_H__\n+\n+/* CN9K IPSEC LA opcodes */\n+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_OUTBOUND 0x20\n+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_INBOUND\t 0x21\n+#define ROC_IE_ONL_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23\n+#define ROC_IE_ONL_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x24\n+\n+/* CN9K IPSEC FP opcodes */\n+#define ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x25UL\n+#define ROC_IE_ONF_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x26UL\n+\n+/* Ucode completion codes */\n+#define ROC_IE_ONF_UCC_SUCCESS 0\n+\n+enum {\n+\tROC_IE_ON_SA_DIR_INBOUND = 0,\n+\tROC_IE_ON_SA_DIR_OUTBOUND = 1,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_IP_VERSION_4 = 0,\n+\tROC_IE_ON_SA_IP_VERSION_6 = 1,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_MODE_TRANSPORT = 0,\n+\tROC_IE_ON_SA_MODE_TUNNEL = 1,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_PROTOCOL_AH = 0,\n+\tROC_IE_ON_SA_PROTOCOL_ESP = 1,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_AES_KEY_LEN_128 = 1,\n+\tROC_IE_ON_SA_AES_KEY_LEN_192 = 2,\n+\tROC_IE_ON_SA_AES_KEY_LEN_256 = 3,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_ENC_NULL = 0,\n+\tROC_IE_ON_SA_ENC_DES_CBC = 1,\n+\tROC_IE_ON_SA_ENC_3DES_CBC = 2,\n+\tROC_IE_ON_SA_ENC_AES_CBC = 3,\n+\tROC_IE_ON_SA_ENC_AES_CTR = 4,\n+\tROC_IE_ON_SA_ENC_AES_GCM = 5,\n+\tROC_IE_ON_SA_ENC_AES_CCM = 6,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_AUTH_NULL = 0,\n+\tROC_IE_ON_SA_AUTH_MD5 = 1,\n+\tROC_IE_ON_SA_AUTH_SHA1 = 2,\n+\tROC_IE_ON_SA_AUTH_SHA2_224 = 3,\n+\tROC_IE_ON_SA_AUTH_SHA2_256 = 4,\n+\tROC_IE_ON_SA_AUTH_SHA2_384 = 5,\n+\tROC_IE_ON_SA_AUTH_SHA2_512 = 6,\n+\tROC_IE_ON_SA_AUTH_AES_GMAC = 7,\n+\tROC_IE_ON_SA_AUTH_AES_XCBC_128 = 8,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_FRAG_POST = 0,\n+\tROC_IE_ON_SA_FRAG_PRE = 1,\n+};\n+\n+enum {\n+\tROC_IE_ON_SA_ENCAP_NONE = 0,\n+\tROC_IE_ON_SA_ENCAP_UDP = 1,\n+};\n+\n+struct roc_ie_onf_sa_ctl {\n+\tuint32_t spi;\n+\tuint64_t exp_proto_inter_frag : 8;\n+\tuint64_t rsvd_41_40 : 2;\n+\t/* Disable SPI, SEQ data in RPTR for Inbound inline */\n+\tuint64_t spi_seq_dis : 1;\n+\tuint64_t esn_en : 1;\n+\tuint64_t rsvd_44_45 : 2;\n+\tuint64_t encap_type : 2;\n+\tuint64_t enc_type : 3;\n+\tuint64_t rsvd_48 : 1;\n+\tuint64_t auth_type : 4;\n+\tuint64_t valid : 1;\n+\tuint64_t direction : 1;\n+\tuint64_t outer_ip_ver : 1;\n+\tuint64_t inner_ip_ver : 1;\n+\tuint64_t ipsec_mode : 1;\n+\tuint64_t ipsec_proto : 1;\n+\tuint64_t aes_key_len : 2;\n+};\n+\n+struct roc_onf_ipsec_outb_sa {\n+\t/* w0 */\n+\tstruct roc_ie_onf_sa_ctl ctl;\n+\n+\t/* w1 */\n+\tuint8_t nonce[4];\n+\tuint16_t udp_src;\n+\tuint16_t udp_dst;\n+\n+\t/* w2 */\n+\tuint32_t ip_src;\n+\tuint32_t ip_dst;\n+\n+\t/* w3-w6 */\n+\tuint8_t cipher_key[32];\n+\n+\t/* w7-w12 */\n+\tuint8_t hmac_key[48];\n+};\n+\n+struct roc_onf_ipsec_inb_sa {\n+\t/* w0 */\n+\tstruct roc_ie_onf_sa_ctl ctl;\n+\n+\t/* w1 */\n+\tuint8_t nonce[4]; /* Only for AES-GCM */\n+\tuint32_t unused;\n+\n+\t/* w2 */\n+\tuint32_t esn_hi;\n+\tuint32_t esn_low;\n+\n+\t/* w3-w6 */\n+\tuint8_t cipher_key[32];\n+\n+\t/* w7-w12 */\n+\tuint8_t hmac_key[48];\n+};\n+\n+#define ROC_ONF_IPSEC_INB_MAX_L2_SZ\t 32UL\n+#define ROC_ONF_IPSEC_OUTB_MAX_L2_SZ\t 30UL\n+#define ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ (ROC_ONF_IPSEC_OUTB_MAX_L2_SZ + 2)\n+\n+#define ROC_ONF_IPSEC_INB_RES_OFF 80\n+#define ROC_ONF_IPSEC_INB_SPI_SEQ_SZ 16\n+\n+struct roc_onf_ipsec_outb_hdr {\n+\tuint32_t ip_id;\n+\tuint32_t seq;\n+\tuint8_t iv[16];\n+};\n+\n+#endif /* __ROC_IE_ON_H__ */\ndiff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h\nnew file mode 100644\nindex 0000000..aeb4be2\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_ie_ot.h\n@@ -0,0 +1,534 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __ROC_IE_OT_H__\n+#define __ROC_IE_OT_H__\n+\n+/* PKIND to be used for CPT Meta parsing */\n+#define ROC_OT_CPT_META_PKIND 58\n+\n+/* CN10K IPSEC opcodes */\n+#define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL\n+#define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL\n+\n+enum roc_ie_ot_ucc_ipsec {\n+\tROC_IE_OT_UCC_SUCCESS = 0x00,\n+\tROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM = 0x02,\n+\tROC_IE_OT_UCC_ERR_SA_INVAL = 0x03,\n+\tROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM = 0x04,\n+\tROC_IE_OT_UCC_ERR_SA_EXPIRED = 0x05,\n+\tROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM = 0x06,\n+\tROC_IE_OT_UCC_ERR_SA_OVERFLOW = 0x07,\n+\tROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM = 0x08,\n+\tROC_IE_OT_UCC_ERR_SA_ESP_BAD_ALGO = 0x09,\n+\tROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM = 0x0a,\n+\tROC_IE_OT_UCC_ERR_SA_ESP_BAD_KEYS = 0x0b,\n+\tROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST = 0x0c,\n+\tROC_IE_OT_UCC_ERR_SA_AH_BAD_ALGO = 0x0d,\n+\tROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN = 0x0e,\n+\tROC_IE_OT_UCC_ERR_SA_AH_BAD_KEYS = 0x0f,\n+\tROC_IE_OT_UCC_ERR_SA_BAD_IP = 0x11,\n+\tROC_IE_OT_UCC_ERR_SA_BAD_CTX = 0x13,\n+\tROC_IE_OT_UCC_ERR_AOP_IPSEC = 0x17,\n+\tROC_IE_OT_UCC_ERR_PKT_IP = 0x23,\n+\tROC_IE_OT_UCC_ERR_PKT_IP6_BAD_EXT = 0x25,\n+\tROC_IE_OT_UCC_ERR_PKT_IP6_HBH = 0x27,\n+\tROC_IE_OT_UCC_ERR_PKT_IP6_BIGEXT = 0x29,\n+\tROC_IE_OT_UCC_ERR_PKT_IP_FRAG = 0x2b,\n+\tROC_IE_OT_UCC_ERR_PKT_IP_ULP = 0x2d,\n+\tROC_IE_OT_UCC_ERR_PKT_SA_MISMATCH = 0x2f,\n+\tROC_IE_OT_UCC_ERR_PKT_SPI_MISMATCH = 0x31,\n+\tROC_IE_OT_UCC_ERR_PKT_ESP_BADPAD = 0x33,\n+\tROC_IE_OT_UCC_ERR_PKT_BADICV = 0x35,\n+\tROC_IE_OT_UCC_ERR_PKT_REPLAY_SEQ = 0x37,\n+\tROC_IE_OT_UCC_ERR_PKT_REPLAY_WINDOW = 0x39,\n+\tROC_IE_OT_UCC_ERR_PKT_BADNH = 0x3b,\n+\tROC_IE_OT_UCC_ERR_PKT_SA_PORT_MISMATCH = 0x3d,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_AR_WIN_DISABLED = 0,\n+\tROC_IE_OT_SA_AR_WIN_64 = 1,\n+\tROC_IE_OT_SA_AR_WIN_128 = 2,\n+\tROC_IE_OT_SA_AR_WIN_256 = 3,\n+\tROC_IE_OT_SA_AR_WIN_512 = 4,\n+\tROC_IE_OT_SA_AR_WIN_1024 = 5,\n+\tROC_IE_OT_SA_AR_WIN_2048 = 6,\n+\tROC_IE_OT_SA_AR_WIN_4096 = 7,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_PKT_FMT_FULL = 0,\n+\tROC_IE_OT_SA_PKT_FMT_META = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_PKT_OUTPUT_DECRYPTED = 0,\n+\tROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG = 1,\n+\tROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG = 2,\n+\tROC_IE_OT_SA_PKT_OUTPUT_UCODE_BASED_DEFRAG = 3,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_DEFRAG_ALL = 0,\n+\tROC_IE_OT_SA_DEFRAG_IN_ORDER = 1,\n+\tROC_IE_OT_SA_DEFRAG_IN_REV_ORDER = 2,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_IV_SRC_DEFAULT = 0,\n+\tROC_IE_OT_SA_IV_SRC_ENC_CTR = 1,\n+\tROC_IE_OT_SA_IV_SRC_FROM_SA = 2,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_COPY_FROM_SA = 0,\n+\tROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_INNER_PKT_IP_CSUM_ENABLE = 0,\n+\tROC_IE_OT_SA_INNER_PKT_IP_CSUM_DISABLE = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_INNER_PKT_L4_CSUM_ENABLE = 0,\n+\tROC_IE_OT_SA_INNER_PKT_L4_CSUM_DISABLE = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_DIR_INBOUND = 0,\n+\tROC_IE_OT_SA_DIR_OUTBOUND = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_IP_VERSION_4 = 0,\n+\tROC_IE_OT_SA_IP_VERSION_6 = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_MODE_TRANSPORT = 0,\n+\tROC_IE_OT_SA_MODE_TUNNEL = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_PROTOCOL_AH = 0,\n+\tROC_IE_OT_SA_PROTOCOL_ESP = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_AES_KEY_LEN_128 = 1,\n+\tROC_IE_OT_SA_AES_KEY_LEN_192 = 2,\n+\tROC_IE_OT_SA_AES_KEY_LEN_256 = 3,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_ENC_NULL = 0,\n+\tROC_IE_OT_SA_ENC_3DES_CBC = 2,\n+\tROC_IE_OT_SA_ENC_AES_CBC = 3,\n+\tROC_IE_OT_SA_ENC_AES_CTR = 4,\n+\tROC_IE_OT_SA_ENC_AES_GCM = 5,\n+\tROC_IE_OT_SA_ENC_AES_CCM = 6,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_AUTH_NULL = 0,\n+\tROC_IE_OT_SA_AUTH_SHA1 = 2,\n+\tROC_IE_OT_SA_AUTH_SHA2_256 = 4,\n+\tROC_IE_OT_SA_AUTH_SHA2_384 = 5,\n+\tROC_IE_OT_SA_AUTH_SHA2_512 = 6,\n+\tROC_IE_OT_SA_AUTH_AES_GMAC = 7,\n+\tROC_IE_OT_SA_AUTH_AES_XCBC_128 = 8,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_ENCAP_NONE = 0,\n+\tROC_IE_OT_SA_ENCAP_UDP = 1,\n+\tROC_IE_OT_SA_ENCAP_TCP = 2,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_LIFE_UNIT_OCTETS = 0,\n+\tROC_IE_OT_SA_LIFE_UNIT_PKTS = 1,\n+};\n+\n+enum {\n+\tROC_IE_OT_SA_IP_HDR_VERIFY_DISABLED = 0,\n+\tROC_IE_OT_SA_IP_HDR_VERIFY_DST_ADDR = 1,\n+\tROC_IE_OT_SA_IP_HDR_VERIFY_SRC_DST_ADDR = 2,\n+};\n+\n+enum {\n+\tROC_IE_OT_REAS_STS_SUCCESS = 0,\n+\tROC_IE_OT_REAS_STS_TIMEOUT = 1,\n+\tROC_IE_OT_REAS_STS_EVICT = 2,\n+\tROC_IE_OT_REAS_STS_BAD_ORDER = 3,\n+\tROC_IE_OT_REAS_STS_TOO_MANY = 4,\n+\tROC_IE_OT_REAS_STS_HSH_EVICT = 5,\n+\tROC_IE_OT_REAS_STS_OVERLAP = 6,\n+\tROC_IE_OT_REAS_STS_ZOMBIE = 7,\n+\tROC_IE_OT_REAS_STS_L3P_ERR = 8,\n+\tROC_IE_OT_REAS_STS_MAX = 9\n+};\n+/* Context units in bytes */\n+#define ROC_CTX_UNIT_8B\t\t 8\n+#define ROC_CTX_UNIT_128B\t 128\n+#define ROC_CTX_MAX_CKEY_LEN\t 32\n+#define ROC_CTX_MAX_OPAD_IPAD_LEN 128\n+\n+/* Anti reply window size supported */\n+#define ROC_AR_WIN_SIZE_MIN\t 64\n+#define ROC_AR_WIN_SIZE_MAX\t 4096\n+#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5\n+\n+/* u64 array size to fit anti replay window bits */\n+#define ROC_AR_WINBITS_SZ \\\n+\t(PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \\\n+\t BITS_PER_LONG_LONG)\n+\n+/* Common bit fields between inbound and outbound SA */\n+union roc_ot_ipsec_sa_word2 {\n+\tstruct {\n+\t\tuint64_t valid : 1;\n+\t\tuint64_t dir : 1;\n+\t\tuint64_t outer_ip_ver : 1;\n+\t\tuint64_t rsvd0 : 1;\n+\t\tuint64_t mode : 1;\n+\t\tuint64_t protocol : 1;\n+\t\tuint64_t aes_key_len : 2;\n+\n+\t\tuint64_t enc_type : 3;\n+\t\tuint64_t life_unit : 1;\n+\t\tuint64_t auth_type : 4;\n+\n+\t\tuint64_t encap_type : 2;\n+\t\tuint64_t rsvd1 : 6;\n+\n+\t\tuint64_t rsvd2 : 7;\n+\t\tuint64_t async_mode : 1;\n+\n+\t\tuint64_t spi : 32;\n+\t} s;\n+\tuint64_t u64;\n+};\n+\n+PLT_STATIC_ASSERT(sizeof(union roc_ot_ipsec_sa_word2) == 1 * sizeof(uint64_t));\n+\n+union roc_ot_ipsec_outer_ip_hdr {\n+\tstruct {\n+\t\tuint32_t dst_addr;\n+\t\tuint32_t src_addr;\n+\t} ipv4;\n+\tstruct {\n+\t\tuint8_t src_addr[16];\n+\t\tuint8_t dst_addr[16];\n+\t} ipv6;\n+};\n+\n+struct roc_ot_ipsec_inb_ctx_update_reg {\n+\tuint64_t ar_base;\n+\tuint64_t ar_valid_mask;\n+\tuint64_t hard_life;\n+\tuint64_t soft_life;\n+\tuint64_t mib_octs;\n+\tuint64_t mib_pkts;\n+\tuint64_t ar_winbits[ROC_AR_WINBITS_SZ];\n+};\n+\n+union roc_ot_ipsec_outb_iv {\n+\tuint64_t u64[2];\n+\tuint8_t iv_dbg[16];\n+\tstruct {\n+\t\tuint8_t iv_dbg1[4];\n+\t\tuint8_t salt[4];\n+\n+\t\tuint32_t rsvd;\n+\t\tuint8_t iv_dbg2[4];\n+\t} s;\n+};\n+\n+struct roc_ot_ipsec_outb_ctx_update_reg {\n+\tuint64_t rsvd;\n+\tuint64_t esn_val;\n+\tuint64_t hard_life;\n+\tuint64_t soft_life;\n+\tuint64_t mib_octs;\n+\tuint64_t mib_pkts;\n+};\n+\n+union roc_ot_ipsec_outb_param1 {\n+\tuint16_t u16;\n+\tstruct {\n+\t\tuint16_t l4_csum_disable : 1;\n+\t\tuint16_t ip_csum_disable : 1;\n+\t\tuint16_t ttl_or_hop_limit : 1;\n+\t\tuint16_t dummy_pkt : 1;\n+\t\tuint16_t rfc_or_override_mode : 1;\n+\t\tuint16_t reserved_5_15 : 11;\n+\t} s;\n+};\n+\n+union roc_ot_ipsec_inb_param1 {\n+\tuint16_t u16;\n+\tstruct {\n+\t\tuint16_t l4_csum_disable : 1;\n+\t\tuint16_t ip_csum_disable : 1;\n+\t\tuint16_t esp_trailer_disable : 1;\n+\t\tuint16_t reserved_3_15 : 13;\n+\t} s;\n+};\n+\n+struct roc_ot_ipsec_inb_sa {\n+\t/* Word0 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t ar_win : 3;\n+\t\t\tuint64_t hard_life_dec : 1;\n+\t\t\tuint64_t soft_life_dec : 1;\n+\t\t\tuint64_t count_glb_octets : 1;\n+\t\t\tuint64_t count_glb_pkts : 1;\n+\t\t\tuint64_t count_mib_bytes : 1;\n+\n+\t\t\tuint64_t count_mib_pkts : 1;\n+\t\t\tuint64_t hw_ctx_off : 7;\n+\n+\t\t\tuint64_t ctx_id : 16;\n+\n+\t\t\tuint64_t orig_pkt_fabs : 1;\n+\t\t\tuint64_t orig_pkt_free : 1;\n+\t\t\tuint64_t pkind : 6;\n+\n+\t\t\tuint64_t rsvd0 : 1;\n+\t\t\tuint64_t et_ovrwr : 1;\n+\t\t\tuint64_t pkt_output : 2;\n+\t\t\tuint64_t pkt_format : 1;\n+\t\t\tuint64_t defrag_opt : 2;\n+\t\t\tuint64_t x2p_dst : 1;\n+\n+\t\t\tuint64_t ctx_push_size : 7;\n+\t\t\tuint64_t rsvd1 : 1;\n+\n+\t\t\tuint64_t ctx_hdr_size : 2;\n+\t\t\tuint64_t aop_valid : 1;\n+\t\t\tuint64_t rsvd2 : 1;\n+\t\t\tuint64_t ctx_size : 4;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w0;\n+\n+\t/* Word1 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t orig_pkt_aura : 20;\n+\t\t\tuint64_t rsvd3 : 4;\n+\t\t\tuint64_t orig_pkt_foff : 8;\n+\t\t\tuint64_t cookie : 32;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w1;\n+\n+\t/* Word 2 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t valid : 1;\n+\t\t\tuint64_t dir : 1;\n+\t\t\tuint64_t outer_ip_ver : 1;\n+\t\t\tuint64_t rsvd4 : 1;\n+\t\t\tuint64_t ipsec_mode : 1;\n+\t\t\tuint64_t ipsec_protocol : 1;\n+\t\t\tuint64_t aes_key_len : 2;\n+\n+\t\t\tuint64_t enc_type : 3;\n+\t\t\tuint64_t life_unit : 1;\n+\t\t\tuint64_t auth_type : 4;\n+\n+\t\t\tuint64_t encap_type : 2;\n+\t\t\tuint64_t et_ovrwr_ddr_en : 1;\n+\t\t\tuint64_t esn_en : 1;\n+\t\t\tuint64_t tport_l4_incr_csum : 1;\n+\t\t\tuint64_t ip_hdr_verify : 2;\n+\t\t\tuint64_t rsvd5 : 1;\n+\n+\t\t\tuint64_t rsvd6 : 7;\n+\t\t\tuint64_t async_mode : 1;\n+\n+\t\t\tuint64_t spi : 32;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w2;\n+\n+\t/* Word3 */\n+\tuint64_t rsvd7;\n+\n+\t/* Word4 - Word7 */\n+\tuint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN];\n+\n+\t/* Word8 - Word9 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t rsvd8;\n+\t\t\tuint8_t salt[4];\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w8;\n+\tuint64_t rsvd9;\n+\n+\t/* Word10 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t rsvd10 : 32;\n+\t\t\tuint64_t udp_src_port : 16;\n+\t\t\tuint64_t udp_dst_port : 16;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w10;\n+\n+\t/* Word11 - Word14 */\n+\tunion roc_ot_ipsec_outer_ip_hdr outer_hdr;\n+\n+\t/* Word15 - Word30 */\n+\tuint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN];\n+\n+\t/* Word31 - Word100 */\n+\tstruct roc_ot_ipsec_inb_ctx_update_reg ctx;\n+};\n+\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w1) ==\n+\t\t 1 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w2) ==\n+\t\t 2 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, cipher_key) ==\n+\t\t 4 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w8) ==\n+\t\t 8 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w10) ==\n+\t\t 10 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, outer_hdr) ==\n+\t\t 11 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, hmac_opad_ipad) ==\n+\t\t 15 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, ctx) ==\n+\t\t 31 * sizeof(uint64_t));\n+\n+struct roc_ot_ipsec_outb_sa {\n+\t/* Word0 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t esn_en : 1;\n+\t\t\tuint64_t ip_id : 1;\n+\t\t\tuint64_t rsvd0 : 1;\n+\t\t\tuint64_t hard_life_dec : 1;\n+\t\t\tuint64_t soft_life_dec : 1;\n+\t\t\tuint64_t count_glb_octets : 1;\n+\t\t\tuint64_t count_glb_pkts : 1;\n+\t\t\tuint64_t count_mib_bytes : 1;\n+\n+\t\t\tuint64_t count_mib_pkts : 1;\n+\t\t\tuint64_t hw_ctx_off : 7;\n+\n+\t\t\tuint64_t rsvd1 : 32;\n+\n+\t\t\tuint64_t ctx_push_size : 7;\n+\t\t\tuint64_t rsvd2 : 1;\n+\n+\t\t\tuint64_t ctx_hdr_size : 2;\n+\t\t\tuint64_t aop_valid : 1;\n+\t\t\tuint64_t rsvd3 : 1;\n+\t\t\tuint64_t ctx_size : 4;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w0;\n+\n+\t/* Word1 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t rsvd4 : 32;\n+\t\t\tuint64_t cookie : 32;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w1;\n+\n+\t/* Word 2 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t valid : 1;\n+\t\t\tuint64_t dir : 1;\n+\t\t\tuint64_t outer_ip_ver : 1;\n+\t\t\tuint64_t rsvd5 : 1;\n+\t\t\tuint64_t ipsec_mode : 1;\n+\t\t\tuint64_t ipsec_protocol : 1;\n+\t\t\tuint64_t aes_key_len : 2;\n+\n+\t\t\tuint64_t enc_type : 3;\n+\t\t\tuint64_t life_unit : 1;\n+\t\t\tuint64_t auth_type : 4;\n+\n+\t\t\tuint64_t encap_type : 2;\n+\t\t\tuint64_t ipv4_df_src_or_ipv6_flw_lbl_src : 1;\n+\t\t\tuint64_t dscp_src : 1;\n+\t\t\tuint64_t iv_src : 2;\n+\t\t\tuint64_t ipid_gen : 1;\n+\t\t\tuint64_t rsvd6 : 1;\n+\n+\t\t\tuint64_t rsvd7 : 7;\n+\t\t\tuint64_t async_mode : 1;\n+\n+\t\t\tuint64_t spi : 32;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w2;\n+\n+\t/* Word3 */\n+\tuint64_t rsvd8;\n+\n+\t/* Word4 - Word7 */\n+\tuint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN];\n+\n+\t/* Word8 - Word9 */\n+\tunion roc_ot_ipsec_outb_iv iv;\n+\n+\t/* Word10 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t rsvd9 : 4;\n+\t\t\tuint64_t ipv4_df_or_ipv6_flw_lbl : 20;\n+\n+\t\t\tuint64_t dscp : 6;\n+\t\t\tuint64_t rsvd10 : 2;\n+\n+\t\t\tuint64_t udp_dst_port : 16;\n+\n+\t\t\tuint64_t udp_src_port : 16;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w10;\n+\n+\t/* Word11 - Word14 */\n+\tunion roc_ot_ipsec_outer_ip_hdr outer_hdr;\n+\n+\t/* Word15 - Word30 */\n+\tuint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN];\n+\n+\t/* Word31 - Word36 */\n+\tstruct roc_ot_ipsec_outb_ctx_update_reg ctx;\n+};\n+\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w1) ==\n+\t\t 1 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w2) ==\n+\t\t 2 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, cipher_key) ==\n+\t\t 4 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, iv) ==\n+\t\t 8 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w10) ==\n+\t\t 10 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, outer_hdr) ==\n+\t\t 11 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==\n+\t\t 15 * sizeof(uint64_t));\n+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==\n+\t\t 31 * sizeof(uint64_t));\n+\n+#endif /* __ROC_IE_OT_H__ */\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex daee100..685ec29 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -49,6 +49,7 @@\n #define PLT_MODEL_MZ_NAME\t \"roc_model_mz\"\n #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE\n #define BITMASK_ULL\t\t GENMASK_ULL\n+#define PLT_ALIGN_CEIL\t\t RTE_ALIGN_CEIL\n \n /** Divide ceil */\n #define PLT_DIV_CEIL(x, y)\t\t\t\\\n", "prefixes": [ "v2", "11/17" ] }