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GET /api/patches/94734/?format=api
{ "id": 94734, "url": "https://patches.dpdk.org/api/patches/94734/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-39-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-39-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-39-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:38", "name": "[v4,38/62] net/cnxk: add flow ctrl set/get ops", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "77e507b41f970164302824404c98021a5a0bc4ce", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-39-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94734/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94734/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5777AA0C41;\n\tWed, 23 Jun 2021 06:51:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3325D41195;\n\tWed, 23 Jun 2021 06:49:26 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5B2C4411A9\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:49:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k7o1025542 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:49:24 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1grt-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:49:24 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:49:22 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:49:22 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id AF1B15B6936;\n Tue, 22 Jun 2021 21:49:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=WVcSmek3S1mKhEJF3lHIDfS8u5x6Y+whBPlBu5TmdRo=;\n b=HoJBxKn6TryMftRxOOu+CByJcI83GtLsz6dWrcKyK1lUGCCuAqFmyZPCXY7bn/6pTpmY\n gma5PXy/Qqgqvqzh5eWs04moVl3vRwypiDnW++U9QUvdfenaKpNtHdBNWivs9bHoZj+F\n BWTPdcmgv91oAFHcLWBgtEBPr1hrO5LiIdrywHPiuK1y9DvbENP8v5CpbdYmO7rXCrQc\n WkEBsnbSW1nHJg/l0ODSH9EPBSGA2uYOYpoC4ZMlgd5qte+e/a/Riahff4qLefU+EBpG\n zIQa25xNVfLJRQb3ChDzOl+U9VUK2lLXMFdX5zI9PpEpf6PT6cz/X9oApmZ2DYjTJl9e +A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:38 +0530", "Message-ID": "<20210623044702.4240-39-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "J9oU0qCjOo7RTUfzpWE-wdR7SvNAiMdg", "X-Proofpoint-GUID": "J9oU0qCjOo7RTUfzpWE-wdR7SvNAiMdg", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 38/62] net/cnxk: add flow ctrl set/get ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nPatch implements set and get operations for flow control.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 1 +\n doc/guides/nics/features/cnxk.ini | 1 +\n doc/guides/nics/features/cnxk_vec.ini | 1 +\n drivers/net/cnxk/cnxk_ethdev.c | 74 +++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 13 +++++\n drivers/net/cnxk/cnxk_ethdev_ops.c | 101 ++++++++++++++++++++++++++++++++++\n 6 files changed, 191 insertions(+)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex af7141f..88ca313 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -26,6 +26,7 @@ Features of the CNXK Ethdev PMD are:\n - MAC filtering\n - Inner and Outer Checksum offload\n - Link state information\n+- Link flow control\n - MTU update\n - Scatter-Gather IO support\n - Vector Poll mode driver\ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex 298f167..afd0f01 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -23,6 +23,7 @@ Allmulticast mode = Y\n Unicast MAC filter = Y\n RSS hash = Y\n Inner RSS = Y\n+Flow control = Y\n Jumbo frame = Y\n Scattered Rx = Y\n L3 checksum offload = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex a673cc1..4bd11ce 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -22,6 +22,7 @@ Allmulticast mode = Y\n Unicast MAC filter = Y\n RSS hash = Y\n Inner RSS = Y\n+Flow control = Y\n Jumbo frame = Y\n L3 checksum offload = Y\n L4 checksum offload = Y\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 0311df3..abca49b 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -81,6 +81,55 @@ nix_recalc_mtu(struct rte_eth_dev *eth_dev)\n \treturn rc;\n }\n \n+static int\n+nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n+\tstruct rte_eth_fc_conf fc_conf = {0};\n+\tint rc;\n+\n+\t/* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW\n+\t * by AF driver, update those info in PMD structure.\n+\t */\n+\trc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tfc->mode = fc_conf.mode;\n+\tfc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||\n+\t\t\t(fc_conf.mode == RTE_FC_RX_PAUSE);\n+\tfc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||\n+\t\t\t(fc_conf.mode == RTE_FC_TX_PAUSE);\n+\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n+nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n+\tstruct rte_eth_fc_conf fc_cfg = {0};\n+\n+\tif (roc_nix_is_vf_or_sdp(&dev->nix))\n+\t\treturn 0;\n+\n+\tfc_cfg.mode = fc->mode;\n+\n+\t/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */\n+\tif (roc_model_is_cn96_ax() &&\n+\t (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {\n+\t\tfc_cfg.mode =\n+\t\t\t\t(fc_cfg.mode == RTE_FC_FULL ||\n+\t\t\t\tfc_cfg.mode == RTE_FC_TX_PAUSE) ?\n+\t\t\t\tRTE_FC_TX_PAUSE : RTE_FC_NONE;\n+\t}\n+\n+\treturn cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);\n+}\n+\n uint64_t\n cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)\n {\n@@ -686,6 +735,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n \tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n \tstruct rte_eth_txmode *txmode = &conf->txmode;\n \tchar ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];\n+\tstruct roc_nix_fc_cfg fc_cfg = {0};\n \tstruct roc_nix *nix = &dev->nix;\n \tstruct rte_ether_addr *ea;\n \tuint8_t nb_rxq, nb_txq;\n@@ -867,6 +917,21 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto cq_fini;\n \t}\n \n+\t/* Init flow control configuration */\n+\tfc_cfg.cq_cfg_valid = false;\n+\tfc_cfg.rxchan_cfg.enable = true;\n+\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to initialize flow control rc=%d\", rc);\n+\t\tgoto cq_fini;\n+\t}\n+\n+\t/* Update flow control configuration to PMD */\n+\trc = nix_init_flow_ctrl_config(eth_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to initialize flow control rc=%d\", rc);\n+\t\tgoto cq_fini;\n+\t}\n \t/*\n \t * Restore queue config when reconfigure followed by\n \t * reconfigure and no queue configure invoked from application case.\n@@ -1066,6 +1131,13 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)\n \t\t\treturn rc;\n \t}\n \n+\t/* Update Flow control configuration */\n+\trc = nix_update_flow_ctrl_config(eth_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable flow control. error code(%d)\", rc);\n+\t\treturn rc;\n+\t}\n+\n \t/* Enable Rx in NPC */\n \trc = roc_nix_npc_rx_ena_dis(&dev->nix, true);\n \tif (rc) {\n@@ -1115,6 +1187,8 @@ struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.allmulticast_disable = cnxk_nix_allmulticast_disable,\n \t.rx_burst_mode_get = cnxk_nix_rx_burst_mode_get,\n \t.tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,\n+\t.flow_ctrl_get = cnxk_nix_flow_ctrl_get,\n+\t.flow_ctrl_set = cnxk_nix_flow_ctrl_set,\n };\n \n static int\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex aea0005..e788a42 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -113,6 +113,12 @@\n \t((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \\\n \t (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))\n \n+struct cnxk_fc_cfg {\n+\tenum rte_eth_fc_mode mode;\n+\tuint8_t rx_pause;\n+\tuint8_t tx_pause;\n+};\n+\n struct cnxk_eth_qconf {\n \tunion {\n \t\tstruct rte_eth_txconf tx;\n@@ -174,6 +180,9 @@ struct cnxk_eth_dev {\n \tstruct cnxk_eth_qconf *tx_qconf;\n \tstruct cnxk_eth_qconf *rx_qconf;\n \n+\t/* Flow control configuration */\n+\tstruct cnxk_fc_cfg fc_cfg;\n+\n \t/* Rx burst for cleanup(Only Primary) */\n \teth_rx_burst_t rx_pkt_burst_no_offload;\n \n@@ -238,6 +247,10 @@ int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\n int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\n+int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n+int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n int cnxk_nix_configure(struct rte_eth_dev *eth_dev);\n int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\t uint16_t nb_desc, uint16_t fp_tx_q_sz,\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex 7ae961a..97c5428 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -199,6 +199,107 @@ cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n }\n \n int\n+cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tenum rte_eth_fc_mode mode_map[] = {\n+\t\t\t\t\t RTE_FC_NONE, RTE_FC_RX_PAUSE,\n+\t\t\t\t\t RTE_FC_TX_PAUSE, RTE_FC_FULL\n+\t\t\t\t\t };\n+\tstruct roc_nix *nix = &dev->nix;\n+\tint mode;\n+\n+\tmode = roc_nix_fc_mode_get(nix);\n+\tif (mode < 0)\n+\t\treturn mode;\n+\n+\tmemset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));\n+\tfc_conf->mode = mode_map[mode];\n+\treturn 0;\n+}\n+\n+static int\n+nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)\n+{\n+\tstruct roc_nix *nix = &dev->nix;\n+\tstruct roc_nix_fc_cfg fc_cfg;\n+\tstruct roc_nix_cq *cq;\n+\n+\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\tcq = &dev->cqs[qid];\n+\tfc_cfg.cq_cfg_valid = true;\n+\tfc_cfg.cq_cfg.enable = enable;\n+\tfc_cfg.cq_cfg.rq = qid;\n+\tfc_cfg.cq_cfg.cq_drop = cq->drop_thresh;\n+\n+\treturn roc_nix_fc_config_set(nix, &fc_cfg);\n+}\n+\n+int\n+cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tenum roc_nix_fc_mode mode_map[] = {\n+\t\t\t\t\t ROC_NIX_FC_NONE, ROC_NIX_FC_RX,\n+\t\t\t\t\t ROC_NIX_FC_TX, ROC_NIX_FC_FULL\n+\t\t\t\t\t };\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n+\tstruct roc_nix *nix = &dev->nix;\n+\tuint8_t rx_pause, tx_pause;\n+\tint rc, i;\n+\n+\tif (roc_nix_is_vf_or_sdp(nix)) {\n+\t\tplt_err(\"Flow control configuration is not allowed on VFs\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||\n+\t fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {\n+\t\tplt_info(\"Only MODE configuration is supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (fc_conf->mode == fc->mode)\n+\t\treturn 0;\n+\n+\trx_pause = (fc_conf->mode == RTE_FC_FULL) ||\n+\t\t (fc_conf->mode == RTE_FC_RX_PAUSE);\n+\ttx_pause = (fc_conf->mode == RTE_FC_FULL) ||\n+\t\t (fc_conf->mode == RTE_FC_TX_PAUSE);\n+\n+\t/* Check if TX pause frame is already enabled or not */\n+\tif (fc->tx_pause ^ tx_pause) {\n+\t\tif (roc_model_is_cn96_ax() && data->dev_started) {\n+\t\t\t/* On Ax, CQ should be in disabled state\n+\t\t\t * while setting flow control configuration.\n+\t\t\t */\n+\t\t\tplt_info(\"Stop the port=%d for setting flow control\",\n+\t\t\t\t data->port_id);\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tfor (i = 0; i < data->nb_rx_queues; i++) {\n+\t\t\trc = nix_fc_cq_config_set(dev, i, tx_pause);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\trc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfc->rx_pause = rx_pause;\n+\tfc->tx_pause = tx_pause;\n+\tfc->mode = fc_conf->mode;\n+\n+\treturn rc;\n+}\n+\n+int\n cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n", "prefixes": [ "v4", "38/62" ] }