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GET /api/patches/94713/?format=api
{ "id": 94713, "url": "https://patches.dpdk.org/api/patches/94713/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-18-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-18-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-18-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:17", "name": "[v4,17/62] net/cnxk: support packet type", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e9c99bfae59d79b30b211a7dc5994c8c6a61ed1c", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-18-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94713/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94713/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C0024A0C41;\n\tWed, 23 Jun 2021 06:49:22 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 65C8A4111E;\n\tWed, 23 Jun 2021 06:48:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 24AC34115C\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:16 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4kORv026099 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:15 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gka-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:15 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:13 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:13 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 503BF5B6939;\n Tue, 22 Jun 2021 21:48:10 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=SnSoFzsWgsN5m/ER+fv0gGDSDaZa40zirHvrPfTYdy8=;\n b=ZHjm23PRRvM6kVNrXNO7oOtnC7KayXKCOUgwZHULFoHKFn3ZlYFNMHtk+jzZ8I5X53Qd\n uUhxlK7K2FrBg5l8NntnV29kjSIJiQ9q4P+JZtHXx0pyhFoyWM8xBhuoqTAJRyA21mZ7\n l34iQjg5gOLYbw7w0rET3lPwYykxDsgjIJ1NABjqDhQPiM4iiOhTUzCI65uZQOcFxMGq\n yrujw7PTyF2h29NV4yudDIO8o+Fxjmzl0baFbcjThAIWzZKP0OvY3v3CvpQEBeCX7QeH\n Dm/FhaGB3bdwPbCtOfOob4yA8dktgWWsF8srKvW7xhMaLkiwGlrlRUXOP8vFtgSTtcPi AA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:17 +0530", "Message-ID": "<20210623044702.4240-18-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "mTY7Nl7PljaFfHBYg2k1sBssrL3NuCpS", "X-Proofpoint-GUID": "mTY7Nl7PljaFfHBYg2k1sBssrL3NuCpS", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 17/62] net/cnxk: support packet type", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for packet type lookup on Rx to translate HW\nspecific types to RTE_PTYPE_* defines\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 1 +\n doc/guides/nics/features/cnxk.ini | 1 +\n doc/guides/nics/features/cnxk_vec.ini | 1 +\n doc/guides/nics/features/cnxk_vf.ini | 1 +\n drivers/net/cnxk/cn10k_ethdev.c | 21 +++\n drivers/net/cnxk/cn10k_rx.h | 11 ++\n drivers/net/cnxk/cn9k_ethdev.c | 21 +++\n drivers/net/cnxk/cn9k_rx.h | 12 ++\n drivers/net/cnxk/cnxk_ethdev.c | 2 +\n drivers/net/cnxk/cnxk_ethdev.h | 14 ++\n drivers/net/cnxk/cnxk_lookup.c | 326 ++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/meson.build | 3 +-\n 12 files changed, 413 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/cnxk/cn10k_rx.h\n create mode 100644 drivers/net/cnxk/cn9k_rx.h\n create mode 100644 drivers/net/cnxk/cnxk_lookup.c", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 7bf6cf5..8bc85c0 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -16,6 +16,7 @@ Features\n \n Features of the CNXK Ethdev PMD are:\n \n+- Packet type information\n - SR-IOV VF\n - Lock-free Tx queue\n - Multiple queues for TX and RX\ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex 462d7c4..503582c 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -14,6 +14,7 @@ Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n+Packet type parsing = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex 09e0d3a..9ad225a 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -14,6 +14,7 @@ Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n+Packet type parsing = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex 4a93a35..8c93ba7 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -13,6 +13,7 @@ Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n+Packet type parsing = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex 454c8ca..f79d03c 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -2,8 +2,25 @@\n * Copyright(C) 2021 Marvell.\n */\n #include \"cn10k_ethdev.h\"\n+#include \"cn10k_rx.h\"\n #include \"cn10k_tx.h\"\n \n+static int\n+cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n+\tif (ptype_mask) {\n+\t\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;\n+\t\tdev->ptype_disable = 0;\n+\t} else {\n+\t\tdev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;\n+\t\tdev->ptype_disable = 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static void\n nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,\n \t\t uint16_t qid)\n@@ -114,6 +131,9 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Data offset from data to start of mbuf is first_skip */\n \trxq->data_off = rq->first_skip;\n \trxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);\n+\n+\t/* Lookup mem */\n+\trxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();\n \treturn 0;\n }\n \n@@ -149,6 +169,7 @@ nix_eth_dev_ops_override(void)\n \tcnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;\n \tcnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;\n \tcnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;\n+\tcnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;\n }\n \n static int\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nnew file mode 100644\nindex 0000000..d3d1661\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CN10K_RX_H__\n+#define __CN10K_RX_H__\n+\n+#include <rte_ether.h>\n+\n+#define NIX_RX_OFFLOAD_PTYPE_F\t BIT(1)\n+\n+#endif /* __CN10K_RX_H__ */\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex 5c696c8..19b3727 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -2,8 +2,25 @@\n * Copyright(C) 2021 Marvell.\n */\n #include \"cn9k_ethdev.h\"\n+#include \"cn9k_rx.h\"\n #include \"cn9k_tx.h\"\n \n+static int\n+cn9k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n+\tif (ptype_mask) {\n+\t\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;\n+\t\tdev->ptype_disable = 0;\n+\t} else {\n+\t\tdev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;\n+\t\tdev->ptype_disable = 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static void\n nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,\n \t\t uint16_t qid)\n@@ -112,6 +129,9 @@ cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Data offset from data to start of mbuf is first_skip */\n \trxq->data_off = rq->first_skip;\n \trxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);\n+\n+\t/* Lookup mem */\n+\trxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();\n \treturn 0;\n }\n \n@@ -158,6 +178,7 @@ nix_eth_dev_ops_override(void)\n \tcnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;\n \tcnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;\n \tcnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;\n+\tcnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set;\n }\n \n static int\ndiff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h\nnew file mode 100644\nindex 0000000..95a1e69\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_rx.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __CN9K_RX_H__\n+#define __CN9K_RX_H__\n+\n+#include <rte_ether.h>\n+\n+#define NIX_RX_OFFLOAD_PTYPE_F\t BIT(1)\n+\n+#endif /* __CN9K_RX_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 424512c..b1ed046 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -872,6 +872,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.link_update = cnxk_nix_link_update,\n \t.tx_queue_release = cnxk_nix_tx_queue_release,\n \t.rx_queue_release = cnxk_nix_rx_queue_release,\n+\t.dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,\n };\n \n static int\n@@ -911,6 +912,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \n \tdev->eth_dev = eth_dev;\n \tdev->configured = 0;\n+\tdev->ptype_disable = 0;\n \n \t/* For vfs, returned max_entries will be 0. but to keep default mac\n \t * address, one entry must be allocated. so setting up to 1.\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex ef8e408..b23df4a 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -91,6 +91,15 @@\n #define RSS_SCTP_INDEX 4\n #define RSS_DMAC_INDEX 5\n \n+#define PTYPE_NON_TUNNEL_WIDTH\t 16\n+#define PTYPE_TUNNEL_WIDTH\t 12\n+#define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)\n+#define PTYPE_TUNNEL_ARRAY_SZ\t BIT(PTYPE_TUNNEL_WIDTH)\n+#define PTYPE_ARRAY_SZ \\\n+\t((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))\n+/* Fastpath lookup */\n+#define CNXK_NIX_FASTPATH_LOOKUP_MEM \"cnxk_nix_fastpath_lookup_mem\"\n+\n struct cnxk_eth_qconf {\n \tunion {\n \t\tstruct rte_eth_txconf tx;\n@@ -119,6 +128,7 @@ struct cnxk_eth_dev {\n \tuint8_t max_mac_entries;\n \n \tuint16_t flags;\n+\tuint8_t ptype_disable;\n \tbool scalar_ena;\n \n \t/* Pointer back to rte */\n@@ -216,6 +226,10 @@ void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,\n \t\t\t\t struct roc_nix_link_info *link);\n int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);\n \n+/* Lookup configuration */\n+const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);\n+void *cnxk_nix_fastpath_lookup_mem_get(void);\n+\n /* Devargs */\n int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,\n \t\t\t struct cnxk_eth_dev *dev);\ndiff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c\nnew file mode 100644\nindex 0000000..0152ad9\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_lookup.c\n@@ -0,0 +1,326 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_memzone.h>\n+\n+#include \"cnxk_ethdev.h\"\n+\n+/* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */\n+#define ERRCODE_ERRLEN_WIDTH 12\n+#define ERR_ARRAY_SZ\t ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))\n+\n+#define SA_TBL_SZ\t(RTE_MAX_ETHPORTS * sizeof(uint64_t))\n+#define LOOKUP_ARRAY_SZ (PTYPE_ARRAY_SZ + ERR_ARRAY_SZ + SA_TBL_SZ)\n+const uint32_t *\n+cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev)\n+{\n+\tRTE_SET_USED(eth_dev);\n+\n+\tstatic const uint32_t ptypes[] = {\n+\t\tRTE_PTYPE_L2_ETHER_QINQ, /* LB */\n+\t\tRTE_PTYPE_L2_ETHER_VLAN, /* LB */\n+\t\tRTE_PTYPE_L2_ETHER_TIMESYNC, /* LB */\n+\t\tRTE_PTYPE_L2_ETHER_ARP,\t /* LC */\n+\t\tRTE_PTYPE_L2_ETHER_NSH,\t /* LC */\n+\t\tRTE_PTYPE_L2_ETHER_FCOE, /* LC */\n+\t\tRTE_PTYPE_L2_ETHER_MPLS, /* LC */\n+\t\tRTE_PTYPE_L3_IPV4,\t /* LC */\n+\t\tRTE_PTYPE_L3_IPV4_EXT,\t /* LC */\n+\t\tRTE_PTYPE_L3_IPV6,\t /* LC */\n+\t\tRTE_PTYPE_L3_IPV6_EXT,\t /* LC */\n+\t\tRTE_PTYPE_L4_TCP,\t /* LD */\n+\t\tRTE_PTYPE_L4_UDP,\t /* LD */\n+\t\tRTE_PTYPE_L4_SCTP,\t /* LD */\n+\t\tRTE_PTYPE_L4_ICMP,\t /* LD */\n+\t\tRTE_PTYPE_L4_IGMP,\t /* LD */\n+\t\tRTE_PTYPE_TUNNEL_GRE,\t /* LD */\n+\t\tRTE_PTYPE_TUNNEL_ESP,\t /* LD */\n+\t\tRTE_PTYPE_TUNNEL_NVGRE,\t /* LD */\n+\t\tRTE_PTYPE_TUNNEL_VXLAN,\t /* LE */\n+\t\tRTE_PTYPE_TUNNEL_GENEVE, /* LE */\n+\t\tRTE_PTYPE_TUNNEL_GTPC,\t /* LE */\n+\t\tRTE_PTYPE_TUNNEL_GTPU,\t /* LE */\n+\t\tRTE_PTYPE_TUNNEL_VXLAN_GPE, /* LE */\n+\t\tRTE_PTYPE_TUNNEL_MPLS_IN_GRE, /* LE */\n+\t\tRTE_PTYPE_TUNNEL_MPLS_IN_UDP, /* LE */\n+\t\tRTE_PTYPE_INNER_L2_ETHER, /* LF */\n+\t\tRTE_PTYPE_INNER_L3_IPV4, /* LG */\n+\t\tRTE_PTYPE_INNER_L3_IPV6, /* LG */\n+\t\tRTE_PTYPE_INNER_L4_TCP,\t /* LH */\n+\t\tRTE_PTYPE_INNER_L4_UDP,\t /* LH */\n+\t\tRTE_PTYPE_INNER_L4_SCTP, /* LH */\n+\t\tRTE_PTYPE_INNER_L4_ICMP, /* LH */\n+\t\tRTE_PTYPE_UNKNOWN,\n+\t};\n+\n+\treturn ptypes;\n+}\n+\n+/*\n+ * +------------------ +------------------ +\n+ * | | IL4 | IL3| IL2 | TU | L4 | L3 | L2 |\n+ * +-------------------+-------------------+\n+ *\n+ * +-------------------+------------------ +\n+ * | | LH | LG | LF | LE | LD | LC | LB |\n+ * +-------------------+-------------------+\n+ *\n+ * ptype [LE - LD - LC - LB] = TU - L4 - L3 - T2\n+ * ptype_tunnel[LH - LG - LF] = IL4 - IL3 - IL2 - TU\n+ *\n+ */\n+static void\n+nix_create_non_tunnel_ptype_array(uint16_t *ptype)\n+{\n+\tuint8_t lb, lc, ld, le;\n+\tuint16_t val;\n+\tuint32_t idx;\n+\n+\tfor (idx = 0; idx < PTYPE_NON_TUNNEL_ARRAY_SZ; idx++) {\n+\t\tlb = idx & 0xF;\n+\t\tlc = (idx & 0xF0) >> 4;\n+\t\tld = (idx & 0xF00) >> 8;\n+\t\tle = (idx & 0xF000) >> 12;\n+\t\tval = RTE_PTYPE_UNKNOWN;\n+\n+\t\tswitch (lb) {\n+\t\tcase NPC_LT_LB_STAG_QINQ:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_QINQ;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LB_CTAG:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_VLAN;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (lc) {\n+\t\tcase NPC_LT_LC_ARP:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_ARP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_NSH:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_NSH;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_FCOE:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_FCOE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_MPLS:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_MPLS;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP:\n+\t\t\tval |= RTE_PTYPE_L3_IPV4;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP_OPT:\n+\t\t\tval |= RTE_PTYPE_L3_IPV4_EXT;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP6:\n+\t\t\tval |= RTE_PTYPE_L3_IPV6;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP6_EXT:\n+\t\t\tval |= RTE_PTYPE_L3_IPV6_EXT;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_PTP:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_TIMESYNC;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (ld) {\n+\t\tcase NPC_LT_LD_TCP:\n+\t\t\tval |= RTE_PTYPE_L4_TCP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_UDP:\n+\t\t\tval |= RTE_PTYPE_L4_UDP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_SCTP:\n+\t\t\tval |= RTE_PTYPE_L4_SCTP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_ICMP:\n+\t\tcase NPC_LT_LD_ICMP6:\n+\t\t\tval |= RTE_PTYPE_L4_ICMP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_IGMP:\n+\t\t\tval |= RTE_PTYPE_L4_IGMP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_GRE:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_GRE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_NVGRE:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_NVGRE;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (le) {\n+\t\tcase NPC_LT_LE_VXLAN:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_VXLAN;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_ESP:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_ESP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_VXLANGPE:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_VXLAN_GPE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_GENEVE:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_GENEVE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_GTPC:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_GTPC;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_GTPU:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_GTPU;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_TU_MPLS_IN_GRE:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_MPLS_IN_GRE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LE_TU_MPLS_IN_UDP:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_MPLS_IN_UDP;\n+\t\t\tbreak;\n+\t\t}\n+\t\tptype[idx] = val;\n+\t}\n+}\n+\n+#define TU_SHIFT(x) ((x) >> PTYPE_NON_TUNNEL_WIDTH)\n+static void\n+nix_create_tunnel_ptype_array(uint16_t *ptype)\n+{\n+\tuint8_t lf, lg, lh;\n+\tuint16_t val;\n+\tuint32_t idx;\n+\n+\t/* Skip non tunnel ptype array memory */\n+\tptype = ptype + PTYPE_NON_TUNNEL_ARRAY_SZ;\n+\n+\tfor (idx = 0; idx < PTYPE_TUNNEL_ARRAY_SZ; idx++) {\n+\t\tlf = idx & 0xF;\n+\t\tlg = (idx & 0xF0) >> 4;\n+\t\tlh = (idx & 0xF00) >> 8;\n+\t\tval = RTE_PTYPE_UNKNOWN;\n+\n+\t\tswitch (lf) {\n+\t\tcase NPC_LT_LF_TU_ETHER:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L2_ETHER);\n+\t\t\tbreak;\n+\t\t}\n+\t\tswitch (lg) {\n+\t\tcase NPC_LT_LG_TU_IP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV4);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LG_TU_IP6:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV6);\n+\t\t\tbreak;\n+\t\t}\n+\t\tswitch (lh) {\n+\t\tcase NPC_LT_LH_TU_TCP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_TCP);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LH_TU_UDP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_UDP);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LH_TU_SCTP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_SCTP);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LH_TU_ICMP:\n+\t\tcase NPC_LT_LH_TU_ICMP6:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_ICMP);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tptype[idx] = val;\n+\t}\n+}\n+\n+static void\n+nix_create_rx_ol_flags_array(void *mem)\n+{\n+\tuint16_t idx, errcode, errlev;\n+\tuint32_t val, *ol_flags;\n+\n+\t/* Skip ptype array memory */\n+\tol_flags = (uint32_t *)((uint8_t *)mem + PTYPE_ARRAY_SZ);\n+\n+\tfor (idx = 0; idx < BIT(ERRCODE_ERRLEN_WIDTH); idx++) {\n+\t\terrlev = idx & 0xf;\n+\t\terrcode = (idx & 0xff0) >> 4;\n+\n+\t\tval = PKT_RX_IP_CKSUM_UNKNOWN;\n+\t\tval |= PKT_RX_L4_CKSUM_UNKNOWN;\n+\t\tval |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;\n+\n+\t\tswitch (errlev) {\n+\t\tcase NPC_ERRLEV_RE:\n+\t\t\t/* Mark all errors as BAD checksum errors\n+\t\t\t * including Outer L2 length mismatch error\n+\t\t\t */\n+\t\t\tif (errcode) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_GOOD;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase NPC_ERRLEV_LC:\n+\t\t\tif (errcode == NPC_EC_OIP4_CSUM ||\n+\t\t\t errcode == NPC_EC_IP_FRAG_OFFSET_1) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\t\tval |= PKT_RX_OUTER_IP_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase NPC_ERRLEV_LG:\n+\t\t\tif (errcode == NPC_EC_IIP4_CSUM)\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\telse\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\tbreak;\n+\t\tcase NPC_ERRLEV_NIX:\n+\t\t\tif (errcode == NIX_RX_PERRCODE_OL4_CHK ||\n+\t\t\t errcode == NIX_RX_PERRCODE_OL4_LEN ||\n+\t\t\t errcode == NIX_RX_PERRCODE_OL4_PORT) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t\tval |= PKT_RX_OUTER_L4_CKSUM_BAD;\n+\t\t\t} else if (errcode == NIX_RX_PERRCODE_IL4_CHK ||\n+\t\t\t\t errcode == NIX_RX_PERRCODE_IL4_LEN ||\n+\t\t\t\t errcode == NIX_RX_PERRCODE_IL4_PORT) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t} else if (errcode == NIX_RX_PERRCODE_IL3_LEN ||\n+\t\t\t\t errcode == NIX_RX_PERRCODE_OL3_LEN) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_GOOD;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\t\tol_flags[idx] = val;\n+\t}\n+}\n+\n+void *\n+cnxk_nix_fastpath_lookup_mem_get(void)\n+{\n+\tconst char name[] = CNXK_NIX_FASTPATH_LOOKUP_MEM;\n+\tconst struct rte_memzone *mz;\n+\tvoid *mem;\n+\n+\tmz = rte_memzone_lookup(name);\n+\tif (mz != NULL)\n+\t\treturn mz->addr;\n+\n+\t/* Request for the first time */\n+\tmz = rte_memzone_reserve_aligned(name, LOOKUP_ARRAY_SZ, SOCKET_ID_ANY,\n+\t\t\t\t\t 0, ROC_ALIGN);\n+\tif (mz != NULL) {\n+\t\tmem = mz->addr;\n+\t\t/* Form the ptype array lookup memory */\n+\t\tnix_create_non_tunnel_ptype_array(mem);\n+\t\tnix_create_tunnel_ptype_array(mem);\n+\t\t/* Form the rx ol_flags based on errcode */\n+\t\tnix_create_rx_ol_flags_array(mem);\n+\t\treturn mem;\n+\t}\n+\treturn NULL;\n+}\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 1ac3d08..5bc0bb5 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -11,7 +11,8 @@ endif\n sources = files('cnxk_ethdev.c',\n \t\t'cnxk_ethdev_ops.c',\n \t\t'cnxk_ethdev_devargs.c',\n-\t\t'cnxk_link.c')\n+\t\t'cnxk_link.c',\n+\t\t'cnxk_lookup.c')\n \n # CN9K\n sources += files('cn9k_ethdev.c')\n", "prefixes": [ "v4", "17/62" ] }