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GET /api/patches/94712/?format=api
{ "id": 94712, "url": "https://patches.dpdk.org/api/patches/94712/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-17-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-17-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-17-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:16", "name": "[v4,16/62] net/cnxk: add Tx queue setup and release", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a9f6e8b6c83f8d19df9721b52c9929504ef0869e", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-17-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94712/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94712/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A5D6A0C41;\n\tWed, 23 Jun 2021 06:49:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8BADB41150;\n\tWed, 23 Jun 2021 06:48:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 98799410FF\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:12 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k6fP025518 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:12 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gk7-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:11 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:09 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:09 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id E22B95B6937;\n Tue, 22 Jun 2021 21:48:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=uJ5MvuTfRlmeu1vwY0wZy1MP8gK8VAg7c1cr6002Yv0=;\n b=F4+BmfGhRPDIgWIIwVbXa8ObtG/woh4YQAVZFDE8oOEdLHpAiiG7NaenlrOyQvfnnc3G\n 2mTOpbyylyMm5LMEKyyYw+iP2UB8/wKwKGECLIphzKC90w3q3lrrWeR0xaRDhcFc7bbu\n X93Ky+x2ZlU33O69HoKMSv8QImQUNQBWL36OX2UvoURheRPYrgarjtFvFIJ/AaVU1TIu\n ewgQjf6IDq4x6lhoanVPmIH3UgpdNszvpDjC49v/RkmTVanpKf8thkhKzFrF/0c7FheZ\n 58DtolKFSSeNX7hvr/pE4YeC3xLoOb+tQl3zmwKlSlLVo9hzLu3N7+A2/R7HhJpvVLvb cg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:16 +0530", "Message-ID": "<20210623044702.4240-17-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "dR4aPDDKRPVke4uviNgNCP1dBr41Ja39", "X-Proofpoint-GUID": "dR4aPDDKRPVke4uviNgNCP1dBr41Ja39", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 16/62] net/cnxk: add Tx queue setup and release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "aDD tx queue setup and release for CN9K and CN10K.\nRelease is common while setup is platform dependent due\nto differences in fast path Tx queue structures.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/features/cnxk.ini | 1 +\n doc/guides/nics/features/cnxk_vec.ini | 1 +\n doc/guides/nics/features/cnxk_vf.ini | 1 +\n drivers/net/cnxk/cn10k_ethdev.c | 72 +++++++++++++++++++++++++\n drivers/net/cnxk/cn10k_ethdev.h | 13 +++++\n drivers/net/cnxk/cn10k_tx.h | 13 +++++\n drivers/net/cnxk/cn9k_ethdev.c | 70 +++++++++++++++++++++++++\n drivers/net/cnxk/cn9k_ethdev.h | 11 ++++\n drivers/net/cnxk/cn9k_tx.h | 13 +++++\n drivers/net/cnxk/cnxk_ethdev.c | 98 +++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 3 ++\n 11 files changed, 296 insertions(+)\n create mode 100644 drivers/net/cnxk/cn10k_tx.h\n create mode 100644 drivers/net/cnxk/cn9k_tx.h", "diff": "diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex a9d2b03..462d7c4 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -11,6 +11,7 @@ Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\n+Runtime Tx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n Linux = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex 6a8ca1f..09e0d3a 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -11,6 +11,7 @@ Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\n+Runtime Tx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n Linux = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex f761638..4a93a35 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -10,6 +10,7 @@ Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\n+Runtime Tx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n Linux = Y\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex b87c4e5..454c8ca 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -2,6 +2,77 @@\n * Copyright(C) 2021 Marvell.\n */\n #include \"cn10k_ethdev.h\"\n+#include \"cn10k_tx.h\"\n+\n+static void\n+nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,\n+\t\t uint16_t qid)\n+{\n+\tstruct nix_send_ext_s *send_hdr_ext;\n+\tunion nix_send_hdr_w0_u send_hdr_w0;\n+\tunion nix_send_sg_s sg_w0;\n+\n+\tRTE_SET_USED(dev);\n+\n+\t/* Initialize the fields based on basic single segment packet */\n+\tmemset(&txq->cmd, 0, sizeof(txq->cmd));\n+\tsend_hdr_w0.u = 0;\n+\tsg_w0.u = 0;\n+\n+\tif (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n+\t\tsend_hdr_w0.sizem1 = 2;\n+\n+\t\tsend_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0];\n+\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n+\t} else {\n+\t\t/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */\n+\t\tsend_hdr_w0.sizem1 = 1;\n+\t}\n+\n+\tsend_hdr_w0.sq = qid;\n+\tsg_w0.subdc = NIX_SUBDC_SG;\n+\tsg_w0.segs = 1;\n+\tsg_w0.ld_type = NIX_SENDLDTYPE_LDD;\n+\n+\ttxq->send_hdr_w0 = send_hdr_w0.u;\n+\ttxq->sg_w0 = sg_w0.u;\n+\n+\trte_wmb();\n+}\n+\n+static int\n+cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t uint16_t nb_desc, unsigned int socket,\n+\t\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cn10k_eth_txq *txq;\n+\tstruct roc_nix_sq *sq;\n+\tint rc;\n+\n+\tRTE_SET_USED(socket);\n+\n+\t/* Common Tx queue setup */\n+\trc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,\n+\t\t\t\t sizeof(struct cn10k_eth_txq), tx_conf);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tsq = &dev->sqs[qid];\n+\t/* Update fast path queue */\n+\ttxq = eth_dev->data->tx_queues[qid];\n+\ttxq->fc_mem = sq->fc;\n+\t/* Store lmt base in tx queue for easy access */\n+\ttxq->lmt_base = dev->nix.lmt_base;\n+\ttxq->io_addr = sq->io_addr;\n+\ttxq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;\n+\ttxq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;\n+\n+\tnix_form_default_desc(dev, txq, qid);\n+\ttxq->lso_tun_fmt = dev->lso_tun_fmt;\n+\treturn 0;\n+}\n \n static int\n cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n@@ -76,6 +147,7 @@ nix_eth_dev_ops_override(void)\n \n \t/* Update platform specific ops */\n \tcnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;\n+\tcnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;\n \tcnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;\n }\n \ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex 08e11bb..18deb95 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -6,6 +6,19 @@\n \n #include <cnxk_ethdev.h>\n \n+struct cn10k_eth_txq {\n+\tuint64_t send_hdr_w0;\n+\tuint64_t sg_w0;\n+\tint64_t fc_cache_pkts;\n+\tuint64_t *fc_mem;\n+\tuintptr_t lmt_base;\n+\trte_iova_t io_addr;\n+\tuint16_t sqes_per_sqb_log2;\n+\tint16_t nb_sqb_bufs_adj;\n+\tuint64_t cmd[4];\n+\tuint64_t lso_tun_fmt;\n+} __plt_cache_aligned;\n+\n struct cn10k_eth_rxq {\n \tuint64_t mbuf_initializer;\n \tuintptr_t desc;\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nnew file mode 100644\nindex 0000000..39d4755\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CN10K_TX_H__\n+#define __CN10K_TX_H__\n+\n+#define NIX_TX_OFFLOAD_VLAN_QINQ_F BIT(2)\n+#define NIX_TX_OFFLOAD_TSO_F\t BIT(4)\n+\n+#define NIX_TX_NEED_EXT_HDR \\\n+\t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)\n+\n+#endif /* __CN10K_TX_H__ */\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex 2ab035e..5c696c8 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -2,6 +2,75 @@\n * Copyright(C) 2021 Marvell.\n */\n #include \"cn9k_ethdev.h\"\n+#include \"cn9k_tx.h\"\n+\n+static void\n+nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,\n+\t\t uint16_t qid)\n+{\n+\tstruct nix_send_ext_s *send_hdr_ext;\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tunion nix_send_sg_s *sg;\n+\n+\tRTE_SET_USED(dev);\n+\n+\t/* Initialize the fields based on basic single segment packet */\n+\tmemset(&txq->cmd, 0, sizeof(txq->cmd));\n+\n+\tif (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n+\t\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n+\t\tsend_hdr->w0.sizem1 = 2;\n+\n+\t\tsend_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];\n+\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n+\t\tsg = (union nix_send_sg_s *)&txq->cmd[4];\n+\t} else {\n+\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n+\t\t/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */\n+\t\tsend_hdr->w0.sizem1 = 1;\n+\t\tsg = (union nix_send_sg_s *)&txq->cmd[2];\n+\t}\n+\n+\tsend_hdr->w0.sq = qid;\n+\tsg->subdc = NIX_SUBDC_SG;\n+\tsg->segs = 1;\n+\tsg->ld_type = NIX_SENDLDTYPE_LDD;\n+\n+\trte_wmb();\n+}\n+\n+static int\n+cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\tuint16_t nb_desc, unsigned int socket,\n+\t\t\tconst struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cn9k_eth_txq *txq;\n+\tstruct roc_nix_sq *sq;\n+\tint rc;\n+\n+\tRTE_SET_USED(socket);\n+\n+\t/* Common Tx queue setup */\n+\trc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc,\n+\t\t\t\t sizeof(struct cn9k_eth_txq), tx_conf);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tsq = &dev->sqs[qid];\n+\t/* Update fast path queue */\n+\ttxq = eth_dev->data->tx_queues[qid];\n+\ttxq->fc_mem = sq->fc;\n+\ttxq->lmt_addr = sq->lmt_addr;\n+\ttxq->io_addr = sq->io_addr;\n+\ttxq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj;\n+\ttxq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2;\n+\n+\tnix_form_default_desc(dev, txq, qid);\n+\ttxq->lso_tun_fmt = dev->lso_tun_fmt;\n+\treturn 0;\n+}\n \n static int\n cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n@@ -87,6 +156,7 @@ nix_eth_dev_ops_override(void)\n \n \t/* Update platform specific ops */\n \tcnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;\n+\tcnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;\n \tcnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;\n }\n \ndiff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h\nindex 6384609..bd7bf50 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.h\n+++ b/drivers/net/cnxk/cn9k_ethdev.h\n@@ -6,6 +6,17 @@\n \n #include <cnxk_ethdev.h>\n \n+struct cn9k_eth_txq {\n+\tuint64_t cmd[8];\n+\tint64_t fc_cache_pkts;\n+\tuint64_t *fc_mem;\n+\tvoid *lmt_addr;\n+\trte_iova_t io_addr;\n+\tuint64_t lso_tun_fmt;\n+\tuint16_t sqes_per_sqb_log2;\n+\tint16_t nb_sqb_bufs_adj;\n+} __plt_cache_aligned;\n+\n struct cn9k_eth_rxq {\n \tuint64_t mbuf_initializer;\n \tuint64_t data_off;\ndiff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h\nnew file mode 100644\nindex 0000000..bb6379b\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_tx.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CN9K_TX_H__\n+#define __CN9K_TX_H__\n+\n+#define NIX_TX_OFFLOAD_VLAN_QINQ_F BIT(2)\n+#define NIX_TX_OFFLOAD_TSO_F\t BIT(4)\n+\n+#define NIX_TX_NEED_EXT_HDR \\\n+\t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)\n+\n+#endif /* __CN9K_TX_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 2775fe4..424512c 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -66,6 +66,103 @@ cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)\n \treturn *tmp;\n }\n \n+static inline uint8_t\n+nix_sq_max_sqe_sz(struct cnxk_eth_dev *dev)\n+{\n+\t/*\n+\t * Maximum three segments can be supported with W8, Choose\n+\t * NIX_MAXSQESZ_W16 for multi segment offload.\n+\t */\n+\tif (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)\n+\t\treturn NIX_MAXSQESZ_W16;\n+\telse\n+\t\treturn NIX_MAXSQESZ_W8;\n+}\n+\n+int\n+cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\tuint16_t nb_desc, uint16_t fp_tx_q_sz,\n+\t\t\tconst struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tconst struct eth_dev_ops *dev_ops = eth_dev->dev_ops;\n+\tstruct cnxk_eth_txq_sp *txq_sp;\n+\tstruct roc_nix_sq *sq;\n+\tsize_t txq_sz;\n+\tint rc;\n+\n+\t/* Free memory prior to re-allocation if needed. */\n+\tif (eth_dev->data->tx_queues[qid] != NULL) {\n+\t\tplt_nix_dbg(\"Freeing memory prior to re-allocation %d\", qid);\n+\t\tdev_ops->tx_queue_release(eth_dev->data->tx_queues[qid]);\n+\t\teth_dev->data->tx_queues[qid] = NULL;\n+\t}\n+\n+\t/* Setup ROC SQ */\n+\tsq = &dev->sqs[qid];\n+\tsq->qid = qid;\n+\tsq->nb_desc = nb_desc;\n+\tsq->max_sqe_sz = nix_sq_max_sqe_sz(dev);\n+\n+\trc = roc_nix_sq_init(&dev->nix, sq);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init sq=%d, rc=%d\", qid, rc);\n+\t\treturn rc;\n+\t}\n+\n+\trc = -ENOMEM;\n+\ttxq_sz = sizeof(struct cnxk_eth_txq_sp) + fp_tx_q_sz;\n+\ttxq_sp = plt_zmalloc(txq_sz, PLT_CACHE_LINE_SIZE);\n+\tif (!txq_sp) {\n+\t\tplt_err(\"Failed to alloc tx queue mem\");\n+\t\trc |= roc_nix_sq_fini(sq);\n+\t\treturn rc;\n+\t}\n+\n+\ttxq_sp->dev = dev;\n+\ttxq_sp->qid = qid;\n+\ttxq_sp->qconf.conf.tx = *tx_conf;\n+\ttxq_sp->qconf.nb_desc = nb_desc;\n+\n+\tplt_nix_dbg(\"sq=%d fc=%p offload=0x%\" PRIx64 \" lmt_addr=%p\"\n+\t\t \" nb_sqb_bufs=%d sqes_per_sqb_log2=%d\",\n+\t\t qid, sq->fc, dev->tx_offloads, sq->lmt_addr,\n+\t\t sq->nb_sqb_bufs, sq->sqes_per_sqb_log2);\n+\n+\t/* Store start of fast path area */\n+\teth_dev->data->tx_queues[qid] = txq_sp + 1;\n+\teth_dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\treturn 0;\n+}\n+\n+static void\n+cnxk_nix_tx_queue_release(void *txq)\n+{\n+\tstruct cnxk_eth_txq_sp *txq_sp;\n+\tstruct cnxk_eth_dev *dev;\n+\tstruct roc_nix_sq *sq;\n+\tuint16_t qid;\n+\tint rc;\n+\n+\tif (!txq)\n+\t\treturn;\n+\n+\ttxq_sp = cnxk_eth_txq_to_sp(txq);\n+\tdev = txq_sp->dev;\n+\tqid = txq_sp->qid;\n+\n+\tplt_nix_dbg(\"Releasing txq %u\", qid);\n+\n+\t/* Cleanup ROC SQ */\n+\tsq = &dev->sqs[qid];\n+\trc = roc_nix_sq_fini(sq);\n+\tif (rc)\n+\t\tplt_err(\"Failed to cleanup sq, rc=%d\", rc);\n+\n+\t/* Finally free */\n+\tplt_free(txq_sp);\n+}\n+\n int\n cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\tuint16_t nb_desc, uint16_t fp_rx_q_sz,\n@@ -773,6 +870,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.dev_infos_get = cnxk_nix_info_get,\n \t.link_update = cnxk_nix_link_update,\n+\t.tx_queue_release = cnxk_nix_tx_queue_release,\n \t.rx_queue_release = cnxk_nix_rx_queue_release,\n };\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 4a7c2ca..ef8e408 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -197,6 +197,9 @@ int cnxk_nix_remove(struct rte_pci_device *pci_dev);\n int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_dev_info *dev_info);\n int cnxk_nix_configure(struct rte_eth_dev *eth_dev);\n+int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t uint16_t nb_desc, uint16_t fp_tx_q_sz,\n+\t\t\t const struct rte_eth_txconf *tx_conf);\n int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\t uint16_t nb_desc, uint16_t fp_rx_q_sz,\n \t\t\t const struct rte_eth_rxconf *rx_conf,\n", "prefixes": [ "v4", "16/62" ] }