Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94709/?format=api
{ "id": 94709, "url": "https://patches.dpdk.org/api/patches/94709/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-14-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-14-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-14-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:13", "name": "[v4,13/62] net/cnxk: add device configuration operation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d285df9b9807547004eaff7107330a2ca9f328ab", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-14-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94709/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94709/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 65B2DA0C41;\n\tWed, 23 Jun 2021 06:48:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C6FCE4114B;\n\tWed, 23 Jun 2021 06:48:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E2AD3410E6\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:02 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k9og025587 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:02 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gjp-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:02 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:59 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:59 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id C51585B6936;\n Tue, 22 Jun 2021 21:47:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=kblZ3PzYYwCBDXVF9/AceNCjrYhmp0QViJPVYDTwVPM=;\n b=YMRdTR0xgf9j5GlLXgSo/lO2SHKsSpVWCqdgL4esTPpEa57MEzXQydWAHRSDDuB2FTXc\n raY2mwd20p7y3xJmOiC8qHN3LQg5zZ5UnMpvTAtrT9SdbhjN8jgZV4Z1SkdFGocyu6fF\n 5g4SelZLYnVF/xCi130DQ028j3mRagP+eexABCNvuZIYXPTn7l8AhWgBlN9uWSWdS65d\n vrdr34C19xqT4WY2Q5z9zvOnAmuEzSE85l/Ior3iXZ02IFUKwxYa+SlVLIAfunPWvN22\n uEfs5Sok6jFfkURJ1o1YigG33n3A9FImUugrr39mq4pg8gmXm5MxX64sPRT4KaudyN39 Lg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:13 +0530", "Message-ID": "<20210623044702.4240-14-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "CS9njC6UwAqVV1Lbz4BYwz15zEfCuYMI", "X-Proofpoint-GUID": "CS9njC6UwAqVV1Lbz4BYwz15zEfCuYMI", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 13/62] net/cnxk: add device configuration\n operation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add device configuration op for CN9K and CN10K. Most of the\ndevice configuration is common between two platforms except for\nsome supported offloads.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 2 +\n doc/guides/nics/features/cnxk.ini | 2 +\n doc/guides/nics/features/cnxk_vec.ini | 2 +\n doc/guides/nics/features/cnxk_vf.ini | 2 +\n drivers/net/cnxk/cn10k_ethdev.c | 34 ++\n drivers/net/cnxk/cn9k_ethdev.c | 45 +++\n drivers/net/cnxk/cnxk_ethdev.c | 568 ++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 85 +++++\n 8 files changed, 740 insertions(+)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 6bd410b..0c2ea89 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -18,6 +18,8 @@ Features of the CNXK Ethdev PMD are:\n \n - SR-IOV VF\n - Lock-free Tx queue\n+- Multiple queues for TX and RX\n+- Receiver Side Scaling (RSS)\n \n Prerequisites\n -------------\ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex b426340..96dba2a 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -8,6 +8,8 @@ Speed capabilities = Y\n Lock-free Tx queue = Y\n SR-IOV = Y\n Multiprocess aware = Y\n+RSS hash = Y\n+Inner RSS = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex 292ac1e..616991c 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -8,6 +8,8 @@ Speed capabilities = Y\n Lock-free Tx queue = Y\n SR-IOV = Y\n Multiprocess aware = Y\n+RSS hash = Y\n+Inner RSS = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex bc2eb8a..a0bd2f1 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -7,6 +7,8 @@\n Speed capabilities = Y\n Lock-free Tx queue = Y\n Multiprocess aware = Y\n+RSS hash = Y\n+Inner RSS = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex ff8ce31..d971bbd 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -4,6 +4,38 @@\n #include \"cn10k_ethdev.h\"\n \n static int\n+cn10k_nix_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tint rc;\n+\n+\t/* Common nix configure */\n+\trc = cnxk_nix_configure(eth_dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tplt_nix_dbg(\"Configured port%d platform specific rx_offload_flags=%x\"\n+\t\t \" tx_offload_flags=0x%x\",\n+\t\t eth_dev->data->port_id, dev->rx_offload_flags,\n+\t\t dev->tx_offload_flags);\n+\treturn 0;\n+}\n+\n+/* Update platform specific eth dev ops */\n+static void\n+nix_eth_dev_ops_override(void)\n+{\n+\tstatic int init_once;\n+\n+\tif (init_once)\n+\t\treturn;\n+\tinit_once = 1;\n+\n+\t/* Update platform specific ops */\n+\tcnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;\n+}\n+\n+static int\n cn10k_nix_remove(struct rte_pci_device *pci_dev)\n {\n \treturn cnxk_nix_remove(pci_dev);\n@@ -26,6 +58,8 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\treturn rc;\n \t}\n \n+\tnix_eth_dev_ops_override();\n+\n \t/* Common probe */\n \trc = cnxk_nix_probe(pci_drv, pci_dev);\n \tif (rc)\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex 98d2d3a..2fb7c14 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -4,6 +4,49 @@\n #include \"cn9k_ethdev.h\"\n \n static int\n+cn9k_nix_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_conf *conf = ð_dev->data->dev_conf;\n+\tstruct rte_eth_txmode *txmode = &conf->txmode;\n+\tint rc;\n+\n+\t/* Platform specific checks */\n+\tif ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) &&\n+\t (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&\n+\t ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||\n+\t (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {\n+\t\tplt_err(\"Outer IP and SCTP checksum unsupported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Common nix configure */\n+\trc = cnxk_nix_configure(eth_dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tplt_nix_dbg(\"Configured port%d platform specific rx_offload_flags=%x\"\n+\t\t \" tx_offload_flags=0x%x\",\n+\t\t eth_dev->data->port_id, dev->rx_offload_flags,\n+\t\t dev->tx_offload_flags);\n+\treturn 0;\n+}\n+\n+/* Update platform specific eth dev ops */\n+static void\n+nix_eth_dev_ops_override(void)\n+{\n+\tstatic int init_once;\n+\n+\tif (init_once)\n+\t\treturn;\n+\tinit_once = 1;\n+\n+\t/* Update platform specific ops */\n+\tcnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;\n+}\n+\n+static int\n cn9k_nix_remove(struct rte_pci_device *pci_dev)\n {\n \treturn cnxk_nix_remove(pci_dev);\n@@ -27,6 +70,8 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\treturn rc;\n \t}\n \n+\tnix_eth_dev_ops_override();\n+\n \t/* Common probe */\n \trc = cnxk_nix_probe(pci_drv, pci_dev);\n \tif (rc)\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 066e01c..251d6eb 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -37,6 +37,567 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev)\n \treturn speed_capa;\n }\n \n+uint32_t\n+cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,\n+\t\t uint8_t rss_level)\n+{\n+\tuint32_t flow_key_type[RSS_MAX_LEVELS][6] = {\n+\t\t{FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6, FLOW_KEY_TYPE_TCP,\n+\t\t FLOW_KEY_TYPE_UDP, FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC},\n+\t\t{FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,\n+\t\t FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,\n+\t\t FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC},\n+\t\t{FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,\n+\t\t FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,\n+\t\t FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,\n+\t\t FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,\n+\t\t FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,\n+\t\t FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC}\n+\t};\n+\tuint32_t flowkey_cfg = 0;\n+\n+\tdev->ethdev_rss_hf = ethdev_rss;\n+\n+\tif (ethdev_rss & ETH_RSS_L2_PAYLOAD)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;\n+\n+\tif (ethdev_rss & ETH_RSS_C_VLAN)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_VLAN;\n+\n+\tif (ethdev_rss & ETH_RSS_L3_SRC_ONLY)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;\n+\n+\tif (ethdev_rss & ETH_RSS_L3_DST_ONLY)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_L3_DST;\n+\n+\tif (ethdev_rss & ETH_RSS_L4_SRC_ONLY)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;\n+\n+\tif (ethdev_rss & ETH_RSS_L4_DST_ONLY)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_L4_DST;\n+\n+\tif (ethdev_rss & RSS_IPV4_ENABLE)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];\n+\n+\tif (ethdev_rss & RSS_IPV6_ENABLE)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_TCP)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_UDP)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_SCTP)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_L2_PAYLOAD)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];\n+\n+\tif (ethdev_rss & RSS_IPV6_EX_ENABLE)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;\n+\n+\tif (ethdev_rss & ETH_RSS_PORT)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_PORT;\n+\n+\tif (ethdev_rss & ETH_RSS_NVGRE)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_NVGRE;\n+\n+\tif (ethdev_rss & ETH_RSS_VXLAN)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_VXLAN;\n+\n+\tif (ethdev_rss & ETH_RSS_GENEVE)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_GENEVE;\n+\n+\tif (ethdev_rss & ETH_RSS_GTPU)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_GTPU;\n+\n+\treturn flowkey_cfg;\n+}\n+\n+static void\n+nix_free_queue_mem(struct cnxk_eth_dev *dev)\n+{\n+\tplt_free(dev->rqs);\n+\tplt_free(dev->cqs);\n+\tplt_free(dev->sqs);\n+\tdev->rqs = NULL;\n+\tdev->cqs = NULL;\n+\tdev->sqs = NULL;\n+}\n+\n+static int\n+nix_rss_default_setup(struct cnxk_eth_dev *dev)\n+{\n+\tstruct rte_eth_dev *eth_dev = dev->eth_dev;\n+\tuint8_t rss_hash_level;\n+\tuint32_t flowkey_cfg;\n+\tuint64_t rss_hf;\n+\n+\trss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;\n+\trss_hash_level = ETH_RSS_LEVEL(rss_hf);\n+\tif (rss_hash_level)\n+\t\trss_hash_level -= 1;\n+\n+\tflowkey_cfg = cnxk_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);\n+\treturn roc_nix_rss_default_setup(&dev->nix, flowkey_cfg);\n+}\n+\n+static int\n+nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tconst struct eth_dev_ops *dev_ops = eth_dev->dev_ops;\n+\tstruct cnxk_eth_qconf *tx_qconf = NULL;\n+\tstruct cnxk_eth_qconf *rx_qconf = NULL;\n+\tstruct cnxk_eth_rxq_sp *rxq_sp;\n+\tstruct cnxk_eth_txq_sp *txq_sp;\n+\tint i, nb_rxq, nb_txq;\n+\tvoid **txq, **rxq;\n+\n+\tnb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);\n+\tnb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);\n+\n+\ttx_qconf = malloc(nb_txq * sizeof(*tx_qconf));\n+\tif (tx_qconf == NULL) {\n+\t\tplt_err(\"Failed to allocate memory for tx_qconf\");\n+\t\tgoto fail;\n+\t}\n+\n+\trx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));\n+\tif (rx_qconf == NULL) {\n+\t\tplt_err(\"Failed to allocate memory for rx_qconf\");\n+\t\tgoto fail;\n+\t}\n+\n+\ttxq = eth_dev->data->tx_queues;\n+\tfor (i = 0; i < nb_txq; i++) {\n+\t\tif (txq[i] == NULL) {\n+\t\t\ttx_qconf[i].valid = false;\n+\t\t\tplt_info(\"txq[%d] is already released\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\t\ttxq_sp = cnxk_eth_txq_to_sp(txq[i]);\n+\t\tmemcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));\n+\t\ttx_qconf[i].valid = true;\n+\t\tdev_ops->tx_queue_release(txq[i]);\n+\t\teth_dev->data->tx_queues[i] = NULL;\n+\t}\n+\n+\trxq = eth_dev->data->rx_queues;\n+\tfor (i = 0; i < nb_rxq; i++) {\n+\t\tif (rxq[i] == NULL) {\n+\t\t\trx_qconf[i].valid = false;\n+\t\t\tplt_info(\"rxq[%d] is already released\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\t\trxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);\n+\t\tmemcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));\n+\t\trx_qconf[i].valid = true;\n+\t\tdev_ops->rx_queue_release(rxq[i]);\n+\t\teth_dev->data->rx_queues[i] = NULL;\n+\t}\n+\n+\tdev->tx_qconf = tx_qconf;\n+\tdev->rx_qconf = rx_qconf;\n+\treturn 0;\n+\n+fail:\n+\tfree(tx_qconf);\n+\tfree(rx_qconf);\n+\treturn -ENOMEM;\n+}\n+\n+static int\n+nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tconst struct eth_dev_ops *dev_ops = eth_dev->dev_ops;\n+\tstruct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;\n+\tstruct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;\n+\tint rc, i, nb_rxq, nb_txq;\n+\tvoid **txq, **rxq;\n+\n+\tnb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);\n+\tnb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);\n+\n+\trc = -ENOMEM;\n+\t/* Setup tx & rx queues with previous configuration so\n+\t * that the queues can be functional in cases like ports\n+\t * are started without re configuring queues.\n+\t *\n+\t * Usual re config sequence is like below:\n+\t * port_configure() {\n+\t * if(reconfigure) {\n+\t * queue_release()\n+\t * queue_setup()\n+\t * }\n+\t * queue_configure() {\n+\t * queue_release()\n+\t * queue_setup()\n+\t * }\n+\t * }\n+\t * port_start()\n+\t *\n+\t * In some application's control path, queue_configure() would\n+\t * NOT be invoked for TXQs/RXQs in port_configure().\n+\t * In such cases, queues can be functional after start as the\n+\t * queues are already setup in port_configure().\n+\t */\n+\tfor (i = 0; i < nb_txq; i++) {\n+\t\tif (!tx_qconf[i].valid)\n+\t\t\tcontinue;\n+\t\trc = dev_ops->tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc, 0,\n+\t\t\t\t\t &tx_qconf[i].conf.tx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to setup tx queue rc=%d\", rc);\n+\t\t\ttxq = eth_dev->data->tx_queues;\n+\t\t\tfor (i -= 1; i >= 0; i--)\n+\t\t\t\tdev_ops->tx_queue_release(txq[i]);\n+\t\t\tgoto fail;\n+\t\t}\n+\t}\n+\n+\tfree(tx_qconf);\n+\ttx_qconf = NULL;\n+\n+\tfor (i = 0; i < nb_rxq; i++) {\n+\t\tif (!rx_qconf[i].valid)\n+\t\t\tcontinue;\n+\t\trc = dev_ops->rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc, 0,\n+\t\t\t\t\t &rx_qconf[i].conf.rx,\n+\t\t\t\t\t rx_qconf[i].mp);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to setup rx queue rc=%d\", rc);\n+\t\t\trxq = eth_dev->data->rx_queues;\n+\t\t\tfor (i -= 1; i >= 0; i--)\n+\t\t\t\tdev_ops->rx_queue_release(rxq[i]);\n+\t\t\tgoto tx_queue_release;\n+\t\t}\n+\t}\n+\n+\tfree(rx_qconf);\n+\trx_qconf = NULL;\n+\n+\treturn 0;\n+\n+tx_queue_release:\n+\ttxq = eth_dev->data->tx_queues;\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++)\n+\t\tdev_ops->tx_queue_release(txq[i]);\n+fail:\n+\tif (tx_qconf)\n+\t\tfree(tx_qconf);\n+\tif (rx_qconf)\n+\t\tfree(rx_qconf);\n+\n+\treturn rc;\n+}\n+\n+static uint16_t\n+nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)\n+{\n+\tRTE_SET_USED(queue);\n+\tRTE_SET_USED(mbufs);\n+\tRTE_SET_USED(pkts);\n+\n+\treturn 0;\n+}\n+\n+static void\n+nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)\n+{\n+\t/* These dummy functions are required for supporting\n+\t * some applications which reconfigure queues without\n+\t * stopping tx burst and rx burst threads(eg kni app)\n+\t * When the queues context is saved, txq/rxqs are released\n+\t * which caused app crash since rx/tx burst is still\n+\t * on different lcores\n+\t */\n+\teth_dev->tx_pkt_burst = nix_eth_nop_burst;\n+\teth_dev->rx_pkt_burst = nix_eth_nop_burst;\n+\trte_mb();\n+}\n+\n+static int\n+nix_lso_tun_fmt_update(struct cnxk_eth_dev *dev)\n+{\n+\tuint8_t udp_tun[ROC_NIX_LSO_TUN_MAX];\n+\tuint8_t tun[ROC_NIX_LSO_TUN_MAX];\n+\tstruct roc_nix *nix = &dev->nix;\n+\tint rc;\n+\n+\trc = roc_nix_lso_fmt_get(nix, udp_tun, tun);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tdev->lso_tun_fmt = ((uint64_t)tun[ROC_NIX_LSO_TUN_V4V4] |\n+\t\t\t (uint64_t)tun[ROC_NIX_LSO_TUN_V4V6] << 8 |\n+\t\t\t (uint64_t)tun[ROC_NIX_LSO_TUN_V6V4] << 16 |\n+\t\t\t (uint64_t)tun[ROC_NIX_LSO_TUN_V6V6] << 24);\n+\n+\tdev->lso_tun_fmt |= ((uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V4] << 32 |\n+\t\t\t (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V4V6] << 40 |\n+\t\t\t (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V4] << 48 |\n+\t\t\t (uint64_t)udp_tun[ROC_NIX_LSO_TUN_V6V6] << 56);\n+\treturn 0;\n+}\n+\n+static int\n+nix_lso_fmt_setup(struct cnxk_eth_dev *dev)\n+{\n+\tstruct roc_nix *nix = &dev->nix;\n+\tint rc;\n+\n+\t/* Nothing much to do if offload is not enabled */\n+\tif (!(dev->tx_offloads &\n+\t (DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |\n+\t DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)))\n+\t\treturn 0;\n+\n+\t/* Setup LSO formats in AF. Its a no-op if other ethdev has\n+\t * already set it up\n+\t */\n+\trc = roc_nix_lso_fmt_setup(nix);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn nix_lso_tun_fmt_update(dev);\n+}\n+\n+int\n+cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_eth_conf *conf = &data->dev_conf;\n+\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n+\tstruct rte_eth_txmode *txmode = &conf->txmode;\n+\tchar ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];\n+\tstruct roc_nix *nix = &dev->nix;\n+\tstruct rte_ether_addr *ea;\n+\tuint8_t nb_rxq, nb_txq;\n+\tuint64_t rx_cfg;\n+\tvoid *qs;\n+\tint rc;\n+\n+\trc = -EINVAL;\n+\n+\t/* Sanity checks */\n+\tif (rte_eal_has_hugepages() == 0) {\n+\t\tplt_err(\"Huge page is not configured\");\n+\t\tgoto fail_configure;\n+\t}\n+\n+\tif (conf->dcb_capability_en == 1) {\n+\t\tplt_err(\"dcb enable is not supported\");\n+\t\tgoto fail_configure;\n+\t}\n+\n+\tif (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {\n+\t\tplt_err(\"Flow director is not supported\");\n+\t\tgoto fail_configure;\n+\t}\n+\n+\tif (rxmode->mq_mode != ETH_MQ_RX_NONE &&\n+\t rxmode->mq_mode != ETH_MQ_RX_RSS) {\n+\t\tplt_err(\"Unsupported mq rx mode %d\", rxmode->mq_mode);\n+\t\tgoto fail_configure;\n+\t}\n+\n+\tif (txmode->mq_mode != ETH_MQ_TX_NONE) {\n+\t\tplt_err(\"Unsupported mq tx mode %d\", txmode->mq_mode);\n+\t\tgoto fail_configure;\n+\t}\n+\n+\t/* Free the resources allocated from the previous configure */\n+\tif (dev->configured == 1) {\n+\t\t/* Unregister queue irq's */\n+\t\troc_nix_unregister_queue_irqs(nix);\n+\n+\t\t/* Unregister CQ irqs if present */\n+\t\tif (eth_dev->data->dev_conf.intr_conf.rxq)\n+\t\t\troc_nix_unregister_cq_irqs(nix);\n+\n+\t\t/* Set no-op functions */\n+\t\tnix_set_nop_rxtx_function(eth_dev);\n+\t\t/* Store queue config for later */\n+\t\trc = nix_store_queue_cfg_and_then_release(eth_dev);\n+\t\tif (rc)\n+\t\t\tgoto fail_configure;\n+\t\troc_nix_tm_fini(nix);\n+\t\troc_nix_lf_free(nix);\n+\t}\n+\n+\tdev->rx_offloads = rxmode->offloads;\n+\tdev->tx_offloads = txmode->offloads;\n+\n+\t/* Prepare rx cfg */\n+\trx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;\n+\tif (dev->rx_offloads &\n+\t (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) {\n+\t\trx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;\n+\t\trx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;\n+\t}\n+\trx_cfg |= (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |\n+\t\t ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |\n+\t\t ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);\n+\n+\tnb_rxq = RTE_MAX(data->nb_rx_queues, 1);\n+\tnb_txq = RTE_MAX(data->nb_tx_queues, 1);\n+\n+\t/* Alloc a nix lf */\n+\trc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init nix_lf rc=%d\", rc);\n+\t\tgoto fail_configure;\n+\t}\n+\n+\tnb_rxq = data->nb_rx_queues;\n+\tnb_txq = data->nb_tx_queues;\n+\trc = -ENOMEM;\n+\tif (nb_rxq) {\n+\t\t/* Allocate memory for roc rq's and cq's */\n+\t\tqs = plt_zmalloc(sizeof(struct roc_nix_rq) * nb_rxq, 0);\n+\t\tif (!qs) {\n+\t\t\tplt_err(\"Failed to alloc rqs\");\n+\t\t\tgoto free_nix_lf;\n+\t\t}\n+\t\tdev->rqs = qs;\n+\n+\t\tqs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);\n+\t\tif (!qs) {\n+\t\t\tplt_err(\"Failed to alloc cqs\");\n+\t\t\tgoto free_nix_lf;\n+\t\t}\n+\t\tdev->cqs = qs;\n+\t}\n+\n+\tif (nb_txq) {\n+\t\t/* Allocate memory for roc sq's */\n+\t\tqs = plt_zmalloc(sizeof(struct roc_nix_sq) * nb_txq, 0);\n+\t\tif (!qs) {\n+\t\t\tplt_err(\"Failed to alloc sqs\");\n+\t\t\tgoto free_nix_lf;\n+\t\t}\n+\t\tdev->sqs = qs;\n+\t}\n+\n+\t/* Re-enable NIX LF error interrupts */\n+\troc_nix_err_intr_ena_dis(nix, true);\n+\troc_nix_ras_intr_ena_dis(nix, true);\n+\n+\tif (nix->rx_ptp_ena) {\n+\t\tplt_err(\"Both PTP and switch header enabled\");\n+\t\tgoto free_nix_lf;\n+\t}\n+\n+\t/* Setup LSO if needed */\n+\trc = nix_lso_fmt_setup(dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup nix lso format fields, rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n+\t/* Configure RSS */\n+\trc = nix_rss_default_setup(dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to configure rss rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n+\t/* Init the default TM scheduler hierarchy */\n+\trc = roc_nix_tm_init(nix);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init traffic manager, rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n+\trc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable default tm hierarchy, rc=%d\", rc);\n+\t\tgoto tm_fini;\n+\t}\n+\n+\t/* Register queue IRQs */\n+\trc = roc_nix_register_queue_irqs(nix);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to register queue interrupts rc=%d\", rc);\n+\t\tgoto tm_fini;\n+\t}\n+\n+\t/* Register cq IRQs */\n+\tif (eth_dev->data->dev_conf.intr_conf.rxq) {\n+\t\tif (eth_dev->data->nb_rx_queues > dev->nix.cints) {\n+\t\t\tplt_err(\"Rx interrupt cannot be enabled, rxq > %d\",\n+\t\t\t\tdev->nix.cints);\n+\t\t\tgoto q_irq_fini;\n+\t\t}\n+\t\t/* Rx interrupt feature cannot work with vector mode because,\n+\t\t * vector mode does not process packets unless min 4 pkts are\n+\t\t * received, while cq interrupts are generated even for 1 pkt\n+\t\t * in the CQ.\n+\t\t */\n+\t\tdev->scalar_ena = true;\n+\n+\t\trc = roc_nix_register_cq_irqs(nix);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to register CQ interrupts rc=%d\", rc);\n+\t\t\tgoto q_irq_fini;\n+\t\t}\n+\t}\n+\n+\t/* Configure loop back mode */\n+\trc = roc_nix_mac_loopback_enable(nix,\n+\t\t\t\t\t eth_dev->data->dev_conf.lpbk_mode);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to configure cgx loop back mode rc=%d\", rc);\n+\t\tgoto cq_fini;\n+\t}\n+\n+\t/*\n+\t * Restore queue config when reconfigure followed by\n+\t * reconfigure and no queue configure invoked from application case.\n+\t */\n+\tif (dev->configured == 1) {\n+\t\trc = nix_restore_queue_cfg(eth_dev);\n+\t\tif (rc)\n+\t\t\tgoto cq_fini;\n+\t}\n+\n+\t/* Update the mac address */\n+\tea = eth_dev->data->mac_addrs;\n+\tmemcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n+\tif (rte_is_zero_ether_addr(ea))\n+\t\trte_eth_random_addr((uint8_t *)ea);\n+\n+\trte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);\n+\n+\tplt_nix_dbg(\"Configured port%d mac=%s nb_rxq=%d nb_txq=%d\"\n+\t\t \" rx_offloads=0x%\" PRIx64 \" tx_offloads=0x%\" PRIx64 \"\",\n+\t\t eth_dev->data->port_id, ea_fmt, nb_rxq, nb_txq,\n+\t\t dev->rx_offloads, dev->tx_offloads);\n+\n+\t/* All good */\n+\tdev->configured = 1;\n+\tdev->nb_rxq = data->nb_rx_queues;\n+\tdev->nb_txq = data->nb_tx_queues;\n+\treturn 0;\n+\n+cq_fini:\n+\troc_nix_unregister_cq_irqs(nix);\n+q_irq_fini:\n+\troc_nix_unregister_queue_irqs(nix);\n+tm_fini:\n+\troc_nix_tm_fini(nix);\n+free_nix_lf:\n+\tnix_free_queue_mem(dev);\n+\trc |= roc_nix_lf_free(nix);\n+fail_configure:\n+\tdev->configured = 0;\n+\treturn rc;\n+}\n+\n /* CNXK platform independent eth dev ops */\n struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.dev_infos_get = cnxk_nix_info_get,\n@@ -75,6 +636,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \tdev->eth_dev = eth_dev;\n+\tdev->configured = 0;\n \n \t/* For vfs, returned max_entries will be 0. but to keep default mac\n \t * address, one entry must be allocated. so setting up to 1.\n@@ -156,6 +718,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\t/* Clear the flag since we are closing down */\n+\tdev->configured = 0;\n+\n \troc_nix_npc_rx_ena_dis(nix, false);\n \n \t/* Free up SQs */\n@@ -182,6 +747,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \tif (eth_dev->data->dev_conf.intr_conf.rxq)\n \t\troc_nix_unregister_cq_irqs(nix);\n \n+\t/* Free ROC RQ's, SQ's and CQ's memory */\n+\tnix_free_queue_mem(dev);\n+\n \t/* Free nix lf resources */\n \trc = roc_nix_lf_free(nix);\n \tif (rc)\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 8d9a7e0..291f5f9 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -65,10 +65,50 @@\n \t DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \\\n \t DEV_RX_OFFLOAD_RSS_HASH)\n \n+#define RSS_IPV4_ENABLE \\\n+\t(ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \\\n+\t ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)\n+\n+#define RSS_IPV6_ENABLE \\\n+\t(ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \\\n+\t ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)\n+\n+#define RSS_IPV6_EX_ENABLE \\\n+\t(ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)\n+\n+#define RSS_MAX_LEVELS 3\n+\n+#define RSS_IPV4_INDEX 0\n+#define RSS_IPV6_INDEX 1\n+#define RSS_TCP_INDEX 2\n+#define RSS_UDP_INDEX 3\n+#define RSS_SCTP_INDEX 4\n+#define RSS_DMAC_INDEX 5\n+\n+struct cnxk_eth_qconf {\n+\tunion {\n+\t\tstruct rte_eth_txconf tx;\n+\t\tstruct rte_eth_rxconf rx;\n+\t} conf;\n+\tstruct rte_mempool *mp;\n+\tuint16_t nb_desc;\n+\tuint8_t valid;\n+};\n+\n struct cnxk_eth_dev {\n \t/* ROC NIX */\n \tstruct roc_nix nix;\n \n+\t/* ROC RQs, SQs and CQs */\n+\tstruct roc_nix_rq *rqs;\n+\tstruct roc_nix_sq *sqs;\n+\tstruct roc_nix_cq *cqs;\n+\n+\t/* Configured queue count */\n+\tuint16_t nb_rxq;\n+\tuint16_t nb_txq;\n+\tuint8_t configured;\n+\n \t/* Max macfilter entries */\n \tuint8_t max_mac_entries;\n \n@@ -90,17 +130,57 @@ struct cnxk_eth_dev {\n \tuint64_t rx_offload_capa;\n \tuint64_t tx_offload_capa;\n \tuint32_t speed_capa;\n+\t/* Configured Rx and Tx offloads */\n+\tuint64_t rx_offloads;\n+\tuint64_t tx_offloads;\n+\t/* Platform specific offload flags */\n+\tuint16_t rx_offload_flags;\n+\tuint16_t tx_offload_flags;\n+\n+\t/* ETHDEV RSS HF bitmask */\n+\tuint64_t ethdev_rss_hf;\n+\n+\t/* Saved qconf before lf realloc */\n+\tstruct cnxk_eth_qconf *tx_qconf;\n+\tstruct cnxk_eth_qconf *rx_qconf;\n \n \t/* Default mac address */\n \tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n+\n+\t/* LSO Tunnel format indices */\n+\tuint64_t lso_tun_fmt;\n };\n \n+struct cnxk_eth_rxq_sp {\n+\tstruct cnxk_eth_dev *dev;\n+\tstruct cnxk_eth_qconf qconf;\n+\tuint16_t qid;\n+} __plt_cache_aligned;\n+\n+struct cnxk_eth_txq_sp {\n+\tstruct cnxk_eth_dev *dev;\n+\tstruct cnxk_eth_qconf qconf;\n+\tuint16_t qid;\n+} __plt_cache_aligned;\n+\n static inline struct cnxk_eth_dev *\n cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n {\n \treturn eth_dev->data->dev_private;\n }\n \n+static inline struct cnxk_eth_rxq_sp *\n+cnxk_eth_rxq_to_sp(void *__rxq)\n+{\n+\treturn ((struct cnxk_eth_rxq_sp *)__rxq) - 1;\n+}\n+\n+static inline struct cnxk_eth_txq_sp *\n+cnxk_eth_txq_to_sp(void *__txq)\n+{\n+\treturn ((struct cnxk_eth_txq_sp *)__txq) - 1;\n+}\n+\n /* Common ethdev ops */\n extern struct eth_dev_ops cnxk_eth_dev_ops;\n \n@@ -110,6 +190,11 @@ int cnxk_nix_probe(struct rte_pci_driver *pci_drv,\n int cnxk_nix_remove(struct rte_pci_device *pci_dev);\n int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_dev_info *dev_info);\n+int cnxk_nix_configure(struct rte_eth_dev *eth_dev);\n+\n+/* RSS */\n+uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,\n+\t\t\t\tuint8_t rss_level);\n \n /* Devargs */\n int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,\n", "prefixes": [ "v4", "13/62" ] }