Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94702/?format=api
{ "id": 94702, "url": "https://patches.dpdk.org/api/patches/94702/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-7-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-7-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-7-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:06", "name": "[v4,06/62] common/cnxk: add provision to enable RED on RQ", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c7099236457dc50b1ada2b86ab85d7f590946dd3", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-7-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94702/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94702/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 61D7FA0C41;\n\tWed, 23 Jun 2021 06:48:05 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7D8A64111A;\n\tWed, 23 Jun 2021 06:47:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 18D2B41102\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:47:39 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4kORq026099 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:38 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1ghp-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:38 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:36 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:36 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id A11695B6937;\n Tue, 22 Jun 2021 21:47:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=8A8F6AFh4+vs4IX/rX0heRPWnavtjgPQQgqR4j3AUf8=;\n b=d+LBUq8hVBrhDuXgAoAeVGedsgVR8W5j+Kx+WNKPkQ8jTJOz5ZOig8Sx10WcTnAnqyZo\n NEaP9ngJ/LZVxfhPszL3PyjIjhnax85+VzkkOuHH6pjcCl78jGfIYKLund8NBIH4gDuA\n dxZezwXaSylG0ts1g9N+v7gM2LGtZe66F5jp0Pvot0umysdM7oCXc+HC/oVEtfQaGHXi\n FT19ae48G9sAar1tgMgYlxUt1CjYnuUoJQ9xXZLY4AUKKIiXQlsYigKVMz4f+qV56E8E\n 3cA95XFImckUzRqwd2AUnpZr+TjZeLC79BOLmjr/TKDDXmfcF8nZtRsWU+h3/hkTalNF bA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:06 +0530", "Message-ID": "<20210623044702.4240-7-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "66UDn67G42RMIpw_CQIYHgqUpJYsQrL5", "X-Proofpoint-GUID": "66UDn67G42RMIpw_CQIYHgqUpJYsQrL5", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 06/62] common/cnxk: add provision to enable\n RED on RQ", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nSend RED pass/drop levels based on rq configurations to kernel.\nFixed the aura and pool shift value calculation.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 8 ++++++\n drivers/common/cnxk/roc_nix_queue.c | 50 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_npa.c | 8 ++++--\n drivers/common/cnxk/roc_npa.h | 5 ++++\n 4 files changed, 69 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 6d9ac10..bb69027 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -161,6 +161,14 @@ struct roc_nix_rq {\n \tuint32_t vwqe_max_sz_exp;\n \tuint64_t vwqe_wait_tmo;\n \tuint64_t vwqe_aura_handle;\n+\t/* Average LPB aura level drop threshold for RED */\n+\tuint8_t red_drop;\n+\t/* Average LPB aura level pass threshold for RED */\n+\tuint8_t red_pass;\n+\t/* Average SPB aura level drop threshold for RED */\n+\tuint8_t spb_red_drop;\n+\t/* Average SPB aura level pass threshold for RED */\n+\tuint8_t spb_red_pass;\n \t/* End of Input parameters */\n \tstruct roc_nix *roc_nix;\n };\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 1c62aa2..0604e7a 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -119,6 +119,15 @@ rq_cn9k_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \taq->rq.qint_idx = rq->qid % nix->qints;\n \taq->rq.xqe_drop_ena = 1;\n \n+\t/* If RED enabled, then fill enable for all cases */\n+\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n+\t\taq->rq.spb_aura_pass = rq->spb_red_pass;\n+\t\taq->rq.lpb_aura_pass = rq->red_pass;\n+\n+\t\taq->rq.spb_aura_drop = rq->spb_red_drop;\n+\t\taq->rq.lpb_aura_drop = rq->red_drop;\n+\t}\n+\n \tif (cfg) {\n \t\tif (rq->sso_ena) {\n \t\t\t/* SSO mode */\n@@ -155,6 +164,14 @@ rq_cn9k_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \t\taq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;\n \t\taq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;\n \t\taq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;\n+\n+\t\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n+\t\t\taq->rq_mask.spb_aura_pass = ~aq->rq_mask.spb_aura_pass;\n+\t\t\taq->rq_mask.lpb_aura_pass = ~aq->rq_mask.lpb_aura_pass;\n+\n+\t\t\taq->rq_mask.spb_aura_drop = ~aq->rq_mask.spb_aura_drop;\n+\t\t\taq->rq_mask.lpb_aura_drop = ~aq->rq_mask.lpb_aura_drop;\n+\t\t}\n \t}\n \n \treturn 0;\n@@ -244,6 +261,23 @@ rq_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \taq->rq.qint_idx = rq->qid % nix->qints;\n \taq->rq.xqe_drop_ena = 1;\n \n+\t/* If RED enabled, then fill enable for all cases */\n+\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n+\t\taq->rq.spb_pool_pass = rq->red_pass;\n+\t\taq->rq.spb_aura_pass = rq->red_pass;\n+\t\taq->rq.lpb_pool_pass = rq->red_pass;\n+\t\taq->rq.lpb_aura_pass = rq->red_pass;\n+\t\taq->rq.wqe_pool_pass = rq->red_pass;\n+\t\taq->rq.xqe_pass = rq->red_pass;\n+\n+\t\taq->rq.spb_pool_drop = rq->red_drop;\n+\t\taq->rq.spb_aura_drop = rq->red_drop;\n+\t\taq->rq.lpb_pool_drop = rq->red_drop;\n+\t\taq->rq.lpb_aura_drop = rq->red_drop;\n+\t\taq->rq.wqe_pool_drop = rq->red_drop;\n+\t\taq->rq.xqe_drop = rq->red_drop;\n+\t}\n+\n \tif (cfg) {\n \t\tif (rq->sso_ena) {\n \t\t\t/* SSO mode */\n@@ -296,6 +330,22 @@ rq_cfg(struct nix *nix, struct roc_nix_rq *rq, bool cfg, bool ena)\n \t\taq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;\n \t\taq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;\n \t\taq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;\n+\n+\t\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n+\t\t\taq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;\n+\t\t\taq->rq_mask.spb_aura_pass = ~aq->rq_mask.spb_aura_pass;\n+\t\t\taq->rq_mask.lpb_pool_pass = ~aq->rq_mask.lpb_pool_pass;\n+\t\t\taq->rq_mask.lpb_aura_pass = ~aq->rq_mask.lpb_aura_pass;\n+\t\t\taq->rq_mask.wqe_pool_pass = ~aq->rq_mask.wqe_pool_pass;\n+\t\t\taq->rq_mask.xqe_pass = ~aq->rq_mask.xqe_pass;\n+\n+\t\t\taq->rq_mask.spb_pool_drop = ~aq->rq_mask.spb_pool_drop;\n+\t\t\taq->rq_mask.spb_aura_drop = ~aq->rq_mask.spb_aura_drop;\n+\t\t\taq->rq_mask.lpb_pool_drop = ~aq->rq_mask.lpb_pool_drop;\n+\t\t\taq->rq_mask.lpb_aura_drop = ~aq->rq_mask.lpb_aura_drop;\n+\t\t\taq->rq_mask.wqe_pool_drop = ~aq->rq_mask.wqe_pool_drop;\n+\t\t\taq->rq_mask.xqe_drop = ~aq->rq_mask.xqe_drop;\n+\t\t}\n \t}\n \n \treturn 0;\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 5ba6e81..d064d12 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -278,13 +278,15 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \t/* Update aura fields */\n \taura->pool_addr = pool_id; /* AF will translate to associated poolctx */\n \taura->ena = 1;\n-\taura->shift = __builtin_clz(block_count) - 8;\n+\taura->shift = plt_log2_u32(block_count);\n+\taura->shift = aura->shift < 8 ? 0 : aura->shift - 8;\n \taura->limit = block_count;\n \taura->pool_caching = 1;\n \taura->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER);\n \taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);\n \taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);\n \taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);\n+\taura->avg_con = ROC_NPA_AVG_CONT;\n \t/* Many to one reduction */\n \taura->err_qint_idx = aura_id % lf->qints;\n \n@@ -293,13 +295,15 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \tpool->ena = 1;\n \tpool->buf_size = block_size / ROC_ALIGN;\n \tpool->stack_max_pages = stack_size;\n-\tpool->shift = __builtin_clz(block_count) - 8;\n+\tpool->shift = plt_log2_u32(block_count);\n+\tpool->shift = pool->shift < 8 ? 0 : pool->shift - 8;\n \tpool->ptr_start = 0;\n \tpool->ptr_end = ~0;\n \tpool->stack_caching = 1;\n \tpool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);\n \tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);\n \tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);\n+\tpool->avg_con = ROC_NPA_AVG_CONT;\n \n \t/* Many to one reduction */\n \tpool->err_qint_idx = pool_id % lf->qints;\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex 59d6223..3fc6192 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -12,6 +12,11 @@\n #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512\n #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15\n \n+/* This value controls how much of the present average resource level is used to\n+ * calculate the new resource level.\n+ */\n+#define ROC_NPA_AVG_CONT 0xE0\n+\n /* 16 CASP instructions can be outstanding in CN9k, but we use only 15\n * outstanding CASPs as we run out of registers.\n */\n", "prefixes": [ "v4", "06/62" ] }