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GET /api/patches/94668/?format=api
{ "id": 94668, "url": "https://patches.dpdk.org/api/patches/94668/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210622093715.10583-1-shaikh@niometrics.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210622093715.10583-1-shaikh@niometrics.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210622093715.10583-1-shaikh@niometrics.com", "date": "2021-06-22T09:37:15", "name": "[1/1] net/i40e: fix compilation failure on core-avx-i", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": true, "hash": "318669abeba08ea293799c800cb0080472415fc6", "submitter": { "id": 2264, "url": "https://patches.dpdk.org/api/people/2264/?format=api", "name": "Shahed Shaikh", "email": "shaikh@niometrics.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210622093715.10583-1-shaikh@niometrics.com/mbox/", "series": [ { "id": 17433, "url": "https://patches.dpdk.org/api/series/17433/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17433", "date": "2021-06-22T09:37:15", "name": "[1/1] net/i40e: fix compilation failure on core-avx-i", "version": 1, "mbox": "https://patches.dpdk.org/series/17433/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94668/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/94668/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 13C8EA0C41;\n\tTue, 22 Jun 2021 11:37:58 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8C44D4003F;\n\tTue, 22 Jun 2021 11:37:57 +0200 (CEST)", "from integrity.niometrics.com (integrity.niometrics.com\n [42.61.70.122]) by mails.dpdk.org (Postfix) with ESMTP id 6DED74003C;\n Tue, 22 Jun 2021 11:37:56 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n by integrity.niometrics.com (Postfix) with ESMTP id B4DB5409CBAC;\n Tue, 22 Jun 2021 17:37:53 +0800 (+08)", "from integrity.niometrics.com ([127.0.0.1])\n by localhost (integrity.niometrics.com [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id t2Fd3jCOijkN; Tue, 22 Jun 2021 17:37:53 +0800 (+08)", "from localhost.localdomain (unknown [202.133.202.138])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by integrity.niometrics.com (Postfix) with ESMTPSA id DB39E409CBA9;\n Tue, 22 Jun 2021 17:37:51 +0800 (+08)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 integrity.niometrics.com B4DB5409CBAC", "OpenDKIM Filter v2.11.0 integrity.niometrics.com DB39E409CBA9" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=niometrics.com;\n s=default; t=1624354675;\n bh=vLyswiHlLh7x0rCnlGCb2oUwxD9cl8ZAyC3NLvVtOk0=;\n h=From:To:Cc:Subject:Date:From;\n b=peKeYlC6S4Tf8Pq2ZitGxYoFmN8SrZw9K8ZZxOTBZ2ZSY4wvdoED1VaqYnukA4CS4\n zX+JSreEufcyrWvtZhN8Hj1x+l0V1MqOO81mo+RLY3qFCzYCem7f5V4+Qca1j1xbi4\n 1FrQ3EIJ3jZ/YHae/bNvdqseV7OuEsW/o0ejZj6c=", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=niometrics.com;\n s=default; t=1624354673;\n bh=vLyswiHlLh7x0rCnlGCb2oUwxD9cl8ZAyC3NLvVtOk0=;\n h=From:To:Cc:Subject:Date:From;\n b=U1CXtWU72ZO7mGpXO3w7CG05CSgQYn2Oaa52ChWZ8D5bgQkNd0vg2+IE3mlNCCHx2\n JzL8d9luMem9SWjwkIXK8v3d5hFdfd/vmVIYyvFtorJPzOXtYLcPvs32Q/w41eBaPP\n TtLNUCwebrAysGoJq054DRUV1zYVC9kS8sFBbg/o=" ], "X-Virus-Scanned": "amavisd-new at niometrics.com", "DMARC-Filter": "OpenDMARC Filter v1.3.2 integrity.niometrics.com DB39E409CBA9", "From": "Shahed Shaikh <shaikh@niometrics.com>", "To": "beilei.xing@intel.com", "Cc": "dev@dpdk.org,\n\tShahed Shaikh <shaikh@niometrics.com>,\n\tstable@dpdk.org", "Date": "Tue, 22 Jun 2021 17:37:15 +0800", "Message-Id": "<20210622093715.10583-1-shaikh@niometrics.com>", "X-Mailer": "git-send-email 2.29.2", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Spam-Status": "No, score=-1.1 required=3.5 tests=ALL_TRUSTED, AWL,\n DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU autolearn=disabled version=3.4.0", "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n integrity.niometrics.com", "Subject": "[dpdk-dev] [PATCH 1/1] net/i40e: fix compilation failure on\n core-avx-i", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "i40e_rxtx_vec_sse.c fails to compile with below configuration:\n- #define RTE_LIBRTE_I40E_16BYTE_RX_DESC 1 in config/rte_config.h\n- cpu=core-axv-i\n- gcc which supports -mavx2 (e.g. gcc 4.8.5)\n\nThis is because commit 0604b1f2208f (\"net/i40e: fix crash in AVX512\")\nadded i40e_rxq_rearm_common() to i40e_rxtx_vec_common.h which is\nincluded by i40e_rxtx_vec_sse.c.\n\nThis function is enabled for compilation if CC_AVX2_SUPPORT is defined.\nAs per drivers/net/i40e/meson.build, CC_AVX2_SUPPORT is defined when\neither CPU supports __AVX2__ or compiler supports -mavx2 option.\n\nSo for given configuration, CC_AVX2_SUPPORT gets defined but we\ndon't pass -mavx2 explicitly to gcc while compiling i40e_rxtx_vec_sse.c.\nHence it fails due to avx2 specific code from i40e_rxq_rearm_command().\n\nThis patch tries to fix the compilation by moving\ni40e_rxq_rearm_common() to a new header file which will only be\nincluded by i40e_rxtx_vec_avx2.c and i40e_rxtx_vec_avx512.c.\n\nFixes: 0604b1f2208f (\"net/i40e: fix crash in AVX512\")\nCc: stable@dpdk.org\n\nSigned-off-by: Shahed Shaikh <shaikh@niometrics.com>\n---\n drivers/net/i40e/i40e_rxtx_vec_avx2.c | 2 +-\n drivers/net/i40e/i40e_rxtx_vec_avx512.c | 2 +-\n drivers/net/i40e/i40e_rxtx_vec_avx_common.h | 210 ++++++++++++++++++++\n drivers/net/i40e/i40e_rxtx_vec_common.h | 201 -------------------\n 4 files changed, 212 insertions(+), 203 deletions(-)\n create mode 100644 drivers/net/i40e/i40e_rxtx_vec_avx_common.h\n\n--\n2.29.2", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx2.c b/drivers/net/i40e/i40e_rxtx_vec_avx2.c\nindex 3b9eef91a9..2afbb71b75 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_avx2.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx2.c\n@@ -10,7 +10,7 @@\n #include \"base/i40e_type.h\"\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n-#include \"i40e_rxtx_vec_common.h\"\n+#include \"i40e_rxtx_vec_avx_common.h\"\n\n #include <rte_vect.h>\n\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_avx512.c b/drivers/net/i40e/i40e_rxtx_vec_avx512.c\nindex bd21d64223..ad225b0e54 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_avx512.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx512.c\n@@ -10,7 +10,7 @@\n #include \"base/i40e_type.h\"\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n-#include \"i40e_rxtx_vec_common.h\"\n+#include \"i40e_rxtx_vec_avx_common.h\"\n\n #include <rte_vect.h>\n\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_avx_common.h b/drivers/net/i40e/i40e_rxtx_vec_avx_common.h\nnew file mode 100644\nindex 0000000000..9f34e52efb\n--- /dev/null\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx_common.h\n@@ -0,0 +1,210 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef _I40E_RXTX_VEC_AVX_COMMON_H_\n+#define _I40E_RXTX_VEC_AVX_COMMON_H_\n+\n+#include \"i40e_rxtx_vec_common.h\"\n+\n+#ifndef __INTEL_COMPILER\n+#pragma GCC diagnostic ignored \"-Wcast-qual\"\n+#endif\n+\n+#ifdef CC_AVX2_SUPPORT\n+static __rte_always_inline void\n+i40e_rxq_rearm_common(struct i40e_rx_queue *rxq, __rte_unused bool avx512)\n+{\n+\tint i;\n+\tuint16_t rx_id;\n+\tvolatile union i40e_rx_desc *rxdp;\n+\tstruct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];\n+\n+\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n+\n+\t/* Pull 'n' more MBUFs into the software ring */\n+\tif (rte_mempool_get_bulk(rxq->mp,\n+\t\t\t\t (void *)rxep,\n+\t\t\t\t RTE_I40E_RXQ_REARM_THRESH) < 0) {\n+\t\tif (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=\n+\t\t rxq->nb_rx_desc) {\n+\t\t\t__m128i dma_addr0;\n+\t\t\tdma_addr0 = _mm_setzero_si128();\n+\t\t\tfor (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {\n+\t\t\t\trxep[i].mbuf = &rxq->fake_mbuf;\n+\t\t\t\t_mm_store_si128((__m128i *)&rxdp[i].read,\n+\t\t\t\t\t\tdma_addr0);\n+\t\t\t}\n+\t\t}\n+\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n+\t\t\tRTE_I40E_RXQ_REARM_THRESH;\n+\t\treturn;\n+\t}\n+\n+#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n+\tstruct rte_mbuf *mb0, *mb1;\n+\t__m128i dma_addr0, dma_addr1;\n+\t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\n+\t\t\tRTE_PKTMBUF_HEADROOM);\n+\t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\n+\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {\n+\t\t__m128i vaddr0, vaddr1;\n+\n+\t\tmb0 = rxep[0].mbuf;\n+\t\tmb1 = rxep[1].mbuf;\n+\n+\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n+\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n+\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n+\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n+\n+\t\t/* convert pa to dma_addr hdr/data */\n+\t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\n+\t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\n+\n+\t\t/* add headroom to pa values */\n+\t\tdma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\n+\t\tdma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\n+\n+\t\t/* flush desc with pa dma_addr */\n+\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\n+\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\n+\t}\n+#else\n+#ifdef CC_AVX512_SUPPORT\n+\tif (avx512) {\n+\t\tstruct rte_mbuf *mb0, *mb1, *mb2, *mb3;\n+\t\tstruct rte_mbuf *mb4, *mb5, *mb6, *mb7;\n+\t\t__m512i dma_addr0_3, dma_addr4_7;\n+\t\t__m512i hdr_room = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);\n+\t\t/* Initialize the mbufs in vector, process 8 mbufs in one loop */\n+\t\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;\n+\t\t\t\ti += 8, rxep += 8, rxdp += 8) {\n+\t\t\t__m128i vaddr0, vaddr1, vaddr2, vaddr3;\n+\t\t\t__m128i vaddr4, vaddr5, vaddr6, vaddr7;\n+\t\t\t__m256i vaddr0_1, vaddr2_3;\n+\t\t\t__m256i vaddr4_5, vaddr6_7;\n+\t\t\t__m512i vaddr0_3, vaddr4_7;\n+\n+\t\t\tmb0 = rxep[0].mbuf;\n+\t\t\tmb1 = rxep[1].mbuf;\n+\t\t\tmb2 = rxep[2].mbuf;\n+\t\t\tmb3 = rxep[3].mbuf;\n+\t\t\tmb4 = rxep[4].mbuf;\n+\t\t\tmb5 = rxep[5].mbuf;\n+\t\t\tmb6 = rxep[6].mbuf;\n+\t\t\tmb7 = rxep[7].mbuf;\n+\n+\t\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n+\t\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n+\t\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n+\t\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n+\t\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n+\t\t\tvaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);\n+\t\t\tvaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);\n+\t\t\tvaddr4 = _mm_loadu_si128((__m128i *)&mb4->buf_addr);\n+\t\t\tvaddr5 = _mm_loadu_si128((__m128i *)&mb5->buf_addr);\n+\t\t\tvaddr6 = _mm_loadu_si128((__m128i *)&mb6->buf_addr);\n+\t\t\tvaddr7 = _mm_loadu_si128((__m128i *)&mb7->buf_addr);\n+\n+\t\t\t/**\n+\t\t\t * merge 0 & 1, by casting 0 to 256-bit and inserting 1\n+\t\t\t * into the high lanes. Similarly for 2 & 3, and so on.\n+\t\t\t */\n+\t\t\tvaddr0_1 =\n+\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),\n+\t\t\t\t\t\t\tvaddr1, 1);\n+\t\t\tvaddr2_3 =\n+\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),\n+\t\t\t\t\t\t\tvaddr3, 1);\n+\t\t\tvaddr4_5 =\n+\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr4),\n+\t\t\t\t\t\t\tvaddr5, 1);\n+\t\t\tvaddr6_7 =\n+\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr6),\n+\t\t\t\t\t\t\tvaddr7, 1);\n+\t\t\tvaddr0_3 =\n+\t\t\t\t_mm512_inserti64x4(_mm512_castsi256_si512(vaddr0_1),\n+\t\t\t\t\t\t\tvaddr2_3, 1);\n+\t\t\tvaddr4_7 =\n+\t\t\t\t_mm512_inserti64x4(_mm512_castsi256_si512(vaddr4_5),\n+\t\t\t\t\t\t\tvaddr6_7, 1);\n+\n+\t\t\t/* convert pa to dma_addr hdr/data */\n+\t\t\tdma_addr0_3 = _mm512_unpackhi_epi64(vaddr0_3, vaddr0_3);\n+\t\t\tdma_addr4_7 = _mm512_unpackhi_epi64(vaddr4_7, vaddr4_7);\n+\n+\t\t\t/* add headroom to pa values */\n+\t\t\tdma_addr0_3 = _mm512_add_epi64(dma_addr0_3, hdr_room);\n+\t\t\tdma_addr4_7 = _mm512_add_epi64(dma_addr4_7, hdr_room);\n+\n+\t\t\t/* flush desc with pa dma_addr */\n+\t\t\t_mm512_store_si512((__m512i *)&rxdp->read, dma_addr0_3);\n+\t\t\t_mm512_store_si512((__m512i *)&(rxdp + 4)->read, dma_addr4_7);\n+\t\t}\n+\t} else\n+#endif\n+\t{\n+\t\tstruct rte_mbuf *mb0, *mb1, *mb2, *mb3;\n+\t\t__m256i dma_addr0_1, dma_addr2_3;\n+\t\t__m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);\n+\t\t/* Initialize the mbufs in vector, process 4 mbufs in one loop */\n+\t\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;\n+\t\t\t\ti += 4, rxep += 4, rxdp += 4) {\n+\t\t\t__m128i vaddr0, vaddr1, vaddr2, vaddr3;\n+\t\t\t__m256i vaddr0_1, vaddr2_3;\n+\n+\t\t\tmb0 = rxep[0].mbuf;\n+\t\t\tmb1 = rxep[1].mbuf;\n+\t\t\tmb2 = rxep[2].mbuf;\n+\t\t\tmb3 = rxep[3].mbuf;\n+\n+\t\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n+\t\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n+\t\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n+\t\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n+\t\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n+\t\t\tvaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);\n+\t\t\tvaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);\n+\n+\t\t\t/*\n+\t\t\t * merge 0 & 1, by casting 0 to 256-bit and inserting 1\n+\t\t\t * into the high lanes. Similarly for 2 & 3\n+\t\t\t */\n+\t\t\tvaddr0_1 = _mm256_inserti128_si256(\n+\t\t\t\t\t_mm256_castsi128_si256(vaddr0), vaddr1, 1);\n+\t\t\tvaddr2_3 = _mm256_inserti128_si256(\n+\t\t\t\t\t_mm256_castsi128_si256(vaddr2), vaddr3, 1);\n+\n+\t\t\t/* convert pa to dma_addr hdr/data */\n+\t\t\tdma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);\n+\t\t\tdma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);\n+\n+\t\t\t/* add headroom to pa values */\n+\t\t\tdma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);\n+\t\t\tdma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);\n+\n+\t\t\t/* flush desc with pa dma_addr */\n+\t\t\t_mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);\n+\t\t\t_mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);\n+\t\t}\n+\t}\n+\n+#endif\n+\n+\trxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;\n+\tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n+\t\trxq->rxrearm_start = 0;\n+\n+\trxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;\n+\n+\trx_id = (uint16_t)((rxq->rxrearm_start == 0) ?\n+\t\t\t (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n+\n+\t/* Update the tail pointer on the NIC */\n+\tI40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);\n+}\n+#endif\n+\n+#endif\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_common.h b/drivers/net/i40e/i40e_rxtx_vec_common.h\nindex 16fcf0aec6..33cebbe88b 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_common.h\n+++ b/drivers/net/i40e/i40e_rxtx_vec_common.h\n@@ -11,10 +11,6 @@\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n\n-#ifndef __INTEL_COMPILER\n-#pragma GCC diagnostic ignored \"-Wcast-qual\"\n-#endif\n-\n static inline uint16_t\n reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,\n \t\t uint16_t nb_bufs, uint8_t *split_flags)\n@@ -256,201 +252,4 @@ i40e_rx_vec_dev_conf_condition_check_default(struct rte_eth_dev *dev)\n \treturn -1;\n #endif\n }\n-\n-#ifdef CC_AVX2_SUPPORT\n-static __rte_always_inline void\n-i40e_rxq_rearm_common(struct i40e_rx_queue *rxq, __rte_unused bool avx512)\n-{\n-\tint i;\n-\tuint16_t rx_id;\n-\tvolatile union i40e_rx_desc *rxdp;\n-\tstruct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];\n-\n-\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n-\n-\t/* Pull 'n' more MBUFs into the software ring */\n-\tif (rte_mempool_get_bulk(rxq->mp,\n-\t\t\t\t (void *)rxep,\n-\t\t\t\t RTE_I40E_RXQ_REARM_THRESH) < 0) {\n-\t\tif (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=\n-\t\t rxq->nb_rx_desc) {\n-\t\t\t__m128i dma_addr0;\n-\t\t\tdma_addr0 = _mm_setzero_si128();\n-\t\t\tfor (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {\n-\t\t\t\trxep[i].mbuf = &rxq->fake_mbuf;\n-\t\t\t\t_mm_store_si128((__m128i *)&rxdp[i].read,\n-\t\t\t\t\t\tdma_addr0);\n-\t\t\t}\n-\t\t}\n-\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n-\t\t\tRTE_I40E_RXQ_REARM_THRESH;\n-\t\treturn;\n-\t}\n-\n-#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n-\tstruct rte_mbuf *mb0, *mb1;\n-\t__m128i dma_addr0, dma_addr1;\n-\t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\n-\t\t\tRTE_PKTMBUF_HEADROOM);\n-\t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\n-\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {\n-\t\t__m128i vaddr0, vaddr1;\n-\n-\t\tmb0 = rxep[0].mbuf;\n-\t\tmb1 = rxep[1].mbuf;\n-\n-\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n-\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n-\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n-\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n-\n-\t\t/* convert pa to dma_addr hdr/data */\n-\t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\n-\t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\n-\n-\t\t/* add headroom to pa values */\n-\t\tdma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\n-\t\tdma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\n-\n-\t\t/* flush desc with pa dma_addr */\n-\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\n-\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\n-\t}\n-#else\n-#ifdef CC_AVX512_SUPPORT\n-\tif (avx512) {\n-\t\tstruct rte_mbuf *mb0, *mb1, *mb2, *mb3;\n-\t\tstruct rte_mbuf *mb4, *mb5, *mb6, *mb7;\n-\t\t__m512i dma_addr0_3, dma_addr4_7;\n-\t\t__m512i hdr_room = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);\n-\t\t/* Initialize the mbufs in vector, process 8 mbufs in one loop */\n-\t\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;\n-\t\t\t\ti += 8, rxep += 8, rxdp += 8) {\n-\t\t\t__m128i vaddr0, vaddr1, vaddr2, vaddr3;\n-\t\t\t__m128i vaddr4, vaddr5, vaddr6, vaddr7;\n-\t\t\t__m256i vaddr0_1, vaddr2_3;\n-\t\t\t__m256i vaddr4_5, vaddr6_7;\n-\t\t\t__m512i vaddr0_3, vaddr4_7;\n-\n-\t\t\tmb0 = rxep[0].mbuf;\n-\t\t\tmb1 = rxep[1].mbuf;\n-\t\t\tmb2 = rxep[2].mbuf;\n-\t\t\tmb3 = rxep[3].mbuf;\n-\t\t\tmb4 = rxep[4].mbuf;\n-\t\t\tmb5 = rxep[5].mbuf;\n-\t\t\tmb6 = rxep[6].mbuf;\n-\t\t\tmb7 = rxep[7].mbuf;\n-\n-\t\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n-\t\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n-\t\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n-\t\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n-\t\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n-\t\t\tvaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);\n-\t\t\tvaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);\n-\t\t\tvaddr4 = _mm_loadu_si128((__m128i *)&mb4->buf_addr);\n-\t\t\tvaddr5 = _mm_loadu_si128((__m128i *)&mb5->buf_addr);\n-\t\t\tvaddr6 = _mm_loadu_si128((__m128i *)&mb6->buf_addr);\n-\t\t\tvaddr7 = _mm_loadu_si128((__m128i *)&mb7->buf_addr);\n-\n-\t\t\t/**\n-\t\t\t * merge 0 & 1, by casting 0 to 256-bit and inserting 1\n-\t\t\t * into the high lanes. Similarly for 2 & 3, and so on.\n-\t\t\t */\n-\t\t\tvaddr0_1 =\n-\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),\n-\t\t\t\t\t\t\tvaddr1, 1);\n-\t\t\tvaddr2_3 =\n-\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),\n-\t\t\t\t\t\t\tvaddr3, 1);\n-\t\t\tvaddr4_5 =\n-\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr4),\n-\t\t\t\t\t\t\tvaddr5, 1);\n-\t\t\tvaddr6_7 =\n-\t\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr6),\n-\t\t\t\t\t\t\tvaddr7, 1);\n-\t\t\tvaddr0_3 =\n-\t\t\t\t_mm512_inserti64x4(_mm512_castsi256_si512(vaddr0_1),\n-\t\t\t\t\t\t\tvaddr2_3, 1);\n-\t\t\tvaddr4_7 =\n-\t\t\t\t_mm512_inserti64x4(_mm512_castsi256_si512(vaddr4_5),\n-\t\t\t\t\t\t\tvaddr6_7, 1);\n-\n-\t\t\t/* convert pa to dma_addr hdr/data */\n-\t\t\tdma_addr0_3 = _mm512_unpackhi_epi64(vaddr0_3, vaddr0_3);\n-\t\t\tdma_addr4_7 = _mm512_unpackhi_epi64(vaddr4_7, vaddr4_7);\n-\n-\t\t\t/* add headroom to pa values */\n-\t\t\tdma_addr0_3 = _mm512_add_epi64(dma_addr0_3, hdr_room);\n-\t\t\tdma_addr4_7 = _mm512_add_epi64(dma_addr4_7, hdr_room);\n-\n-\t\t\t/* flush desc with pa dma_addr */\n-\t\t\t_mm512_store_si512((__m512i *)&rxdp->read, dma_addr0_3);\n-\t\t\t_mm512_store_si512((__m512i *)&(rxdp + 4)->read, dma_addr4_7);\n-\t\t}\n-\t} else\n-#endif\n-\t{\n-\t\tstruct rte_mbuf *mb0, *mb1, *mb2, *mb3;\n-\t\t__m256i dma_addr0_1, dma_addr2_3;\n-\t\t__m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);\n-\t\t/* Initialize the mbufs in vector, process 4 mbufs in one loop */\n-\t\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;\n-\t\t\t\ti += 4, rxep += 4, rxdp += 4) {\n-\t\t\t__m128i vaddr0, vaddr1, vaddr2, vaddr3;\n-\t\t\t__m256i vaddr0_1, vaddr2_3;\n-\n-\t\t\tmb0 = rxep[0].mbuf;\n-\t\t\tmb1 = rxep[1].mbuf;\n-\t\t\tmb2 = rxep[2].mbuf;\n-\t\t\tmb3 = rxep[3].mbuf;\n-\n-\t\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n-\t\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n-\t\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n-\t\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n-\t\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n-\t\t\tvaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);\n-\t\t\tvaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);\n-\n-\t\t\t/*\n-\t\t\t * merge 0 & 1, by casting 0 to 256-bit and inserting 1\n-\t\t\t * into the high lanes. Similarly for 2 & 3\n-\t\t\t */\n-\t\t\tvaddr0_1 = _mm256_inserti128_si256(\n-\t\t\t\t\t_mm256_castsi128_si256(vaddr0), vaddr1, 1);\n-\t\t\tvaddr2_3 = _mm256_inserti128_si256(\n-\t\t\t\t\t_mm256_castsi128_si256(vaddr2), vaddr3, 1);\n-\n-\t\t\t/* convert pa to dma_addr hdr/data */\n-\t\t\tdma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);\n-\t\t\tdma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);\n-\n-\t\t\t/* add headroom to pa values */\n-\t\t\tdma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);\n-\t\t\tdma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);\n-\n-\t\t\t/* flush desc with pa dma_addr */\n-\t\t\t_mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);\n-\t\t\t_mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);\n-\t\t}\n-\t}\n-\n-#endif\n-\n-\trxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;\n-\tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n-\t\trxq->rxrearm_start = 0;\n-\n-\trxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;\n-\n-\trx_id = (uint16_t)((rxq->rxrearm_start == 0) ?\n-\t\t\t (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n-\n-\t/* Update the tail pointer on the NIC */\n-\tI40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);\n-}\n-#endif\n-\n #endif\n", "prefixes": [ "1/1" ] }