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GET /api/patches/94645/?format=api
{ "id": 94645, "url": "https://patches.dpdk.org/api/patches/94645/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-21-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-21-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-21-tduszynski@marvell.com", "date": "2021-06-21T15:04:37", "name": "[v3,20/32] common/cnxk: support for setting bphy irq handler", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "44ac3e8cc20a09592557e208d11156e4eb639489", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-21-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94645/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94645/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A0AFA0547;\n\tMon, 21 Jun 2021 17:07:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ED62A4121D;\n\tMon, 21 Jun 2021 17:06:00 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C5BD04122E\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:05:59 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LF5HTA008514; Mon, 21 Jun 2021 08:05:56 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xja2w-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:05:56 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:05:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:05:55 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id D6FCC3F705B;\n Mon, 21 Jun 2021 08:05:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=O/NM+Y87xIOdDweQacl/Fe9yK15ZVaBvfsedhCfhZQ0=;\n b=dpCbvB7uygmSIxhb2oc4ovBUkD3U5NO+prcuw47d2gRISn5CprmBR/tH/NkwL1tGWRLF\n FEhyAF85zDzTpD/PKpQekl4E+yAeWmKxTa0TVa5h9e2PivUjb3eoKBM8BfZze7hHgwZn\n qV9fhjz2M7O3VbjgPPvjCj/3oPnn2mPhlmif46a5BQPHnhd4LICau03PXsI7TXC/ZBZV\n oNEn8nB7kSW95e/QEDWKCQmKlpu1gosIdMvfnzUWCpPsYdEiZFjcNF6UjuCfe5P9tM8a\n 7D6fhkgfr84iHlhoW2YuGrY1aCXVsKCIV/JLAJq2wjaCj64G8Mp6ebzQ55OZjncovq6A lw==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, Neil Horman\n <nhorman@tuxdriver.com>", "CC": "<thomas@monjalon.net>, <dev@dpdk.org>, Tomasz Duszynski\n <tduszynski@marvell.com>, Jakub Palider <jpalider@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:37 +0200", "Message-ID": "<20210621150449.19070-21-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "nFyDPfQ2XIWOd5_pmyvG3A4GzX8nPc85", "X-Proofpoint-ORIG-GUID": "nFyDPfQ2XIWOd5_pmyvG3A4GzX8nPc85", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 20/32] common/cnxk: support for setting bphy\n irq handler", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for setting custom baseband phy irq handler.\n\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/roc_bphy_irq.c | 121 +++++++++++++++++++++++++++\n drivers/common/cnxk/roc_bphy_irq.h | 5 ++\n drivers/common/cnxk/roc_io.h | 9 ++\n drivers/common/cnxk/roc_io_generic.h | 5 ++\n drivers/common/cnxk/version.map | 2 +\n 5 files changed, 142 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c\nindex a90c055ff..f988abf51 100644\n--- a/drivers/common/cnxk/roc_bphy_irq.c\n+++ b/drivers/common/cnxk/roc_bphy_irq.c\n@@ -4,12 +4,22 @@\n #include <fcntl.h>\n #include <pthread.h>\n #include <sys/ioctl.h>\n+#include <sys/mman.h>\n #include <sys/queue.h>\n #include <unistd.h>\n \n #include \"roc_api.h\"\n #include \"roc_bphy_irq.h\"\n \n+#define roc_cpuset_t cpu_set_t\n+\n+struct roc_bphy_irq_usr_data {\n+\tuint64_t isr_base;\n+\tuint64_t sp;\n+\tuint64_t cpu;\n+\tuint64_t irq_num;\n+};\n+\n struct roc_bphy_irq_stack {\n \tSTAILQ_ENTRY(roc_bphy_irq_stack) entries;\n \tvoid *sp_buffer;\n@@ -21,6 +31,8 @@ struct roc_bphy_irq_stack {\n #define ROC_BPHY_CTR_DEV_PATH \"/dev/otx-bphy-ctr\"\n \n #define ROC_BPHY_IOC_MAGIC 0xF3\n+#define ROC_BPHY_IOC_SET_BPHY_HANDLER \\\n+\t_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)\n #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ\t_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)\n #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)\n \n@@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu)\n \treturn NULL;\n }\n \n+void\n+roc_bphy_intr_handler(unsigned int irq_num)\n+{\n+\tstruct roc_bphy_irq_chip *irq_chip;\n+\tconst struct plt_memzone *mz;\n+\n+\tmz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);\n+\tif (mz == NULL)\n+\t\treturn;\n+\n+\tirq_chip = *(struct roc_bphy_irq_chip **)mz->addr;\n+\tif (irq_chip == NULL)\n+\t\treturn;\n+\n+\tif (irq_chip->irq_vecs[irq_num].handler != NULL)\n+\t\tirq_chip->irq_vecs[irq_num].handler(\n+\t\t\t(int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);\n+\n+\troc_atf_ret();\n+}\n+\n+int\n+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,\n+\t\t\t void (*isr)(int irq_num, void *isr_data),\n+\t\t\t void *isr_data)\n+{\n+\troc_cpuset_t orig_cpuset, intr_cpuset;\n+\tstruct roc_bphy_irq_usr_data irq_usr;\n+\tconst struct plt_memzone *mz;\n+\tint i, retval, curr_cpu, rc;\n+\tchar *env;\n+\n+\tmz = plt_memzone_lookup(chip->mz_name);\n+\tif (mz == NULL) {\n+\t\t/* what we want is just a pointer to chip, not object itself */\n+\t\tmz = plt_memzone_reserve_cache_align(chip->mz_name,\n+\t\t\t\t\t\t sizeof(chip));\n+\t\tif (mz == NULL)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (chip->irq_vecs[irq_num].handler != NULL)\n+\t\treturn -EINVAL;\n+\n+\trc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),\n+\t\t\t\t &orig_cpuset);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to get affinity mask\");\n+\t\treturn rc;\n+\t}\n+\n+\tfor (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)\n+\t\tif (CPU_ISSET(i, &orig_cpuset))\n+\t\t\tcurr_cpu = i;\n+\tif (curr_cpu < 0)\n+\t\treturn -ENOENT;\n+\n+\tCPU_ZERO(&intr_cpuset);\n+\tCPU_SET(curr_cpu, &intr_cpuset);\n+\tretval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),\n+\t\t\t\t\t&intr_cpuset);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to set affinity mask\");\n+\t\treturn rc;\n+\t}\n+\n+\tirq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;\n+\tirq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);\n+\tirq_usr.cpu = curr_cpu;\n+\tif (irq_usr.sp == 0) {\n+\t\trc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),\n+\t\t\t\t\t &orig_cpuset);\n+\t\tif (rc < 0)\n+\t\t\tplt_err(\"Failed to restore affinity mask\");\n+\t\treturn rc;\n+\t}\n+\n+\t/* On simulator memory locking operation takes much time. We want\n+\t * to skip this when running in such an environment.\n+\t */\n+\tenv = getenv(\"BPHY_INTR_MLOCK_DISABLE\");\n+\tif (env == NULL) {\n+\t\trc = mlockall(MCL_CURRENT | MCL_FUTURE);\n+\t\tif (rc < 0)\n+\t\t\tplt_warn(\"Failed to lock memory into RAM\");\n+\t}\n+\n+\t*((struct roc_bphy_irq_chip **)(mz->addr)) = chip;\n+\tirq_usr.irq_num = irq_num;\n+\tchip->irq_vecs[irq_num].handler_cpu = curr_cpu;\n+\tchip->irq_vecs[irq_num].handler = isr;\n+\tchip->irq_vecs[irq_num].isr_data = isr_data;\n+\tretval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);\n+\tif (retval != 0) {\n+\t\troc_bphy_irq_stack_remove(curr_cpu);\n+\t\tchip->irq_vecs[irq_num].handler = NULL;\n+\t\tchip->irq_vecs[irq_num].handler_cpu = -1;\n+\t} else {\n+\t\tchip->n_handlers++;\n+\t}\n+\n+\trc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),\n+\t\t\t\t &orig_cpuset);\n+\tif (rc < 0)\n+\t\tplt_warn(\"Failed to restore affinity mask\");\n+\n+\treturn retval;\n+}\n+\n bool\n roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)\n {\ndiff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h\nindex 549a84a7d..7dd23f4ab 100644\n--- a/drivers/common/cnxk/roc_bphy_irq.h\n+++ b/drivers/common/cnxk/roc_bphy_irq.h\n@@ -25,6 +25,11 @@ __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);\n __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);\n __roc_api void roc_bphy_irq_stack_remove(int cpu);\n __roc_api void *roc_bphy_irq_stack_get(int cpu);\n+__roc_api void roc_bphy_intr_handler(unsigned int irq_num);\n+__roc_api int\n+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,\n+\t\t\t void (*handler)(int irq_num, void *isr_data),\n+\t\t\t void *isr_data);\n __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,\n \t\t\t\t int irq_num);\n \ndiff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h\nindex fb3d9c5e5..aee8c7f97 100644\n--- a/drivers/common/cnxk/roc_io.h\n+++ b/drivers/common/cnxk/roc_io.h\n@@ -184,4 +184,13 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)\n \t\tdst128[i] = src128[i];\n }\n \n+static __plt_always_inline void\n+roc_atf_ret(void)\n+{\n+\t/* This will allow wfi in EL0 to cause async exception to EL3\n+\t * which will optionally perform necessary actions.\n+\t */\n+\t__asm(\"wfi\");\n+}\n+\n #endif /* _ROC_IO_H_ */\ndiff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h\nindex c1689b6f8..28cb0963e 100644\n--- a/drivers/common/cnxk/roc_io_generic.h\n+++ b/drivers/common/cnxk/roc_io_generic.h\n@@ -119,4 +119,9 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)\n \tPLT_SET_USED(segdw);\n }\n \n+static __plt_always_inline void\n+roc_atf_ret(void)\n+{\n+}\n+\n #endif /* _ROC_IO_GENERIC_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 78601fe31..861a97cc0 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -24,7 +24,9 @@ INTERNAL {\n \troc_bphy_dev_init;\n \troc_bphy_intr_available;\n \troc_bphy_intr_fini;\n+\troc_bphy_intr_handler;\n \troc_bphy_intr_init;\n+\troc_bphy_irq_handler_set;\n \troc_bphy_irq_stack_get;\n \troc_bphy_irq_stack_remove;\n \troc_clk_freq_get;\n", "prefixes": [ "v3", "20/32" ] }