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GET /api/patches/94592/?format=api
{ "id": 94592, "url": "https://patches.dpdk.org/api/patches/94592/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621073506.96017-3-wojciechx.liguzinski@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621073506.96017-3-wojciechx.liguzinski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621073506.96017-3-wojciechx.liguzinski@intel.com", "date": "2021-06-21T07:35:05", "name": "[RFC,v3,2/3] example/qos_sched: add PIE support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a5553a035682ec777dfef88f9773c802ca49ba28", "submitter": { "id": 2195, "url": "https://patches.dpdk.org/api/people/2195/?format=api", "name": "Liguzinski, WojciechX", "email": "wojciechx.liguzinski@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621073506.96017-3-wojciechx.liguzinski@intel.com/mbox/", "series": [ { "id": 17417, "url": "https://patches.dpdk.org/api/series/17417/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17417", "date": "2021-06-21T07:35:03", "name": "Add PIE support for HQoS library", "version": 3, "mbox": "https://patches.dpdk.org/series/17417/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94592/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94592/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E1AC1A0547;\n\tMon, 21 Jun 2021 09:35:42 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A6B4341175;\n\tMon, 21 Jun 2021 09:35:39 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id DBE9341158\n for <dev@dpdk.org>; Mon, 21 Jun 2021 09:35:36 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jun 2021 00:35:28 -0700", "from silpixa00400629.ir.intel.com ([10.237.214.62])\n by fmsmga008.fm.intel.com with ESMTP; 21 Jun 2021 00:35:27 -0700" ], "IronPort-SDR": [ "\n UwliuNyvxQ1mYP2TfRHyPQut3sqHOqezfCMoU8t3sgP4K0bBozSh6X8ujzKUG9lFxf2YRskUJA\n 7gxY5JcNozog==", "\n MSEAMgEbQvQwrwupoYwT2GDS5zIr9ObAZq8mCIIiSXI5b+P3juYLx72ym5D4N7/wQybIs8ftBP\n lJ457KwPe/wA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10021\"; a=\"206614876\"", "E=Sophos;i=\"5.83,289,1616482800\"; d=\"scan'208\";a=\"206614876\"", "E=Sophos;i=\"5.83,289,1616482800\"; d=\"scan'208\";a=\"453794335\"" ], "X-ExtLoop1": "1", "From": "\"Liguzinski, WojciechX\" <wojciechx.liguzinski@intel.com>", "To": "dev@dpdk.org,\n\tjasvinder.singh@intel.com,\n\tcristian.dumitrescu@intel.com", "Cc": "savinay.dharmappa@intel.com,\n\tmegha.ajmera@intel.com", "Date": "Mon, 21 Jun 2021 08:35:05 +0100", "Message-Id": "<20210621073506.96017-3-wojciechx.liguzinski@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210621073506.96017-1-wojciechx.liguzinski@intel.com>", "References": "<20210615090200.56824-1-wojciechx.liguzinski@intel.com>\n <20210621073506.96017-1-wojciechx.liguzinski@intel.com>", "Subject": "[dpdk-dev] [RFC PATCH v3 2/3] example/qos_sched: add PIE support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "patch add support enable PIE or RED by\nparsing config file.\n\nSigned-off-by: Liguzinski, WojciechX <wojciechx.liguzinski@intel.com>\n---\n config/rte_config.h | 1 -\n examples/qos_sched/app_thread.c | 1 -\n examples/qos_sched/cfg_file.c | 82 ++++++++++---\n examples/qos_sched/init.c | 7 +-\n examples/qos_sched/profile.cfg | 196 +++++++++++++++++++++-----------\n 5 files changed, 200 insertions(+), 87 deletions(-)", "diff": "diff --git a/config/rte_config.h b/config/rte_config.h\nindex 590903c07d..48132f27df 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -89,7 +89,6 @@\n #define RTE_MAX_LCORE_FREQS 64\n \n /* rte_sched defines */\n-#undef RTE_SCHED_RED\n #undef RTE_SCHED_COLLECT_STATS\n #undef RTE_SCHED_SUBPORT_TC_OV\n #define RTE_SCHED_PORT_N_GRINDERS 8\ndiff --git a/examples/qos_sched/app_thread.c b/examples/qos_sched/app_thread.c\nindex dbc878b553..895c0d3592 100644\n--- a/examples/qos_sched/app_thread.c\n+++ b/examples/qos_sched/app_thread.c\n@@ -205,7 +205,6 @@ app_worker_thread(struct thread_conf **confs)\n \t\tif (likely(nb_pkt)) {\n \t\t\tint nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs,\n \t\t\t\t\tnb_pkt);\n-\n \t\t\tAPP_STATS_ADD(conf->stat.nb_drop, nb_pkt - nb_sent);\n \t\t\tAPP_STATS_ADD(conf->stat.nb_rx, nb_pkt);\n \t\t}\ndiff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c\nindex cd167bd8e6..657763ca90 100644\n--- a/examples/qos_sched/cfg_file.c\n+++ b/examples/qos_sched/cfg_file.c\n@@ -242,20 +242,20 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \tmemset(active_queues, 0, sizeof(active_queues));\n \tn_active_queues = 0;\n \n-#ifdef RTE_SCHED_RED\n-\tchar sec_name[CFG_NAME_LEN];\n-\tstruct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n+#ifdef RTE_SCHED_AQM\n+\tenum rte_sched_aqm_mode aqm_mode;\n \n-\tsnprintf(sec_name, sizeof(sec_name), \"red\");\n+\tstruct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n \n-\tif (rte_cfgfile_has_section(cfg, sec_name)) {\n+\tif (rte_cfgfile_has_section(cfg, \"red\")) {\n+\t\taqm_mode = RTE_SCHED_AQM_WRED;\n \n \t\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n \t\t\tchar str[32];\n \n \t\t\t/* Parse WRED min thresholds */\n \t\t\tsnprintf(str, sizeof(str), \"tc %d wred min\", i);\n-\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, str);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n \t\t\tif (entry) {\n \t\t\t\tchar *next;\n \t\t\t\t/* for each packet colour (green, yellow, red) */\n@@ -315,7 +315,42 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t}\n \t\t}\n \t}\n-#endif /* RTE_SCHED_RED */\n+\n+\tstruct rte_pie_params pie_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\n+\tif (rte_cfgfile_has_section(cfg, \"pie\")) {\n+\t\taqm_mode = RTE_SCHED_AQM_PIE;\n+\n+\t\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\t\tchar str[32];\n+\n+\t\t\t/* Parse Queue Delay Ref value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d qdelay ref\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tpie_params[i].qdelay_ref = (uint16_t) atoi(entry);\n+\n+\t\t\t/* Parse Max Burst value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d max burst\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tpie_params[i].max_burst = (uint16_t) atoi(entry);\n+\n+\t\t\t/* Parse Update Interval Value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d update interval\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tpie_params[i].dp_update_interval = (uint16_t) atoi(entry);\n+\n+\t\t\t/* Parse Tailq Threshold Value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d tailq th\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tpie_params[i].tailq_th = (uint16_t) atoi(entry);\n+\n+\t\t}\n+\t}\n+#endif /* RTE_SCHED_AQM */\n \n \tfor (i = 0; i < MAX_SCHED_SUBPORTS; i++) {\n \t\tchar sec_name[CFG_NAME_LEN];\n@@ -393,17 +428,30 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t\t}\n \t\t\t\t}\n \t\t\t}\n-#ifdef RTE_SCHED_RED\n+#ifdef RTE_SCHED_AQM\n+\t\t\tsubport_params[i].aqm = aqm_mode;\n+\n \t\t\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n-\t\t\t\tfor (k = 0; k < RTE_COLORS; k++) {\n-\t\t\t\t\tsubport_params[i].red_params[j][k].min_th =\n-\t\t\t\t\t\tred_params[j][k].min_th;\n-\t\t\t\t\tsubport_params[i].red_params[j][k].max_th =\n-\t\t\t\t\t\tred_params[j][k].max_th;\n-\t\t\t\t\tsubport_params[i].red_params[j][k].maxp_inv =\n-\t\t\t\t\t\tred_params[j][k].maxp_inv;\n-\t\t\t\t\tsubport_params[i].red_params[j][k].wq_log2 =\n-\t\t\t\t\t\tred_params[j][k].wq_log2;\n+\t\t\t\tif (subport_params[i].aqm == RTE_SCHED_AQM_WRED) {\n+\t\t\t\t\tfor (k = 0; k < RTE_COLORS; k++) {\n+\t\t\t\t\t\tsubport_params[i].wred_params[j][k].min_th =\n+\t\t\t\t\t\t\tred_params[j][k].min_th;\n+\t\t\t\t\t\tsubport_params[i].wred_params[j][k].max_th =\n+\t\t\t\t\t\t\tred_params[j][k].max_th;\n+\t\t\t\t\t\tsubport_params[i].wred_params[j][k].maxp_inv =\n+\t\t\t\t\t\t\tred_params[j][k].maxp_inv;\n+\t\t\t\t\t\tsubport_params[i].wred_params[j][k].wq_log2 =\n+\t\t\t\t\t\t\tred_params[j][k].wq_log2;\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n+\t\t\t\t\tsubport_params[i].pie_params[j].qdelay_ref =\n+\t\t\t\t\t\tpie_params[j].qdelay_ref;\n+\t\t\t\t\tsubport_params[i].pie_params[j].dp_update_interval =\n+\t\t\t\t\t\tpie_params[j].dp_update_interval;\n+\t\t\t\t\tsubport_params[i].pie_params[j].max_burst =\n+\t\t\t\t\t\tpie_params[j].max_burst;\n+\t\t\t\t\tsubport_params[i].pie_params[j].tailq_th =\n+\t\t\t\t\t\tpie_params[j].tailq_th;\n \t\t\t\t}\n \t\t\t}\n #endif\ndiff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c\nindex 1abe003fc6..96ba3b6616 100644\n--- a/examples/qos_sched/init.c\n+++ b/examples/qos_sched/init.c\n@@ -212,8 +212,9 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t\t.n_pipe_profiles = sizeof(pipe_profiles) /\n \t\t\tsizeof(struct rte_sched_pipe_params),\n \t\t.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,\n-#ifdef RTE_SCHED_RED\n-\t.red_params = {\n+#ifdef RTE_SCHED_AQM\n+\t.aqm = RTE_SCHED_AQM_WRED,\n+\t.wred_params = {\n \t\t/* Traffic Class 0 Colors Green / Yellow / Red */\n \t\t[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t\t[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n@@ -279,7 +280,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t\t[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t},\n-#endif /* RTE_SCHED_RED */\n+#endif /* RTE_SCHED_AQM */\n \t},\n };\n \ndiff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg\nindex 4486d2799e..d4b21c0170 100644\n--- a/examples/qos_sched/profile.cfg\n+++ b/examples/qos_sched/profile.cfg\n@@ -76,68 +76,134 @@ tc 12 oversubscription weight = 1\n tc 12 wrr weights = 1 1 1 1\n \n ; RED params per traffic class and color (Green / Yellow / Red)\n-[red]\n-tc 0 wred min = 48 40 32\n-tc 0 wred max = 64 64 64\n-tc 0 wred inv prob = 10 10 10\n-tc 0 wred weight = 9 9 9\n-\n-tc 1 wred min = 48 40 32\n-tc 1 wred max = 64 64 64\n-tc 1 wred inv prob = 10 10 10\n-tc 1 wred weight = 9 9 9\n-\n-tc 2 wred min = 48 40 32\n-tc 2 wred max = 64 64 64\n-tc 2 wred inv prob = 10 10 10\n-tc 2 wred weight = 9 9 9\n-\n-tc 3 wred min = 48 40 32\n-tc 3 wred max = 64 64 64\n-tc 3 wred inv prob = 10 10 10\n-tc 3 wred weight = 9 9 9\n-\n-tc 4 wred min = 48 40 32\n-tc 4 wred max = 64 64 64\n-tc 4 wred inv prob = 10 10 10\n-tc 4 wred weight = 9 9 9\n-\n-tc 5 wred min = 48 40 32\n-tc 5 wred max = 64 64 64\n-tc 5 wred inv prob = 10 10 10\n-tc 5 wred weight = 9 9 9\n-\n-tc 6 wred min = 48 40 32\n-tc 6 wred max = 64 64 64\n-tc 6 wred inv prob = 10 10 10\n-tc 6 wred weight = 9 9 9\n-\n-tc 7 wred min = 48 40 32\n-tc 7 wred max = 64 64 64\n-tc 7 wred inv prob = 10 10 10\n-tc 7 wred weight = 9 9 9\n-\n-tc 8 wred min = 48 40 32\n-tc 8 wred max = 64 64 64\n-tc 8 wred inv prob = 10 10 10\n-tc 8 wred weight = 9 9 9\n-\n-tc 9 wred min = 48 40 32\n-tc 9 wred max = 64 64 64\n-tc 9 wred inv prob = 10 10 10\n-tc 9 wred weight = 9 9 9\n-\n-tc 10 wred min = 48 40 32\n-tc 10 wred max = 64 64 64\n-tc 10 wred inv prob = 10 10 10\n-tc 10 wred weight = 9 9 9\n-\n-tc 11 wred min = 48 40 32\n-tc 11 wred max = 64 64 64\n-tc 11 wred inv prob = 10 10 10\n-tc 11 wred weight = 9 9 9\n-\n-tc 12 wred min = 48 40 32\n-tc 12 wred max = 64 64 64\n-tc 12 wred inv prob = 10 10 10\n-tc 12 wred weight = 9 9 9\n+;[red]\n+;tc 0 wred min = 48 40 32\n+;tc 0 wred max = 64 64 64\n+;tc 0 wred inv prob = 10 10 10\n+;tc 0 wred weight = 9 9 9\n+\n+;tc 1 wred min = 48 40 32\n+;tc 1 wred max = 64 64 64\n+;tc 1 wred inv prob = 10 10 10\n+;tc 1 wred weight = 9 9 9\n+\n+;tc 2 wred min = 48 40 32\n+;tc 2 wred max = 64 64 64\n+;tc 2 wred inv prob = 10 10 10\n+;tc 2 wred weight = 9 9 9\n+\n+;tc 3 wred min = 48 40 32\n+;tc 3 wred max = 64 64 64\n+;tc 3 wred inv prob = 10 10 10\n+;tc 3 wred weight = 9 9 9\n+\n+;tc 4 wred min = 48 40 32\n+;tc 4 wred max = 64 64 64\n+;tc 4 wred inv prob = 10 10 10\n+;tc 4 wred weight = 9 9 9\n+\n+;tc 5 wred min = 48 40 32\n+;tc 5 wred max = 64 64 64\n+;tc 5 wred inv prob = 10 10 10\n+;tc 5 wred weight = 9 9 9\n+\n+;tc 6 wred min = 48 40 32\n+;tc 6 wred max = 64 64 64\n+;tc 6 wred inv prob = 10 10 10\n+;tc 6 wred weight = 9 9 9\n+\n+;tc 7 wred min = 48 40 32\n+;tc 7 wred max = 64 64 64\n+;tc 7 wred inv prob = 10 10 10\n+;tc 7 wred weight = 9 9 9\n+\n+;tc 8 wred min = 48 40 32\n+;tc 8 wred max = 64 64 64\n+;tc 8 wred inv prob = 10 10 10\n+;tc 8 wred weight = 9 9 9\n+\n+;tc 9 wred min = 48 40 32\n+;tc 9 wred max = 64 64 64\n+;tc 9 wred inv prob = 10 10 10\n+;tc 9 wred weight = 9 9 9\n+\n+;tc 10 wred min = 48 40 32\n+;tc 10 wred max = 64 64 64\n+;tc 10 wred inv prob = 10 10 10\n+;tc 10 wred weight = 9 9 9\n+\n+;tc 11 wred min = 48 40 32\n+;tc 11 wred max = 64 64 64\n+;tc 11 wred inv prob = 10 10 10\n+;tc 11 wred weight = 9 9 9\n+\n+;tc 12 wred min = 48 40 32\n+;tc 12 wred max = 64 64 64\n+;tc 12 wred inv prob = 10 10 10\n+;tc 12 wred weight = 9 9 9\n+\n+[pie]\n+tc 0 qdelay ref = 15\n+tc 0 max burst = 150\n+tc 0 update interval = 15\n+tc 0 tailq th = 64\n+\n+tc 1 qdelay ref = 15\n+tc 1 max burst = 150\n+tc 1 update interval = 15\n+tc 1 tailq th = 64\n+\n+tc 2 qdelay ref = 15\n+tc 2 max burst = 150\n+tc 2 update interval = 15\n+tc 2 tailq th = 64\n+\n+tc 3 qdelay ref = 15\n+tc 3 max burst = 150\n+tc 3 update interval = 15\n+tc 3 tailq th = 64\n+\n+tc 4 qdelay ref = 15\n+tc 4 max burst = 150\n+tc 4 update interval = 15\n+tc 4 tailq th = 64\n+\n+tc 5 qdelay ref = 15\n+tc 5 max burst = 150\n+tc 5 update interval = 15\n+tc 5 tailq th = 64\n+\n+tc 6 qdelay ref = 15\n+tc 6 max burst = 150\n+tc 6 update interval = 15\n+tc 6 tailq th = 64\n+\n+tc 7 qdelay ref = 15\n+tc 7 max burst = 150\n+tc 7 update interval = 15\n+tc 7 tailq th = 64\n+\n+tc 8 qdelay ref = 15\n+tc 8 max burst = 150\n+tc 8 update interval = 15\n+tc 8 tailq th = 64\n+\n+tc 9 qdelay ref = 15\n+tc 9 max burst = 150\n+tc 9 update interval = 15\n+tc 9 tailq th = 64\n+\n+tc 10 qdelay ref = 15\n+tc 10 max burst = 150\n+tc 10 update interval = 15\n+tc 10 tailq th = 64\n+\n+tc 11 qdelay ref = 15\n+tc 11 max burst = 150\n+tc 11 update interval = 15\n+tc 11 tailq th = 64\n+\n+tc 12 qdelay ref = 15\n+tc 12 max burst = 150\n+tc 12 update interval = 15\n+tc 12 tailq th = 64\n", "prefixes": [ "RFC", "v3", "2/3" ] }