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GET /api/patches/94568/?format=api
{ "id": 94568, "url": "https://patches.dpdk.org/api/patches/94568/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-12-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210620202906.10974-12-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210620202906.10974-12-pbhagavatula@marvell.com", "date": "2021-06-20T20:29:05", "name": "[v3,12/13] event/cnxk: add Rx event vector fastpath", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4fbb79fe06b7325fe7f2c70a8097239ea83397da", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-12-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17410, "url": "https://patches.dpdk.org/api/series/17410/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17410", "date": "2021-06-20T20:28:54", "name": "[v3,01/13] net/cnxk: add multi seg Rx vector routine", "version": 3, "mbox": "https://patches.dpdk.org/series/17410/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94568/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94568/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A1A32A0547;\n\tSun, 20 Jun 2021 22:30:45 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8772C4117B;\n\tSun, 20 Jun 2021 22:29:57 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0EFAF407FF\n for <dev@dpdk.org>; Sun, 20 Jun 2021 22:29:54 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15KKQ4v0010109 for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:54 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 399dxrmgt1-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:54 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 20 Jun 2021 13:29:52 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 20 Jun 2021 13:29:52 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id C39523F7066;\n Sun, 20 Jun 2021 13:29:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=bVVfaQ4qidnMVGtT59nbIfauH55cqpgH2liucpBpzUw=;\n b=J4JNjT8t2QPh+gFKO1rN658dS3pUr8GBMNU5F7v1XXjChfmfJcFM4YjrojG04eFf9ZJq\n E61c2Jou0IcAdVAriBxI4SK3+3l2XQ4tVnafdBye9zJq9pJDqt8yo1lCYxrxN1fO94pK\n 5RYDzGId4EwkZOttXHKSXxQbN8AS2UKBjITIM22WvV75niQpGuoTDUpX+UQokubTFsAD\n 86j68BVnBkclsWY11XCe/8lP9t5thdjJZ8LgfsHgErn3H9p+vpOVmU/e8lE48BGPYot5\n d71OSmkkmDKWuYDXatV7JXLKEO1kz8I/WPpVklNn5knWgYWs6Rt1Dr33Li5OT7ntmgKR 7g==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 21 Jun 2021 01:59:05 +0530", "Message-ID": "<20210620202906.10974-12-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210620202906.10974-1-pbhagavatula@marvell.com>", "References": "<20210619110154.10301-1-pbhagavatula@marvell.com>\n <20210620202906.10974-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "4Ta4WWQiDaUH_1W3lW2sZ1LjVpklPamG", "X-Proofpoint-GUID": "4Ta4WWQiDaUH_1W3lW2sZ1LjVpklPamG", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-20_14:2021-06-20,\n 2021-06-20 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 12/13] event/cnxk: add Rx event vector fastpath", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd Rx event vector fastpath to convert HW defined metadata into\nrte_mbuf and rte_event_vector.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/rel_notes/release_21_08.rst | 1 +\n drivers/event/cnxk/cn10k_worker.h | 56 +++++++\n drivers/net/cnxk/cn10k_rx.h | 200 +++++++++++++++----------\n drivers/net/cnxk/cn10k_rx_vec.c | 2 +-\n drivers/net/cnxk/cn10k_rx_vec_mseg.c | 5 +-\n 5 files changed, 179 insertions(+), 85 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst\nindex 80ff93269c..11ccc9bcb5 100644\n--- a/doc/guides/rel_notes/release_21_08.rst\n+++ b/doc/guides/rel_notes/release_21_08.rst\n@@ -64,6 +64,7 @@ New Features\n \n * Added Rx/Tx adapter support for event/cnxk when the ethernet device requested\n is net/cnxk.\n+ * Add support for event vectorization for Rx adapter.\n \n \n Removed Items\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 3c90c85009..7a48a6b17d 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -5,6 +5,8 @@\n #ifndef __CN10K_WORKER_H__\n #define __CN10K_WORKER_H__\n \n+#include <rte_vect.h>\n+\n #include \"cnxk_ethdev.h\"\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n@@ -101,6 +103,49 @@ cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n \t\t\t mbuf_init | ((uint64_t)port_id) << 48, flags);\n }\n \n+static __rte_always_inline void\n+cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n+\t\t void *lookup_mem, void *tstamp)\n+{\n+\tuint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |\n+\t\t\t (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);\n+\tstruct rte_event_vector *vec;\n+\tuint16_t nb_mbufs, non_vec;\n+\tuint64_t **wqe;\n+\n+\tmbuf_init |= ((uint64_t)port_id) << 48;\n+\tvec = (struct rte_event_vector *)vwqe;\n+\twqe = vec->u64s;\n+\n+\tnb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);\n+\tnb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,\n+\t\t\t\t\t flags | NIX_RX_VWQE_F, lookup_mem,\n+\t\t\t\t\t tstamp);\n+\twqe += nb_mbufs;\n+\tnon_vec = vec->nb_elem - nb_mbufs;\n+\n+\twhile (non_vec) {\n+\t\tstruct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];\n+\t\tstruct rte_mbuf *mbuf;\n+\t\tuint64_t tstamp_ptr;\n+\n+\t\tmbuf = (struct rte_mbuf *)((char *)cqe -\n+\t\t\t\t\t sizeof(struct rte_mbuf));\n+\t\tcn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,\n+\t\t\t\t mbuf_init, flags);\n+\t\t/* Extracting tstamp, if PTP enabled*/\n+\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)cqe) +\n+\t\t\t\t\t CNXK_SSO_WQE_SG_PTR);\n+\t\tcnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,\n+\t\t\t\t\tflags & NIX_RX_OFFLOAD_TSTAMP_F,\n+\t\t\t\t\tflags & NIX_RX_MULTI_SEG_F,\n+\t\t\t\t\t(uint64_t *)tstamp_ptr);\n+\t\twqe[0] = (uint64_t *)mbuf;\n+\t\tnon_vec--;\n+\t\twqe++;\n+\t}\n+}\n+\n static __rte_always_inline uint16_t\n cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t const uint32_t flags, void *lookup_mem)\n@@ -152,6 +197,17 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t\t\t\t\tflags & NIX_RX_MULTI_SEG_F,\n \t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n \t\t\tgw.u64[1] = mbuf;\n+\t\t} else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t\t RTE_EVENT_TYPE_ETHDEV_VECTOR) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\t\t\t__uint128_t vwqe_hdr = *(__uint128_t *)gw.u64[1];\n+\n+\t\t\tvwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) |\n+\t\t\t\t ((vwqe_hdr & 0xFFFF) << 48) |\n+\t\t\t\t ((uint64_t)port << 32);\n+\t\t\t*(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;\n+\t\t\tcn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,\n+\t\t\t\t\t ws->tstamp);\n \t\t}\n \t}\n \ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex d9572b19e7..a506a867ca 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -21,6 +21,7 @@\n * Defining it from backwards to denote its been\n * not used as offload flags to pick function\n */\n+#define NIX_RX_VWQE_F\t BIT(14)\n #define NIX_RX_MULTI_SEG_F BIT(15)\n \n #define CNXK_NIX_CQ_ENTRY_SZ 128\n@@ -28,6 +29,11 @@\n #define CQE_CAST(x)\t ((struct nix_cqe_hdr_s *)(x))\n #define CQE_SZ(x)\t ((x) * CNXK_NIX_CQ_ENTRY_SZ)\n \n+#define CQE_PTR_OFF(b, i, o, f) \\\n+\t(((f) & NIX_RX_VWQE_F) ? \\\n+\t\t (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) + (o)) : \\\n+\t\t (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) + (o)))\n+\n union mbuf_initializer {\n \tstruct {\n \t\tuint16_t data_off;\n@@ -317,61 +323,87 @@ nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf)\n }\n \n static __rte_always_inline uint16_t\n-cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n-\t\t\t uint16_t pkts, const uint16_t flags)\n+cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n+\t\t\t const uint16_t flags, void *lookup_mem,\n+\t\t\t struct cnxk_timesync_info *tstamp)\n {\n-\tstruct cn10k_eth_rxq *rxq = rx_queue;\n-\tuint16_t packets = 0;\n+\tstruct cn10k_eth_rxq *rxq = args;\n+\tconst uint64_t mbuf_initializer = (flags & NIX_RX_VWQE_F) ?\n+\t\t\t\t\t\t\t*(uint64_t *)args :\n+\t\t\t\t\t\t\trxq->mbuf_initializer;\n+\tconst uint64x2_t data_off = flags & NIX_RX_VWQE_F ?\n+\t\t\t\t\t\t vdupq_n_u64(0x80ULL) :\n+\t\t\t\t\t\t vdupq_n_u64(rxq->data_off);\n+\tconst uint32_t qmask = flags & NIX_RX_VWQE_F ? 0 : rxq->qmask;\n+\tconst uint64_t wdata = flags & NIX_RX_VWQE_F ? 0 : rxq->wdata;\n+\tconst uintptr_t desc = flags & NIX_RX_VWQE_F ? 0 : rxq->desc;\n \tuint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;\n-\tconst uint64_t mbuf_initializer = rxq->mbuf_initializer;\n-\tconst uint64x2_t data_off = vdupq_n_u64(rxq->data_off);\n \tuint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;\n \tuint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);\n \tuint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);\n \tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n \tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n \tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n-\tconst uint16_t *lookup_mem = rxq->lookup_mem;\n-\tconst uint32_t qmask = rxq->qmask;\n-\tconst uint64_t wdata = rxq->wdata;\n-\tconst uintptr_t desc = rxq->desc;\n \tuint8x16_t f0, f1, f2, f3;\n-\tuint32_t head = rxq->head;\n+\tuint16_t packets = 0;\n \tuint16_t pkts_left;\n-\n-\tpkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n-\tpkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);\n-\n-\t/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */\n-\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\tuint32_t head;\n+\tuintptr_t cq0;\n+\n+\tif (!(flags & NIX_RX_VWQE_F)) {\n+\t\tlookup_mem = rxq->lookup_mem;\n+\t\thead = rxq->head;\n+\n+\t\tpkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\t\tpkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);\n+\t\t/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */\n+\t\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\t\tif (flags & NIX_RX_OFFLOAD_TSTAMP_F)\n+\t\t\ttstamp = rxq->tstamp;\n+\t} else {\n+\t\tRTE_SET_USED(head);\n+\t}\n \n \twhile (packets < pkts) {\n-\t\t/* Exit loop if head is about to wrap and become unaligned */\n-\t\tif (((head + NIX_DESCS_PER_LOOP - 1) & qmask) <\n-\t\t NIX_DESCS_PER_LOOP) {\n-\t\t\tpkts_left += (pkts - packets);\n-\t\t\tbreak;\n-\t\t}\n+\t\tif (!(flags & NIX_RX_VWQE_F)) {\n+\t\t\t/* Exit loop if head is about to wrap and become\n+\t\t\t * unaligned.\n+\t\t\t */\n+\t\t\tif (((head + NIX_DESCS_PER_LOOP - 1) & qmask) <\n+\t\t\t NIX_DESCS_PER_LOOP) {\n+\t\t\t\tpkts_left += (pkts - packets);\n+\t\t\t\tbreak;\n+\t\t\t}\n \n-\t\tconst uintptr_t cq0 = desc + CQE_SZ(head);\n+\t\t\tcq0 = desc + CQE_SZ(head);\n+\t\t} else {\n+\t\t\tcq0 = (uintptr_t)&mbufs[packets];\n+\t\t}\n \n \t\t/* Prefetch N desc ahead */\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 8, 0, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 9, 0, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 10, 0, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 11, 0, flags));\n \n \t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n-\t\tcq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));\n-\t\tcq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));\n-\t\tcq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));\n-\t\tcq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));\n-\n-\t\t/* Extract mbuf from NIX_RX_SG_S */\n-\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n-\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n-\t\tmbuf01 = vqsubq_u64(mbuf01, data_off);\n-\t\tmbuf23 = vqsubq_u64(mbuf23, data_off);\n+\t\tcq0_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 0, 64, flags));\n+\t\tcq1_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 1, 64, flags));\n+\t\tcq2_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 2, 64, flags));\n+\t\tcq3_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 3, 64, flags));\n+\n+\t\tif (!(flags & NIX_RX_VWQE_F)) {\n+\t\t\t/* Extract mbuf from NIX_RX_SG_S */\n+\t\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n+\t\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n+\t\t\tmbuf01 = vqsubq_u64(mbuf01, data_off);\n+\t\t\tmbuf23 = vqsubq_u64(mbuf23, data_off);\n+\t\t} else {\n+\t\t\tmbuf01 =\n+\t\t\t\tvsubq_u64(vld1q_u64((uint64_t *)cq0), data_off);\n+\t\t\tmbuf23 = vsubq_u64(vld1q_u64((uint64_t *)(cq0 + 16)),\n+\t\t\t\t\t data_off);\n+\t\t}\n \n \t\t/* Move mbufs to scalar registers for future use */\n \t\tmbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);\n@@ -395,14 +427,14 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n \n \t\t/* Load CQE word0 and word 1 */\n-\t\tuint64_t cq0_w0 = ((uint64_t *)(cq0 + CQE_SZ(0)))[0];\n-\t\tuint64_t cq0_w1 = ((uint64_t *)(cq0 + CQE_SZ(0)))[1];\n-\t\tuint64_t cq1_w0 = ((uint64_t *)(cq0 + CQE_SZ(1)))[0];\n-\t\tuint64_t cq1_w1 = ((uint64_t *)(cq0 + CQE_SZ(1)))[1];\n-\t\tuint64_t cq2_w0 = ((uint64_t *)(cq0 + CQE_SZ(2)))[0];\n-\t\tuint64_t cq2_w1 = ((uint64_t *)(cq0 + CQE_SZ(2)))[1];\n-\t\tuint64_t cq3_w0 = ((uint64_t *)(cq0 + CQE_SZ(3)))[0];\n-\t\tuint64_t cq3_w1 = ((uint64_t *)(cq0 + CQE_SZ(3)))[1];\n+\t\tconst uint64_t cq0_w0 = *CQE_PTR_OFF(cq0, 0, 0, flags);\n+\t\tconst uint64_t cq0_w1 = *CQE_PTR_OFF(cq0, 0, 1, flags);\n+\t\tconst uint64_t cq1_w0 = *CQE_PTR_OFF(cq0, 1, 0, flags);\n+\t\tconst uint64_t cq1_w1 = *CQE_PTR_OFF(cq0, 1, 1, flags);\n+\t\tconst uint64_t cq2_w0 = *CQE_PTR_OFF(cq0, 2, 0, flags);\n+\t\tconst uint64_t cq2_w1 = *CQE_PTR_OFF(cq0, 2, 1, flags);\n+\t\tconst uint64_t cq3_w0 = *CQE_PTR_OFF(cq0, 3, 0, flags);\n+\t\tconst uint64_t cq3_w1 = *CQE_PTR_OFF(cq0, 3, 1, flags);\n \n \t\tif (flags & NIX_RX_OFFLOAD_RSS_F) {\n \t\t\t/* Fill rss in the rx_descriptor_fields1 */\n@@ -459,17 +491,17 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \t\tif (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {\n \t\t\tol_flags0 = nix_update_match_id(\n-\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(0) + 38), ol_flags0,\n-\t\t\t\tmbuf0);\n+\t\t\t\t*(uint16_t *)CQE_PTR_OFF(cq0, 0, 38, flags),\n+\t\t\t\tol_flags0, mbuf0);\n \t\t\tol_flags1 = nix_update_match_id(\n-\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(1) + 38), ol_flags1,\n-\t\t\t\tmbuf1);\n+\t\t\t\t*(uint16_t *)CQE_PTR_OFF(cq0, 1, 38, flags),\n+\t\t\t\tol_flags1, mbuf1);\n \t\t\tol_flags2 = nix_update_match_id(\n-\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(2) + 38), ol_flags2,\n-\t\t\t\tmbuf2);\n+\t\t\t\t*(uint16_t *)CQE_PTR_OFF(cq0, 2, 38, flags),\n+\t\t\t\tol_flags2, mbuf2);\n \t\t\tol_flags3 = nix_update_match_id(\n-\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(3) + 38), ol_flags3,\n-\t\t\t\tmbuf3);\n+\t\t\t\t*(uint16_t *)CQE_PTR_OFF(cq0, 3, 38, flags),\n+\t\t\t\tol_flags3, mbuf3);\n \t\t}\n \n \t\tif (flags & NIX_RX_OFFLOAD_TSTAMP_F) {\n@@ -488,7 +520,7 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC};\n \t\t\tconst uint64_t ts_olf = PKT_RX_IEEE1588_PTP |\n \t\t\t\t\t\tPKT_RX_IEEE1588_TMST |\n-\t\t\t\t\t\trxq->tstamp->rx_tstamp_dynflag;\n+\t\t\t\t\t\ttstamp->rx_tstamp_dynflag;\n \t\t\tconst uint32x4_t and_mask = {0x1, 0x2, 0x4, 0x8};\n \t\t\tuint64x2_t ts01, ts23, mask;\n \t\t\tuint64_t ts[4];\n@@ -526,14 +558,10 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\tts[3] = vgetq_lane_u64(ts23, 1);\n \n \t\t\t/* Store timestamp into dynfield. */\n-\t\t\t*cnxk_nix_timestamp_dynfield(mbuf0, rxq->tstamp) =\n-\t\t\t\tts[0];\n-\t\t\t*cnxk_nix_timestamp_dynfield(mbuf1, rxq->tstamp) =\n-\t\t\t\tts[1];\n-\t\t\t*cnxk_nix_timestamp_dynfield(mbuf2, rxq->tstamp) =\n-\t\t\t\tts[2];\n-\t\t\t*cnxk_nix_timestamp_dynfield(mbuf3, rxq->tstamp) =\n-\t\t\t\tts[3];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf0, tstamp) = ts[0];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf1, tstamp) = ts[1];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf2, tstamp) = ts[2];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf3, tstamp) = ts[3];\n \n \t\t\t/* Generate ptype mask to filter L2 ether timesync */\n \t\t\tmask = vdupq_n_u32(vgetq_lane_u32(f0, 0));\n@@ -559,9 +587,8 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\t/* Update Rxq timestamp with the latest\n \t\t\t\t * timestamp.\n \t\t\t\t */\n-\t\t\t\trxq->tstamp->rx_ready = 1;\n-\t\t\t\trxq->tstamp->rx_tstamp =\n-\t\t\t\t\tts[31 - __builtin_clz(res)];\n+\t\t\t\ttstamp->rx_ready = 1;\n+\t\t\t\ttstamp->rx_tstamp = ts[31 - __builtin_clz(res)];\n \t\t\t}\n \t\t}\n \n@@ -584,25 +611,25 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n \n \t\t/* Store the mbufs to rx_pkts */\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n+\t\tvst1q_u64((uint64_t *)&mbufs[packets], mbuf01);\n+\t\tvst1q_u64((uint64_t *)&mbufs[packets + 2], mbuf23);\n \n \t\tif (flags & NIX_RX_MULTI_SEG_F) {\n \t\t\t/* Multi segment is enable build mseg list for\n \t\t\t * individual mbufs in scalar mode.\n \t\t\t */\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t\t(cq0 + CQE_SZ(0) + 8), mbuf0,\n-\t\t\t\t\t mbuf_initializer, flags);\n+\t\t\t\t\t (CQE_PTR_OFF(cq0, 0, 8, flags)),\n+\t\t\t\t\t mbuf0, mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t\t(cq0 + CQE_SZ(1) + 8), mbuf1,\n-\t\t\t\t\t mbuf_initializer, flags);\n+\t\t\t\t\t (CQE_PTR_OFF(cq0, 1, 8, flags)),\n+\t\t\t\t\t mbuf1, mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t\t(cq0 + CQE_SZ(2) + 8), mbuf2,\n-\t\t\t\t\t mbuf_initializer, flags);\n+\t\t\t\t\t (CQE_PTR_OFF(cq0, 2, 8, flags)),\n+\t\t\t\t\t mbuf2, mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t\t(cq0 + CQE_SZ(3) + 8), mbuf3,\n-\t\t\t\t\t mbuf_initializer, flags);\n+\t\t\t\t\t (CQE_PTR_OFF(cq0, 3, 8, flags)),\n+\t\t\t\t\t mbuf3, mbuf_initializer, flags);\n \t\t} else {\n \t\t\t/* Update that no more segments */\n \t\t\tmbuf0->next = NULL;\n@@ -623,12 +650,18 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t__mempool_check_cookies(mbuf2->pool, (void **)&mbuf2, 1, 1);\n \t\t__mempool_check_cookies(mbuf3->pool, (void **)&mbuf3, 1, 1);\n \n-\t\t/* Advance head pointer and packets */\n-\t\thead += NIX_DESCS_PER_LOOP;\n-\t\thead &= qmask;\n \t\tpackets += NIX_DESCS_PER_LOOP;\n+\n+\t\tif (!(flags & NIX_RX_VWQE_F)) {\n+\t\t\t/* Advance head pointer and packets */\n+\t\t\thead += NIX_DESCS_PER_LOOP;\n+\t\t\thead &= qmask;\n+\t\t}\n \t}\n \n+\tif (flags & NIX_RX_VWQE_F)\n+\t\treturn packets;\n+\n \trxq->head = head;\n \trxq->available -= packets;\n \n@@ -637,8 +670,8 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \tplt_write64((rxq->wdata | packets), rxq->cq_door);\n \n \tif (unlikely(pkts_left))\n-\t\tpackets += cn10k_nix_recv_pkts(rx_queue, &rx_pkts[packets],\n-\t\t\t\t\t pkts_left, flags);\n+\t\tpackets += cn10k_nix_recv_pkts(args, &mbufs[packets], pkts_left,\n+\t\t\t\t\t flags);\n \n \treturn packets;\n }\n@@ -647,12 +680,15 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n static inline uint16_t\n cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n-\t\t\t uint16_t pkts, const uint16_t flags)\n+\t\t\t uint16_t pkts, const uint16_t flags,\n+\t\t\t void *lookup_mem, void *tstamp)\n {\n+\tRTE_SET_USED(lookup_mem);\n \tRTE_SET_USED(rx_queue);\n \tRTE_SET_USED(rx_pkts);\n \tRTE_SET_USED(pkts);\n \tRTE_SET_USED(flags);\n+\tRTE_SET_USED(tstamp);\n \n \treturn 0;\n }\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec.c b/drivers/net/cnxk/cn10k_rx_vec.c\nindex 93528a44f9..166735ad59 100644\n--- a/drivers/net/cnxk/cn10k_rx_vec.c\n+++ b/drivers/net/cnxk/cn10k_rx_vec.c\n@@ -12,7 +12,7 @@\n \t\t\t\t\t uint16_t pkts) \\\n \t{ \\\n \t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n-\t\t\t\t\t\t (flags));\t\t \\\n+\t\t\t\t\t\t (flags), NULL, NULL); \\\n \t}\n \n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec_mseg.c b/drivers/net/cnxk/cn10k_rx_vec_mseg.c\nindex 04d1e46c82..1f44dddddd 100644\n--- a/drivers/net/cnxk/cn10k_rx_vec_mseg.c\n+++ b/drivers/net/cnxk/cn10k_rx_vec_mseg.c\n@@ -9,8 +9,9 @@\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_mseg_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n \t{ \\\n-\t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n-\t\t\t\t\t (flags) | NIX_RX_MULTI_SEG_F); \\\n+\t\treturn cn10k_nix_recv_pkts_vector( \\\n+\t\t\trx_queue, rx_pkts, pkts, (flags) | NIX_RX_MULTI_SEG_F, \\\n+\t\t\tNULL, NULL); \\\n \t}\n \n NIX_RX_FASTPATH_MODES\n", "prefixes": [ "v3", "12/13" ] }