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GET /api/patches/94565/?format=api
{ "id": 94565, "url": "https://patches.dpdk.org/api/patches/94565/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-8-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210620202906.10974-8-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210620202906.10974-8-pbhagavatula@marvell.com", "date": "2021-06-20T20:29:01", "name": "[v3,08/13] event/cnxk: add Rx adapter fastpath ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8e0f94d6be1a998cb536400d3067bbe31bc307ef", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-8-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17410, "url": "https://patches.dpdk.org/api/series/17410/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17410", "date": "2021-06-20T20:28:54", "name": "[v3,01/13] net/cnxk: add multi seg Rx vector routine", "version": 3, "mbox": "https://patches.dpdk.org/series/17410/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94565/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94565/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C6D1A0547;\n\tSun, 20 Jun 2021 22:30:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E1E3341175;\n\tSun, 20 Jun 2021 22:29:44 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7FEC841142\n for <dev@dpdk.org>; Sun, 20 Jun 2021 22:29:42 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15KKQOMY010167 for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:41 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 399dxrmgsc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:41 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 20 Jun 2021 13:29:39 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 20 Jun 2021 13:29:39 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id E6F763F7066;\n Sun, 20 Jun 2021 13:29:37 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=C9ZcgtU7x0/U4EQgUIpLzMZwXEif23tVZSZmUzL+OoM=;\n b=lBwRgquWnEs5xc90TCJtJZ2f3+AqNe8qCMoyal3WsVlCN0Pmwkn20gZMuxc397jNf8F+\n /JolZTOwP2NP67OkZNbSxnPhsFWqjQoSBEGoaysTpoZF5/QrljMmdOMQphu3b1a+0gW/\n liWsFmym5t9QysUd6J1bjKp+is5x3PCdNSfXzq/q1hSU9YJKFkAjVOdwvsCQ39Hv0W/1\n Ch0s2VuGu1r6uAXH+DWZYieB3QG1w/4XJD6J4h0hh4/E8qAehYgWA6cuS889VnkbzhMa\n Myff39K1dH4phz2p43/3kD+r7o7E3SXsXYvgXjpL+hK7S6hg5+B2ftjpj4nxWox96VcL DA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 21 Jun 2021 01:59:01 +0530", "Message-ID": "<20210620202906.10974-8-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210620202906.10974-1-pbhagavatula@marvell.com>", "References": "<20210619110154.10301-1-pbhagavatula@marvell.com>\n <20210620202906.10974-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "6OaS1mjLMGLBh8zjqoobOYOGv9oDieC1", "X-Proofpoint-GUID": "6OaS1mjLMGLBh8zjqoobOYOGv9oDieC1", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-20_14:2021-06-20,\n 2021-06-20 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 08/13] event/cnxk: add Rx adapter fastpath ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd support for event eth Rx adapter fastpath operations.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 136 +++++++-\n drivers/event/cnxk/cn10k_worker.c | 54 ----\n drivers/event/cnxk/cn10k_worker.h | 97 +++++-\n drivers/event/cnxk/cn10k_worker_deq.c | 44 +++\n drivers/event/cnxk/cn10k_worker_deq_burst.c | 29 ++\n drivers/event/cnxk/cn10k_worker_deq_tmo.c | 72 +++++\n drivers/event/cnxk/cn9k_eventdev.c | 305 +++++++++++++++++-\n drivers/event/cnxk/cn9k_worker.c | 117 -------\n drivers/event/cnxk/cn9k_worker.h | 174 ++++++++--\n drivers/event/cnxk/cn9k_worker_deq.c | 44 +++\n drivers/event/cnxk/cn9k_worker_deq_burst.c | 29 ++\n drivers/event/cnxk/cn9k_worker_deq_tmo.c | 72 +++++\n drivers/event/cnxk/cn9k_worker_dual_deq.c | 53 +++\n .../event/cnxk/cn9k_worker_dual_deq_burst.c | 30 ++\n drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c | 89 +++++\n drivers/event/cnxk/cnxk_eventdev.h | 1 +\n drivers/event/cnxk/meson.build | 9 +\n 17 files changed, 1124 insertions(+), 231 deletions(-)\n create mode 100644 drivers/event/cnxk/cn10k_worker_deq.c\n create mode 100644 drivers/event/cnxk/cn10k_worker_deq_burst.c\n create mode 100644 drivers/event/cnxk/cn10k_worker_deq_tmo.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_deq.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_deq_burst.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_deq_tmo.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_dual_deq.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_dual_deq_burst.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 2060c8fe84..ba7d95fff7 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -237,17 +237,141 @@ static void\n cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tconst event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_tmo_deq[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_tmo_deq_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_tmo_deq_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_tmo_deq_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t\t};\n \n \tevent_dev->enqueue = cn10k_sso_hws_enq;\n \tevent_dev->enqueue_burst = cn10k_sso_hws_enq_burst;\n \tevent_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;\n \tevent_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;\n-\n-\tevent_dev->dequeue = cn10k_sso_hws_deq;\n-\tevent_dev->dequeue_burst = cn10k_sso_hws_deq_burst;\n-\tif (dev->is_timeout_deq) {\n-\t\tevent_dev->dequeue = cn10k_sso_hws_tmo_deq;\n-\t\tevent_dev->dequeue_burst = cn10k_sso_hws_tmo_deq_burst;\n+\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n+\t\tevent_dev->dequeue = sso_hws_deq_seg\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_seg_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_tmo_deq_seg\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_tmo_deq_seg_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n+\t} else {\n+\t\tevent_dev->dequeue = sso_hws_deq\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_tmo_deq\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_tmo_deq_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n \t}\n }\n \ndiff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nindex 5dbae275ba..c71aa37327 100644\n--- a/drivers/event/cnxk/cn10k_worker.c\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -60,57 +60,3 @@ cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \n \treturn 1;\n }\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn10k_sso_hws *ws = port;\n-\n-\tRTE_SET_USED(timeout_ticks);\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0);\n-\t\treturn 1;\n-\t}\n-\n-\treturn cn10k_sso_hws_get_work(ws, ev);\n-}\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events,\n-\t\t\tuint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn10k_sso_hws_deq(port, ev, timeout_ticks);\n-}\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_tmo_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn10k_sso_hws *ws = port;\n-\tuint16_t ret = 1;\n-\tuint64_t iter;\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0);\n-\t\treturn ret;\n-\t}\n-\n-\tret = cn10k_sso_hws_get_work(ws, ev);\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++)\n-\t\tret = cn10k_sso_hws_get_work(ws, ev);\n-\n-\treturn ret;\n-}\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t uint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn10k_sso_hws_tmo_deq(port, ev, timeout_ticks);\n-}\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex c7250bf9e7..b724083caa 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -87,20 +87,37 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,\n \t\tcn10k_sso_hws_fwd_group(ws, ev, grp);\n }\n \n+static __rte_always_inline void\n+cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n+\t\t const uint32_t tag, const uint32_t flags,\n+\t\t const void *const lookup_mem)\n+{\n+\tconst uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |\n+\t\t\t\t (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);\n+\n+\tcn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,\n+\t\t\t (struct rte_mbuf *)mbuf, lookup_mem,\n+\t\t\t mbuf_init | ((uint64_t)port_id) << 48, flags);\n+}\n+\n static __rte_always_inline uint16_t\n-cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev)\n+cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n+\t\t const uint32_t flags, void *lookup_mem)\n {\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t tstamp_ptr;\n+\tuint64_t mbuf;\n \n \tgw.get_work = ws->gw_wdata;\n #if defined(RTE_ARCH_ARM64) && !defined(__clang__)\n \tasm volatile(\n \t\tPLT_CPU_FEATURE_PREAMBLE\n \t\t\"caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\\n\"\n-\t\t: [wdata] \"+r\"(gw.get_work)\n+\t\t\"sub %[mbuf], %H[wdata], #0x80\t\t\t\t\\n\"\n+\t\t: [wdata] \"+r\"(gw.get_work), [mbuf] \"=&r\"(mbuf)\n \t\t: [gw_loc] \"r\"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)\n \t\t: \"memory\");\n #else\n@@ -109,11 +126,34 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \t\troc_load_pair(gw.u64[0], gw.u64[1],\n \t\t\t ws->base + SSOW_LF_GWS_WQE0);\n \t} while (gw.u64[0] & BIT_ULL(63));\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\t/* Extracting tstamp, if PTP enabled*/\n+\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n+\t\t\t\t\t\t\t gw.u64[1]) +\n+\t\t\t\t\t\t CNXK_SSO_WQE_SG_PTR);\n+\t\t\tcnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,\n+\t\t\t\t\t\tws->tstamp,\n+\t\t\t\t\t\tflags & NIX_RX_OFFLOAD_TSTAMP_F,\n+\t\t\t\t\t\tflags & NIX_RX_MULTI_SEG_F,\n+\t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -128,6 +168,7 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n@@ -138,7 +179,9 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \t\t \"\t\tldp %[tag], %[wqp], [%[tag_loc]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\t\\n\"\n \t\t \"done%=:\tdmb ld\t\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->base + SSOW_LF_GWS_WQE0)\n \t\t : \"memory\");\n #else\n@@ -146,12 +189,25 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \t\troc_load_pair(gw.u64[0], gw.u64[1],\n \t\t\t ws->base + SSOW_LF_GWS_WQE0);\n \t} while (gw.u64[0] & BIT_ULL(63));\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, 0, NULL);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -170,16 +226,29 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n \t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events);\n \n-uint16_t __rte_hot cn10k_sso_hws_deq(void *port, struct rte_event *ev,\n-\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn10k_sso_hws_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn10k_sso_hws_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn10k_sso_hws_tmo_deq_burst(void *port,\n-\t\t\t\t\t struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n \n #endif\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq.c b/drivers/event/cnxk/cn10k_worker_deq.c\nnew file mode 100644\nindex 0000000000..36ec454ccc\n--- /dev/null\n+++ b/drivers/event/cnxk/cn10k_worker_deq.c\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn10k_sso_hws_get_work( \\\n+\t\t\tws, ev, flags | NIX_RX_MULTI_SEG_F, ws->lookup_mem); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq_burst.c b/drivers/event/cnxk/cn10k_worker_deq_burst.c\nnew file mode 100644\nindex 0000000000..29ecc551cf\n--- /dev/null\n+++ b/drivers/event/cnxk/cn10k_worker_deq_burst.c\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn10k_sso_hws_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn10k_sso_hws_deq_seg_##name(port, ev, timeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn10k_worker_deq_tmo.c b/drivers/event/cnxk/cn10k_worker_deq_tmo.c\nnew file mode 100644\nindex 0000000000..c8524a27bd\n--- /dev/null\n+++ b/drivers/event/cnxk/cn10k_worker_deq_tmo.c\n@@ -0,0 +1,72 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn ret; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn10k_sso_hws_deq_tmo_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn ret; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn10k_sso_hws_deq_tmo_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\ttimeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 072800c243..e386cb784a 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -252,17 +252,202 @@ static void\n cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\t/* Single WS modes */\n+\tconst event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t\t};\n+\n+\t/* Dual WS modes */\n+\tconst event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_dual_deq_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_dual_deq_tmo_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_dual_deq_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t\t};\n \n \tevent_dev->enqueue = cn9k_sso_hws_enq;\n \tevent_dev->enqueue_burst = cn9k_sso_hws_enq_burst;\n \tevent_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;\n \tevent_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;\n-\n-\tevent_dev->dequeue = cn9k_sso_hws_deq;\n-\tevent_dev->dequeue_burst = cn9k_sso_hws_deq_burst;\n-\tif (dev->deq_tmo_ns) {\n-\t\tevent_dev->dequeue = cn9k_sso_hws_tmo_deq;\n-\t\tevent_dev->dequeue_burst = cn9k_sso_hws_tmo_deq_burst;\n+\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n+\t\tevent_dev->dequeue = sso_hws_deq_seg\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_seg_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_deq_tmo_seg\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_deq_tmo_seg_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n+\t} else {\n+\t\tevent_dev->dequeue = sso_hws_deq\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_deq_tmo\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_deq_tmo_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n \t}\n \n \tif (dev->dual_ws) {\n@@ -272,14 +457,110 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\tevent_dev->enqueue_forward_burst =\n \t\t\tcn9k_sso_hws_dual_enq_fwd_burst;\n \n-\t\tevent_dev->dequeue = cn9k_sso_hws_dual_deq;\n-\t\tevent_dev->dequeue_burst = cn9k_sso_hws_dual_deq_burst;\n-\t\tif (dev->deq_tmo_ns) {\n-\t\t\tevent_dev->dequeue = cn9k_sso_hws_dual_tmo_deq;\n-\t\t\tevent_dev->dequeue_burst =\n-\t\t\t\tcn9k_sso_hws_dual_tmo_deq_burst;\n+\t\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n+\t\t\tevent_dev->dequeue = sso_hws_dual_deq_seg\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_dual_deq_seg_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tif (dev->is_timeout_deq) {\n+\t\t\t\tevent_dev->dequeue = sso_hws_dual_deq_tmo_seg\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t\tevent_dev->dequeue_burst =\n+\t\t\t\t\tsso_hws_dual_deq_tmo_seg_burst\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t}\n+\t\t} else {\n+\t\t\tevent_dev->dequeue = sso_hws_dual_deq\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_dual_deq_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tif (dev->is_timeout_deq) {\n+\t\t\t\tevent_dev->dequeue = sso_hws_dual_deq_tmo\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t\tevent_dev->dequeue_burst =\n+\t\t\t\t\tsso_hws_dual_deq_tmo_burst\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t}\n \t\t}\n \t}\n+\n+\trte_mb();\n }\n \n static void *\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nindex 9ceacc98dd..538bc4b0b3 100644\n--- a/drivers/event/cnxk/cn9k_worker.c\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -60,60 +60,6 @@ cn9k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \treturn 1;\n }\n \n-uint16_t __rte_hot\n-cn9k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws *ws = port;\n-\n-\tRTE_SET_USED(timeout_ticks);\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->tag_op);\n-\t\treturn 1;\n-\t}\n-\n-\treturn cn9k_sso_hws_get_work(ws, ev);\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events,\n-\t\t uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_deq(port, ev, timeout_ticks);\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_tmo_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws *ws = port;\n-\tuint16_t ret = 1;\n-\tuint64_t iter;\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->tag_op);\n-\t\treturn ret;\n-\t}\n-\n-\tret = cn9k_sso_hws_get_work(ws, ev);\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++)\n-\t\tret = cn9k_sso_hws_get_work(ws, ev);\n-\n-\treturn ret;\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t uint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_tmo_deq(port, ev, timeout_ticks);\n-}\n-\n /* Dual ws ops. */\n \n uint16_t __rte_hot\n@@ -171,66 +117,3 @@ cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],\n \n \treturn 1;\n }\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws_dual *dws = port;\n-\tuint16_t gw;\n-\n-\tRTE_SET_USED(timeout_ticks);\n-\tif (dws->swtag_req) {\n-\t\tdws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(dws->ws_state[!dws->vws].tag_op);\n-\t\treturn 1;\n-\t}\n-\n-\tgw = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws],\n-\t\t\t\t\t&dws->ws_state[!dws->vws], ev);\n-\tdws->vws = !dws->vws;\n-\treturn gw;\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t uint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_dual_deq(port, ev, timeout_ticks);\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws_dual *dws = port;\n-\tuint16_t ret = 1;\n-\tuint64_t iter;\n-\n-\tif (dws->swtag_req) {\n-\t\tdws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(dws->ws_state[!dws->vws].tag_op);\n-\t\treturn ret;\n-\t}\n-\n-\tret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws],\n-\t\t\t\t\t &dws->ws_state[!dws->vws], ev);\n-\tdws->vws = !dws->vws;\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) {\n-\t\tret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws],\n-\t\t\t\t\t\t &dws->ws_state[!dws->vws], ev);\n-\t\tdws->vws = !dws->vws;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\tuint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_dual_tmo_deq(port, ev, timeout_ticks);\n-}\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex f5a4401465..c01c00e1da 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -128,17 +128,36 @@ cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws,\n \t}\n }\n \n+static __rte_always_inline void\n+cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n+\t\t const uint32_t tag, const uint32_t flags,\n+\t\t const void *const lookup_mem)\n+{\n+\tconst uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |\n+\t\t\t\t (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);\n+\n+\tcn9k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,\n+\t\t\t (struct rte_mbuf *)mbuf, lookup_mem,\n+\t\t\t mbuf_init | ((uint64_t)port_id) << 48, flags);\n+}\n+\n static __rte_always_inline uint16_t\n cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\t\t struct cn9k_sso_hws_state *ws_pair,\n-\t\t\t struct rte_event *ev)\n+\t\t\t struct rte_event *ev, const uint32_t flags,\n+\t\t\t const void *const lookup_mem,\n+\t\t\t struct cnxk_timesync_info *const tstamp)\n {\n \tconst uint64_t set_gw = BIT_ULL(16) | 1;\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t tstamp_ptr;\n+\tuint64_t mbuf;\n \n+\tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\trte_prefetch_non_temporal(lookup_mem);\n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"rty%=:\t\t\t\t\t\\n\"\n@@ -147,7 +166,10 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n \t\t \"done%=:\tstr %[gw], [%[pong]]\t\t\\n\"\n \t\t \"\t\tdmb ld\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n+\t\t \"\t\tprfm pldl1keep, [%[mbuf]]\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op),\n \t\t [gw] \"r\"(set_gw), [pong] \"r\"(ws_pair->getwrk_op));\n #else\n@@ -156,12 +178,34 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\tgw.u64[0] = plt_read64(ws->tag_op);\n \tgw.u64[1] = plt_read64(ws->wqp_op);\n \tplt_write64(set_gw, ws_pair->getwrk_op);\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\t/* Extracting tstamp, if PTP enabled*/\n+\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n+\t\t\t\t\t\t\t gw.u64[1]) +\n+\t\t\t\t\t\t CNXK_SSO_WQE_SG_PTR);\n+\t\t\tcnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,\n+\t\t\t\t\t\tflags & NIX_RX_OFFLOAD_TSTAMP_F,\n+\t\t\t\t\t\tflags & NIX_RX_MULTI_SEG_F,\n+\t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -169,16 +213,22 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n }\n \n static __rte_always_inline uint16_t\n-cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n+cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,\n+\t\t const uint32_t flags, const void *const lookup_mem)\n {\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t tstamp_ptr;\n+\tuint64_t mbuf;\n \n \tplt_write64(BIT_ULL(16) | /* wait for work. */\n \t\t\t 1,\t /* Use Mask set 0. */\n \t\t ws->getwrk_op);\n+\n+\tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\trte_prefetch_non_temporal(lookup_mem);\n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n@@ -190,7 +240,10 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n \t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n \t\t \"done%=:\tdmb ld\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n+\t\t \"\t\tprfm pldl1keep, [%[mbuf]]\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op));\n #else\n \tgw.u64[0] = plt_read64(ws->tag_op);\n@@ -198,12 +251,35 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n \t\tgw.u64[0] = plt_read64(ws->tag_op);\n \n \tgw.u64[1] = plt_read64(ws->wqp_op);\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\t/* Extracting tstamp, if PTP enabled*/\n+\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n+\t\t\t\t\t\t\t gw.u64[1]) +\n+\t\t\t\t\t\t CNXK_SSO_WQE_SG_PTR);\n+\t\t\tcnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,\n+\t\t\t\t\t\tws->tstamp,\n+\t\t\t\t\t\tflags & NIX_RX_OFFLOAD_TSTAMP_F,\n+\t\t\t\t\t\tflags & NIX_RX_MULTI_SEG_F,\n+\t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -218,6 +294,7 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n@@ -230,7 +307,9 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n \t\t \"done%=:\tdmb ld\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op));\n #else\n \tgw.u64[0] = plt_read64(ws->tag_op);\n@@ -238,12 +317,25 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \t\tgw.u64[0] = plt_read64(ws->tag_op);\n \n \tgw.u64[1] = plt_read64(ws->wqp_op);\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, 0, NULL);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -274,28 +366,54 @@ uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,\n \t\t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t\t uint16_t nb_events);\n \n-uint16_t __rte_hot cn9k_sso_hws_deq(void *port, struct rte_event *ev,\n-\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\tuint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-\n-uint16_t __rte_hot cn9k_sso_hws_dual_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst(void *port,\n-\t\t\t\t\t struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_burst(void *port,\n-\t\t\t\t\t\t struct rte_event ev[],\n-\t\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t\t uint64_t timeout_ticks);\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n \n #endif\ndiff --git a/drivers/event/cnxk/cn9k_worker_deq.c b/drivers/event/cnxk/cn9k_worker_deq.c\nnew file mode 100644\nindex 0000000000..51ccaf4ec4\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_deq.c\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_get_work( \\\n+\t\t\tws, ev, flags | NIX_RX_MULTI_SEG_F, ws->lookup_mem); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker_deq_burst.c b/drivers/event/cnxk/cn9k_worker_deq_burst.c\nnew file mode 100644\nindex 0000000000..4e2801459b\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_deq_burst.c\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_deq_seg_##name(port, ev, timeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker_deq_tmo.c b/drivers/event/cnxk/cn9k_worker_deq_tmo.c\nnew file mode 100644\nindex 0000000000..9713d1ef00\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_deq_tmo.c\n@@ -0,0 +1,72 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn ret; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_deq_tmo_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn ret; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_deq_tmo_seg_##name(port, ev, \\\n+\t\t\t\t\t\t timeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker_dual_deq.c b/drivers/event/cnxk/cn9k_worker_dual_deq.c\nnew file mode 100644\nindex 0000000000..709fa2d9ef\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_dual_deq.c\n@@ -0,0 +1,53 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t gw; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tgw = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t&dws->ws_state[dws->vws], &dws->ws_state[!dws->vws], \\\n+\t\t\tev, flags, dws->lookup_mem, dws->tstamp); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\treturn gw; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t gw; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tgw = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t&dws->ws_state[dws->vws], &dws->ws_state[!dws->vws], \\\n+\t\t\tev, flags, dws->lookup_mem, dws->tstamp); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\treturn gw; \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c b/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c\nnew file mode 100644\nindex 0000000000..d50e1cf83f\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_dual_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_dual_deq_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\ttimeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c b/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c\nnew file mode 100644\nindex 0000000000..a0508fdf0d\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c\n@@ -0,0 +1,89 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tret = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t&dws->ws_state[dws->vws], &dws->ws_state[!dws->vws], \\\n+\t\t\tev, flags, dws->lookup_mem, dws->tstamp); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \\\n+\t\t\tret = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t\t&dws->ws_state[dws->vws], \\\n+\t\t\t\t&dws->ws_state[!dws->vws], ev, flags, \\\n+\t\t\t\tdws->lookup_mem, dws->tstamp); \\\n+\t\t\tdws->vws = !dws->vws; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn ret; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_dual_deq_tmo_##name(port, ev, \\\n+\t\t\t\t\t\t\ttimeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tret = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t&dws->ws_state[dws->vws], &dws->ws_state[!dws->vws], \\\n+\t\t\tev, flags, dws->lookup_mem, dws->tstamp); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \\\n+\t\t\tret = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t\t&dws->ws_state[dws->vws], \\\n+\t\t\t\t&dws->ws_state[!dws->vws], ev, flags, \\\n+\t\t\t\tdws->lookup_mem, dws->tstamp); \\\n+\t\t\tdws->vws = !dws->vws; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn ret; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_dual_deq_tmo_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\t timeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex b65d725f55..9d5d2d0339 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -33,6 +33,7 @@\n #define CNXK_SSO_MZ_NAME \"cnxk_evdev_mz\"\n #define CNXK_SSO_XAQ_CACHE_CNT (0x7)\n #define CNXK_SSO_XAQ_SLACK (8)\n+#define CNXK_SSO_WQE_SG_PTR (9)\n \n #define CNXK_TT_FROM_TAG(x)\t (((x) >> 32) & SSO_TT_EMPTY)\n #define CNXK_TT_FROM_EVENT(x)\t (((x) >> 38) & SSO_TT_EMPTY)\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex eda562f5b5..c5c1c0ee8e 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -11,8 +11,17 @@ endif\n sources = files(\n 'cn9k_eventdev.c',\n 'cn9k_worker.c',\n+ 'cn9k_worker_deq.c',\n+ 'cn9k_worker_deq_burst.c',\n+ 'cn9k_worker_deq_tmo.c',\n+ 'cn9k_worker_dual_deq.c',\n+ 'cn9k_worker_dual_deq_burst.c',\n+ 'cn9k_worker_dual_deq_tmo.c',\n 'cn10k_eventdev.c',\n 'cn10k_worker.c',\n+ 'cn10k_worker_deq.c',\n+ 'cn10k_worker_deq_burst.c',\n+ 'cn10k_worker_deq_tmo.c',\n 'cnxk_eventdev.c',\n 'cnxk_eventdev_adptr.c',\n 'cnxk_eventdev_selftest.c',\n", "prefixes": [ "v3", "08/13" ] }