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GET /api/patches/94560/?format=api
{ "id": 94560, "url": "https://patches.dpdk.org/api/patches/94560/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-3-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210620202906.10974-3-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210620202906.10974-3-pbhagavatula@marvell.com", "date": "2021-06-20T20:28:56", "name": "[v3,03/13] net/cnxk: enable VLAN processing in vector Tx", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e2ba872b4be2b3ae08dd30582781ed3b75d72ab9", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-3-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17410, "url": "https://patches.dpdk.org/api/series/17410/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17410", "date": "2021-06-20T20:28:54", "name": "[v3,01/13] net/cnxk: add multi seg Rx vector routine", "version": 3, "mbox": "https://patches.dpdk.org/series/17410/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94560/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94560/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8ACF6A0547;\n\tSun, 20 Jun 2021 22:29:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0943E41151;\n\tSun, 20 Jun 2021 22:29:26 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 7FA6541151\n for <dev@dpdk.org>; Sun, 20 Jun 2021 22:29:24 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15KKGfRA023551 for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:23 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 399g3qm1c4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:23 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 20 Jun 2021 13:29:21 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 20 Jun 2021 13:29:21 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 373203F7066;\n Sun, 20 Jun 2021 13:29:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=8vzOeUppOqFGgT/rWYE8pVlKheTBM15sgCg3133Wjxw=;\n b=hej5Vz+sTsUP/0rHslx2SQYnMQqhdL0L4X/r9fzF+/CxnK+XFP+/6a2nh2zAgAzxjcUu\n dVZN40kWZ3MYcwv3do0mAPzfBdbI61BuGvzV+9U9ehStAmpyZNcBjeajmZ/716Y44vJm\n hW0F1KXOOdguoHijBRfJ+gh21zmcKqQSCM3lHsPrsh6XQwzgkjHOsV6GRWOTW5TR+zoS\n qipt7B7mTlN8flokubcwR4PM2zeik3bjj1UJvAJeloZ/zVPxEh8iYBEfQTV8AWTteWDW\n +XmP+cH6na5R4z6clEciKpfMN+AJllpJ4gXMqnVqNBzAJXJ9L+0GM5D0csF7QhLrvP5N nQ==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Mon, 21 Jun 2021 01:58:56 +0530", "Message-ID": "<20210620202906.10974-3-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210620202906.10974-1-pbhagavatula@marvell.com>", "References": "<20210619110154.10301-1-pbhagavatula@marvell.com>\n <20210620202906.10974-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "lrz2V_SkY9ysmPXJSZi7xvfgyXzaPUvp", "X-Proofpoint-ORIG-GUID": "lrz2V_SkY9ysmPXJSZi7xvfgyXzaPUvp", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-20_11:2021-06-20,\n 2021-06-20 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 03/13] net/cnxk: enable VLAN processing in\n vector Tx", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nEnable VLAN offload in vector Tx burst function.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/cnxk/cn10k_tx.c | 3 +-\n drivers/net/cnxk/cn10k_tx.h | 125 +++++++++++++++++++++++++++----\n drivers/net/cnxk/cn10k_tx_vec.c | 3 +-\n drivers/net/cnxk/cn9k_tx.c | 3 +-\n drivers/net/cnxk/cn9k_tx.h | 128 ++++++++++++++++++++++++++++----\n drivers/net/cnxk/cn9k_tx_vec.c | 3 +-\n 6 files changed, 227 insertions(+), 38 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_tx.c b/drivers/net/cnxk/cn10k_tx.c\nindex 18694dc704..05bc163a40 100644\n--- a/drivers/net/cnxk/cn10k_tx.c\n+++ b/drivers/net/cnxk/cn10k_tx.c\n@@ -69,8 +69,7 @@ cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n \n \tif (dev->scalar_ena ||\n \t (dev->tx_offload_flags &\n-\t (NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F |\n-\t NIX_TX_OFFLOAD_TSO_F)))\n+\t (NIX_TX_OFFLOAD_TSTAMP_F | NIX_TX_OFFLOAD_TSO_F)))\n \t\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \telse\n \t\tpick_tx_func(eth_dev, nix_eth_tx_vec_burst);\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex 8b1446f25c..1e16978584 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -62,9 +62,14 @@ cn10k_nix_tx_ext_subs(const uint16_t flags)\n static __rte_always_inline uint8_t\n cn10k_nix_pkts_per_vec_brst(const uint16_t flags)\n {\n-\tRTE_SET_USED(flags);\n-\t/* We can pack up to 4 packets per LMTLINE if there are no offloads. */\n-\treturn 4 << ROC_LMT_LINES_PER_CORE_LOG2;\n+\treturn ((flags & NIX_TX_NEED_EXT_HDR) ? 2 : 4)\n+\t << ROC_LMT_LINES_PER_CORE_LOG2;\n+}\n+\n+static __rte_always_inline uint8_t\n+cn10k_nix_tx_dwords_per_line(const uint16_t flags)\n+{\n+\treturn (flags & NIX_TX_NEED_EXT_HDR) ? 6 : 8;\n }\n \n static __rte_always_inline uint64_t\n@@ -98,10 +103,9 @@ cn10k_nix_tx_steor_data(const uint16_t flags)\n static __rte_always_inline uint64_t\n cn10k_nix_tx_steor_vec_data(const uint16_t flags)\n {\n-\tconst uint64_t dw_m1 = 0x7;\n+\tconst uint64_t dw_m1 = cn10k_nix_tx_dwords_per_line(flags) - 1;\n \tuint64_t data;\n \n-\tRTE_SET_USED(flags);\n \t/* This will be moved to addr area */\n \tdata = dw_m1;\n \t/* 15 vector sizes for single seg */\n@@ -690,11 +694,14 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n {\n \tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n \tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n-\tuint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP];\n+\tuint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP],\n+\t\tcmd2[NIX_DESCS_PER_LOOP];\n \tuint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3, data, pa;\n \tuint64x2_t senddesc01_w0, senddesc23_w0;\n \tuint64x2_t senddesc01_w1, senddesc23_w1;\n \tuint16_t left, scalar, burst, i, lmt_id;\n+\tuint64x2_t sendext01_w0, sendext23_w0;\n+\tuint64x2_t sendext01_w1, sendext23_w1;\n \tuint64x2_t sgdesc01_w0, sgdesc23_w0;\n \tuint64x2_t sgdesc01_w1, sgdesc23_w1;\n \tstruct cn10k_eth_txq *txq = tx_queue;\n@@ -720,6 +727,14 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tsgdesc01_w0 = vld1q_dup_u64(&txq->sg_w0);\n \tsgdesc23_w0 = sgdesc01_w0;\n \n+\t/* Load command defaults into vector variables. */\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tsendext01_w0 = vld1q_dup_u64(&txq->cmd[0]);\n+\t\tsendext23_w0 = sendext01_w0;\n+\t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n+\t\tsendext23_w1 = sendext01_w1;\n+\t}\n+\n \t/* Get LMT base address and LMT ID as lcore id */\n \tROC_LMT_BASE_ID_GET(laddr, lmt_id);\n \tleft = pkts;\n@@ -738,6 +753,13 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tsenddesc23_w0 = senddesc01_w0;\n \t\tsgdesc23_w0 = sgdesc01_w0;\n \n+\t\t/* Clear vlan enables. */\n+\t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t\tsendext01_w1 = vbicq_u64(sendext01_w1,\n+\t\t\t\t\t\t vdupq_n_u64(0x3FFFF00FFFF00));\n+\t\t\tsendext23_w1 = sendext01_w1;\n+\t\t}\n+\n \t\t/* Move mbufs to iova */\n \t\tmbuf0 = (uint64_t *)tx_pkts[0];\n \t\tmbuf1 = (uint64_t *)tx_pkts[1];\n@@ -1303,6 +1325,52 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n \t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n \n+\t\tif (flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) {\n+\t\t\t/* Tx ol_flag for vlan. */\n+\t\t\tconst uint64x2_t olv = {PKT_TX_VLAN, PKT_TX_VLAN};\n+\t\t\t/* Bit enable for VLAN1 */\n+\t\t\tconst uint64x2_t mlv = {BIT_ULL(49), BIT_ULL(49)};\n+\t\t\t/* Tx ol_flag for QnQ. */\n+\t\t\tconst uint64x2_t olq = {PKT_TX_QINQ, PKT_TX_QINQ};\n+\t\t\t/* Bit enable for VLAN0 */\n+\t\t\tconst uint64x2_t mlq = {BIT_ULL(48), BIT_ULL(48)};\n+\t\t\t/* Load vlan values from packet. outer is VLAN 0 */\n+\t\t\tuint64x2_t ext01 = {\n+\t\t\t\t((uint32_t)tx_pkts[0]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[0]->vlan_tci) << 32,\n+\t\t\t\t((uint32_t)tx_pkts[1]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[1]->vlan_tci) << 32,\n+\t\t\t};\n+\t\t\tuint64x2_t ext23 = {\n+\t\t\t\t((uint32_t)tx_pkts[2]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[2]->vlan_tci) << 32,\n+\t\t\t\t((uint32_t)tx_pkts[3]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[3]->vlan_tci) << 32,\n+\t\t\t};\n+\n+\t\t\t/* Get ol_flags of the packets. */\n+\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n+\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n+\n+\t\t\t/* ORR vlan outer/inner values into cmd. */\n+\t\t\tsendext01_w1 = vorrq_u64(sendext01_w1, ext01);\n+\t\t\tsendext23_w1 = vorrq_u64(sendext23_w1, ext23);\n+\n+\t\t\t/* Test for offload enable bits and generate masks. */\n+\t\t\txtmp128 = vorrq_u64(vandq_u64(vtstq_u64(xtmp128, olv),\n+\t\t\t\t\t\t mlv),\n+\t\t\t\t\t vandq_u64(vtstq_u64(xtmp128, olq),\n+\t\t\t\t\t\t mlq));\n+\t\t\tytmp128 = vorrq_u64(vandq_u64(vtstq_u64(ytmp128, olv),\n+\t\t\t\t\t\t mlv),\n+\t\t\t\t\t vandq_u64(vtstq_u64(ytmp128, olq),\n+\t\t\t\t\t\t mlq));\n+\n+\t\t\t/* Set vlan enable bits into cmd based on mask. */\n+\t\t\tsendext01_w1 = vorrq_u64(sendext01_w1, xtmp128);\n+\t\t\tsendext23_w1 = vorrq_u64(sendext23_w1, ytmp128);\n+\t\t}\n+\n \t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n \t\t\t/* Set don't free bit if reference count > 1 */\n \t\t\txmask01 = vdupq_n_u64(0);\n@@ -1381,16 +1449,41 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tcmd1[2] = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);\n \t\tcmd1[3] = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);\n \n-\t\t/* Store the prepared send desc to LMT lines */\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd1[0]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd0[1]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd1[1]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd0[2]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[2]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 96), cmd0[3]);\n-\t\tvst1q_u64(LMT_OFF(laddr, lnum, 112), cmd1[3]);\n-\t\tlnum += 1;\n+\t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t\tcmd2[0] = vzip1q_u64(sendext01_w0, sendext01_w1);\n+\t\t\tcmd2[1] = vzip2q_u64(sendext01_w0, sendext01_w1);\n+\t\t\tcmd2[2] = vzip1q_u64(sendext23_w0, sendext23_w1);\n+\t\t\tcmd2[3] = vzip2q_u64(sendext23_w0, sendext23_w1);\n+\t\t}\n+\n+\t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t\t/* Store the prepared send desc to LMT lines */\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[0]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[0]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd0[1]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd2[1]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[1]);\n+\t\t\tlnum += 1;\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[2]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[2]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[2]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd0[3]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd2[3]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[3]);\n+\t\t\tlnum += 1;\n+\t\t} else {\n+\t\t\t/* Store the prepared send desc to LMT lines */\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd1[0]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd0[1]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd1[1]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd0[2]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[2]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 96), cmd0[3]);\n+\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 112), cmd1[3]);\n+\t\t\tlnum += 1;\n+\t\t}\n \n \t\ttx_pkts = tx_pkts + NIX_DESCS_PER_LOOP;\n \t}\ndiff --git a/drivers/net/cnxk/cn10k_tx_vec.c b/drivers/net/cnxk/cn10k_tx_vec.c\nindex 7453f3bc98..beb5c649bb 100644\n--- a/drivers/net/cnxk/cn10k_tx_vec.c\n+++ b/drivers/net/cnxk/cn10k_tx_vec.c\n@@ -14,8 +14,7 @@\n \t\tuint64_t cmd[sz]; \\\n \t\t\t\t\t\t\t\t\t \\\n \t\t/* VLAN, TSTMP, TSO is not supported by vec */ \\\n-\t\tif ((flags) & NIX_TX_OFFLOAD_VLAN_QINQ_F ||\t\t \\\n-\t\t (flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t \\\n+\t\tif ((flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t \\\n \t\t (flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn10k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd,\\\ndiff --git a/drivers/net/cnxk/cn9k_tx.c b/drivers/net/cnxk/cn9k_tx.c\nindex b802606075..4b43cdaff9 100644\n--- a/drivers/net/cnxk/cn9k_tx.c\n+++ b/drivers/net/cnxk/cn9k_tx.c\n@@ -68,8 +68,7 @@ cn9k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n \n \tif (dev->scalar_ena ||\n \t (dev->tx_offload_flags &\n-\t (NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F |\n-\t NIX_TX_OFFLOAD_TSO_F)))\n+\t (NIX_TX_OFFLOAD_TSTAMP_F | NIX_TX_OFFLOAD_TSO_F)))\n \t\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \telse\n \t\tpick_tx_func(eth_dev, nix_eth_tx_vec_burst);\ndiff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h\nindex 1899d6670f..d5715bb52d 100644\n--- a/drivers/net/cnxk/cn9k_tx.h\n+++ b/drivers/net/cnxk/cn9k_tx.h\n@@ -552,10 +552,13 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n {\n \tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n \tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n-\tuint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP];\n+\tuint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP],\n+\t\tcmd2[NIX_DESCS_PER_LOOP];\n \tuint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n \tuint64x2_t senddesc01_w0, senddesc23_w0;\n \tuint64x2_t senddesc01_w1, senddesc23_w1;\n+\tuint64x2_t sendext01_w0, sendext23_w0;\n+\tuint64x2_t sendext01_w1, sendext23_w1;\n \tuint64x2_t sgdesc01_w0, sgdesc23_w0;\n \tuint64x2_t sgdesc01_w1, sgdesc23_w1;\n \tstruct cn9k_eth_txq *txq = tx_queue;\n@@ -585,8 +588,19 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tsenddesc23_w0 = senddesc01_w0;\n \tsenddesc01_w1 = vdupq_n_u64(0);\n \tsenddesc23_w1 = senddesc01_w1;\n-\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n-\tsgdesc23_w0 = sgdesc01_w0;\n+\n+\t/* Load command defaults into vector variables. */\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tsendext01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n+\t\tsendext23_w0 = sendext01_w0;\n+\t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n+\t\tsendext23_w1 = sendext01_w1;\n+\t\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[4]);\n+\t\tsgdesc23_w0 = sgdesc01_w0;\n+\t} else {\n+\t\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n+\t\tsgdesc23_w0 = sgdesc01_w0;\n+\t}\n \n \tfor (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {\n \t\t/* Clear lower 32bit of SEND_HDR_W0 and SEND_SG_W0 */\n@@ -597,6 +611,13 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tsenddesc23_w0 = senddesc01_w0;\n \t\tsgdesc23_w0 = sgdesc01_w0;\n \n+\t\t/* Clear vlan enables. */\n+\t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t\tsendext01_w1 = vbicq_u64(sendext01_w1,\n+\t\t\t\t\t\t vdupq_n_u64(0x3FFFF00FFFF00));\n+\t\t\tsendext23_w1 = sendext01_w1;\n+\t\t}\n+\n \t\t/* Move mbufs to iova */\n \t\tmbuf0 = (uint64_t *)tx_pkts[0];\n \t\tmbuf1 = (uint64_t *)tx_pkts[1];\n@@ -1162,6 +1183,52 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n \t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n \n+\t\tif (flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) {\n+\t\t\t/* Tx ol_flag for vlan. */\n+\t\t\tconst uint64x2_t olv = {PKT_TX_VLAN, PKT_TX_VLAN};\n+\t\t\t/* Bit enable for VLAN1 */\n+\t\t\tconst uint64x2_t mlv = {BIT_ULL(49), BIT_ULL(49)};\n+\t\t\t/* Tx ol_flag for QnQ. */\n+\t\t\tconst uint64x2_t olq = {PKT_TX_QINQ, PKT_TX_QINQ};\n+\t\t\t/* Bit enable for VLAN0 */\n+\t\t\tconst uint64x2_t mlq = {BIT_ULL(48), BIT_ULL(48)};\n+\t\t\t/* Load vlan values from packet. outer is VLAN 0 */\n+\t\t\tuint64x2_t ext01 = {\n+\t\t\t\t((uint32_t)tx_pkts[0]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[0]->vlan_tci) << 32,\n+\t\t\t\t((uint32_t)tx_pkts[1]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[1]->vlan_tci) << 32,\n+\t\t\t};\n+\t\t\tuint64x2_t ext23 = {\n+\t\t\t\t((uint32_t)tx_pkts[2]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[2]->vlan_tci) << 32,\n+\t\t\t\t((uint32_t)tx_pkts[3]->vlan_tci_outer) << 8 |\n+\t\t\t\t\t((uint64_t)tx_pkts[3]->vlan_tci) << 32,\n+\t\t\t};\n+\n+\t\t\t/* Get ol_flags of the packets. */\n+\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n+\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n+\n+\t\t\t/* ORR vlan outer/inner values into cmd. */\n+\t\t\tsendext01_w1 = vorrq_u64(sendext01_w1, ext01);\n+\t\t\tsendext23_w1 = vorrq_u64(sendext23_w1, ext23);\n+\n+\t\t\t/* Test for offload enable bits and generate masks. */\n+\t\t\txtmp128 = vorrq_u64(vandq_u64(vtstq_u64(xtmp128, olv),\n+\t\t\t\t\t\t mlv),\n+\t\t\t\t\t vandq_u64(vtstq_u64(xtmp128, olq),\n+\t\t\t\t\t\t mlq));\n+\t\t\tytmp128 = vorrq_u64(vandq_u64(vtstq_u64(ytmp128, olv),\n+\t\t\t\t\t\t mlv),\n+\t\t\t\t\t vandq_u64(vtstq_u64(ytmp128, olq),\n+\t\t\t\t\t\t mlq));\n+\n+\t\t\t/* Set vlan enable bits into cmd based on mask. */\n+\t\t\tsendext01_w1 = vorrq_u64(sendext01_w1, xtmp128);\n+\t\t\tsendext23_w1 = vorrq_u64(sendext23_w1, ytmp128);\n+\t\t}\n+\n \t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n \t\t\t/* Set don't free bit if reference count > 1 */\n \t\t\txmask01 = vdupq_n_u64(0);\n@@ -1247,17 +1314,50 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tcmd1[2] = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);\n \t\tcmd1[3] = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);\n \n-\t\tdo {\n-\t\t\tvst1q_u64(lmt_addr, cmd0[0]);\n-\t\t\tvst1q_u64(lmt_addr + 2, cmd1[0]);\n-\t\t\tvst1q_u64(lmt_addr + 4, cmd0[1]);\n-\t\t\tvst1q_u64(lmt_addr + 6, cmd1[1]);\n-\t\t\tvst1q_u64(lmt_addr + 8, cmd0[2]);\n-\t\t\tvst1q_u64(lmt_addr + 10, cmd1[2]);\n-\t\t\tvst1q_u64(lmt_addr + 12, cmd0[3]);\n-\t\t\tvst1q_u64(lmt_addr + 14, cmd1[3]);\n-\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n-\t\t} while (lmt_status == 0);\n+\t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t\tcmd2[0] = vzip1q_u64(sendext01_w0, sendext01_w1);\n+\t\t\tcmd2[1] = vzip2q_u64(sendext01_w0, sendext01_w1);\n+\t\t\tcmd2[2] = vzip1q_u64(sendext23_w0, sendext23_w1);\n+\t\t\tcmd2[3] = vzip2q_u64(sendext23_w0, sendext23_w1);\n+\t\t}\n+\n+\t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t\t/* With ext header in the command we can no longer send\n+\t\t\t * all 4 packets together since LMTLINE is 128bytes.\n+\t\t\t * Split and Tx twice.\n+\t\t\t */\n+\t\t\tdo {\n+\t\t\t\tvst1q_u64(lmt_addr, cmd0[0]);\n+\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[0]);\n+\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[0]);\n+\t\t\t\tvst1q_u64(lmt_addr + 6, cmd0[1]);\n+\t\t\t\tvst1q_u64(lmt_addr + 8, cmd2[1]);\n+\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[1]);\n+\t\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t\t\t} while (lmt_status == 0);\n+\n+\t\t\tdo {\n+\t\t\t\tvst1q_u64(lmt_addr, cmd0[2]);\n+\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[2]);\n+\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[2]);\n+\t\t\t\tvst1q_u64(lmt_addr + 6, cmd0[3]);\n+\t\t\t\tvst1q_u64(lmt_addr + 8, cmd2[3]);\n+\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[3]);\n+\t\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t\t\t} while (lmt_status == 0);\n+\t\t} else {\n+\t\t\tdo {\n+\t\t\t\tvst1q_u64(lmt_addr, cmd0[0]);\n+\t\t\t\tvst1q_u64(lmt_addr + 2, cmd1[0]);\n+\t\t\t\tvst1q_u64(lmt_addr + 4, cmd0[1]);\n+\t\t\t\tvst1q_u64(lmt_addr + 6, cmd1[1]);\n+\t\t\t\tvst1q_u64(lmt_addr + 8, cmd0[2]);\n+\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[2]);\n+\t\t\t\tvst1q_u64(lmt_addr + 12, cmd0[3]);\n+\t\t\t\tvst1q_u64(lmt_addr + 14, cmd1[3]);\n+\t\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t\t\t} while (lmt_status == 0);\n+\t\t}\n \t\ttx_pkts = tx_pkts + NIX_DESCS_PER_LOOP;\n \t}\n \ndiff --git a/drivers/net/cnxk/cn9k_tx_vec.c b/drivers/net/cnxk/cn9k_tx_vec.c\nindex a6e7c9e542..5842facb58 100644\n--- a/drivers/net/cnxk/cn9k_tx_vec.c\n+++ b/drivers/net/cnxk/cn9k_tx_vec.c\n@@ -14,8 +14,7 @@\n \t\tuint64_t cmd[sz]; \\\n \t\t\t\t\t\t\t\t\t \\\n \t\t/* VLAN, TSTMP, TSO is not supported by vec */ \\\n-\t\tif ((flags) & NIX_TX_OFFLOAD_VLAN_QINQ_F ||\t\t \\\n-\t\t (flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t \\\n+\t\tif ((flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t \\\n \t\t (flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn9k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd, \\\n", "prefixes": [ "v3", "03/13" ] }