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GET /api/patches/94542/?format=api
{ "id": 94542, "url": "https://patches.dpdk.org/api/patches/94542/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210619110154.10301-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210619110154.10301-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210619110154.10301-2-pbhagavatula@marvell.com", "date": "2021-06-19T11:01:42", "name": "[v2,02/13] net/cnxk: enable ptp processing in vector Rx", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b688c0654ad2b5407c72d4d4553a273524a4b1f8", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210619110154.10301-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17405, "url": "https://patches.dpdk.org/api/series/17405/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17405", "date": "2021-06-19T11:01:41", "name": "[v2,01/13] net/cnxk: add multi seg Rx vector routine", "version": 2, "mbox": "https://patches.dpdk.org/series/17405/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94542/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94542/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6918A0A0C;\n\tSat, 19 Jun 2021 13:02:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E890C4111A;\n\tSat, 19 Jun 2021 13:02:16 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id EE62B40E32\n for <dev@dpdk.org>; Sat, 19 Jun 2021 13:02:14 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15JAu1tP007709 for <dev@dpdk.org>; Sat, 19 Jun 2021 04:02:14 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 398tu0v60v-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 19 Jun 2021 04:02:14 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sat, 19 Jun 2021 04:02:11 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sat, 19 Jun 2021 04:02:11 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id BE7885B696D;\n Sat, 19 Jun 2021 04:02:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=eRnjN9BIc/KwQK9oW4sScKQ3iCyDO4jZO8otyLqUS9E=;\n b=XTVFSAd8jc/OJ6d6y9/lRIt96cdYP+7BpHmhWBp4/mbCVbEeunkqilai+OGGn5Dlr3qc\n DcyNgSrAIMEk1f4miFBbgLfkJkhighFD4miYwSJlw1EZz+rusls1X5q7b9ojkhmyr6ow\n wSlM9iY7/KFMtc+JHnkeS20gSV+BIBcxowGdpKulZ/AlRiwLKeNs6HtiaOMEp01NO07R\n Gm3RMicCNctRBizCl8OlickrPUbPxROCwbwL7VSjwK2RC9hBoai+AsVgqvIR971dpq5u\n wP+HkVLfUVC5lLtsbxD1uKlIneeSPPY/L+pJ0gfMiZWVu6wjE9GTNaEeslFd7YFNrTu8 Kg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Sat, 19 Jun 2021 16:31:42 +0530", "Message-ID": "<20210619110154.10301-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210619110154.10301-1-pbhagavatula@marvell.com>", "References": "<20210524122303.1116-1-pbhagavatula@marvell.com>\n <20210619110154.10301-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "fVT4wlpuKG-wgN9UPLoeOruZeeAvczow", "X-Proofpoint-ORIG-GUID": "fVT4wlpuKG-wgN9UPLoeOruZeeAvczow", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-19_09:2021-06-18,\n 2021-06-19 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 02/13] net/cnxk: enable ptp processing in\n vector Rx", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nEnable PTP offload in vector Rx burst function, use vector path\nfor processing mbufs and finally switch to scalar when extracting\ntimestamp.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/cnxk/cn10k_ethdev.c | 1 -\n drivers/net/cnxk/cn10k_rx.c | 5 +-\n drivers/net/cnxk/cn10k_rx.h | 124 ++++++++++++++++++++++++++++----\n drivers/net/cnxk/cn10k_rx_vec.c | 3 -\n drivers/net/cnxk/cn9k_ethdev.c | 1 -\n drivers/net/cnxk/cn9k_rx.c | 5 +-\n drivers/net/cnxk/cn9k_rx.h | 124 ++++++++++++++++++++++++++++----\n drivers/net/cnxk/cn9k_rx_vec.c | 3 -\n drivers/net/cnxk/cnxk_ethdev.h | 19 ++---\n 9 files changed, 232 insertions(+), 53 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex b079edbd35..7caec6cf14 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -301,7 +301,6 @@ nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)\n \tif (nix_recalc_mtu(eth_dev))\n \t\tplt_err(\"Failed to set MTU size for ptp\");\n \n-\tdev->scalar_ena = true;\n \tdev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;\n \n \t/* Setting up the function pointers as per new offload flags */\ndiff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c\nindex 3a9fd71309..69e767ac3d 100644\n--- a/drivers/net/cnxk/cn10k_rx.c\n+++ b/drivers/net/cnxk/cn10k_rx.c\n@@ -75,10 +75,7 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n \t\tdev->rx_pkt_burst_no_offload =\n \t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0];\n \n-\t/* For PTP enabled, scalar rx function should be chosen as most of the\n-\t * PTP apps are implemented to rx burst 1 pkt.\n-\t */\n-\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {\n+\tif (dev->scalar_ena) {\n \t\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n \t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst);\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex 5926ff7f46..abdd58e888 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -109,7 +109,7 @@ nix_update_match_id(const uint16_t match_id, uint64_t ol_flags,\n \n static __rte_always_inline void\n nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n-\t\t uint64_t rearm)\n+\t\t uint64_t rearm, const uint16_t flags)\n {\n \tconst rte_iova_t *iova_list;\n \tstruct rte_mbuf *head;\n@@ -125,8 +125,10 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n \t\treturn;\n \t}\n \n-\tmbuf->pkt_len = rx->pkt_lenm1 + 1;\n-\tmbuf->data_len = sg & 0xFFFF;\n+\tmbuf->pkt_len = (rx->pkt_lenm1 + 1) - (flags & NIX_RX_OFFLOAD_TSTAMP_F ?\n+\t\t\t\t\t CNXK_NIX_TIMESYNC_RX_OFFSET : 0);\n+\tmbuf->data_len = (sg & 0xFFFF) - (flags & NIX_RX_OFFLOAD_TSTAMP_F ?\n+\t\t\t\t\t CNXK_NIX_TIMESYNC_RX_OFFSET : 0);\n \tmbuf->nb_segs = nb_segs;\n \tsg = sg >> 16;\n \n@@ -207,7 +209,7 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t*(uint64_t *)(&mbuf->rearm_data) = val;\n \n \tif (flag & NIX_RX_MULTI_SEG_F)\n-\t\tnix_cqe_xtract_mseg(rx, mbuf, val);\n+\t\tnix_cqe_xtract_mseg(rx, mbuf, val, flag);\n \telse\n \t\tmbuf->next = NULL;\n }\n@@ -272,8 +274,9 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \t\t\t\t flags);\n \t\tcnxk_nix_mbuf_to_tstamp(mbuf, rxq->tstamp,\n \t\t\t\t\t(flags & NIX_RX_OFFLOAD_TSTAMP_F),\n-\t\t\t\t\t(uint64_t *)((uint8_t *)mbuf + data_off)\n-\t\t\t\t\t);\n+\t\t\t\t\t(flags & NIX_RX_MULTI_SEG_F),\n+\t\t\t\t\t(uint64_t *)((uint8_t *)mbuf\n+\t\t\t\t\t\t\t\t+ data_off));\n \t\trx_pkts[packets++] = mbuf;\n \t\troc_prefetch_store_keep(mbuf);\n \t\thead++;\n@@ -469,6 +472,99 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\tmbuf3);\n \t\t}\n \n+\t\tif (flags & NIX_RX_OFFLOAD_TSTAMP_F) {\n+\t\t\tconst uint16x8_t len_off = {\n+\t\t\t\t0,\t\t\t /* ptype 0:15 */\n+\t\t\t\t0,\t\t\t /* ptype 16:32 */\n+\t\t\t\tCNXK_NIX_TIMESYNC_RX_OFFSET, /* pktlen 0:15*/\n+\t\t\t\t0,\t\t\t /* pktlen 16:32 */\n+\t\t\t\tCNXK_NIX_TIMESYNC_RX_OFFSET, /* datalen 0:15 */\n+\t\t\t\t0,\n+\t\t\t\t0,\n+\t\t\t\t0};\n+\t\t\tconst uint32x4_t ptype = {RTE_PTYPE_L2_ETHER_TIMESYNC,\n+\t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC,\n+\t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC,\n+\t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC};\n+\t\t\tconst uint64_t ts_olf = PKT_RX_IEEE1588_PTP |\n+\t\t\t\t\t\tPKT_RX_IEEE1588_TMST |\n+\t\t\t\t\t\trxq->tstamp->rx_tstamp_dynflag;\n+\t\t\tconst uint32x4_t and_mask = {0x1, 0x2, 0x4, 0x8};\n+\t\t\tuint64x2_t ts01, ts23, mask;\n+\t\t\tuint64_t ts[4];\n+\t\t\tuint8_t res;\n+\n+\t\t\t/* Substract timesync length from total pkt length. */\n+\t\t\tf0 = vsubq_u16(f0, len_off);\n+\t\t\tf1 = vsubq_u16(f1, len_off);\n+\t\t\tf2 = vsubq_u16(f2, len_off);\n+\t\t\tf3 = vsubq_u16(f3, len_off);\n+\n+\t\t\t/* Get the address of actual timestamp. */\n+\t\t\tts01 = vaddq_u64(mbuf01, data_off);\n+\t\t\tts23 = vaddq_u64(mbuf23, data_off);\n+\t\t\t/* Load timestamp from address. */\n+\t\t\tts01 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts01,\n+\t\t\t\t\t\t\t\t\t 0),\n+\t\t\t\t\t ts01, 0);\n+\t\t\tts01 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts01,\n+\t\t\t\t\t\t\t\t\t 1),\n+\t\t\t\t\t ts01, 1);\n+\t\t\tts23 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts23,\n+\t\t\t\t\t\t\t\t\t 0),\n+\t\t\t\t\t ts23, 0);\n+\t\t\tts23 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts23,\n+\t\t\t\t\t\t\t\t\t 1),\n+\t\t\t\t\t ts23, 1);\n+\t\t\t/* Convert from be to cpu byteorder. */\n+\t\t\tts01 = vrev64q_u8(ts01);\n+\t\t\tts23 = vrev64q_u8(ts23);\n+\t\t\t/* Store timestamp into scalar for later use. */\n+\t\t\tts[0] = vgetq_lane_u64(ts01, 0);\n+\t\t\tts[1] = vgetq_lane_u64(ts01, 1);\n+\t\t\tts[2] = vgetq_lane_u64(ts23, 0);\n+\t\t\tts[3] = vgetq_lane_u64(ts23, 1);\n+\n+\t\t\t/* Store timestamp into dynfield. */\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf0, rxq->tstamp) =\n+\t\t\t\tts[0];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf1, rxq->tstamp) =\n+\t\t\t\tts[1];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf2, rxq->tstamp) =\n+\t\t\t\tts[2];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf3, rxq->tstamp) =\n+\t\t\t\tts[3];\n+\n+\t\t\t/* Generate ptype mask to filter L2 ether timesync */\n+\t\t\tmask = vdupq_n_u32(vgetq_lane_u32(f0, 0));\n+\t\t\tmask = vsetq_lane_u32(vgetq_lane_u32(f1, 0), mask, 1);\n+\t\t\tmask = vsetq_lane_u32(vgetq_lane_u32(f2, 0), mask, 2);\n+\t\t\tmask = vsetq_lane_u32(vgetq_lane_u32(f3, 0), mask, 3);\n+\n+\t\t\t/* Match against L2 ether timesync. */\n+\t\t\tmask = vceqq_u32(mask, ptype);\n+\t\t\t/* Convert from vector from scalar mask */\n+\t\t\tres = vaddvq_u32(vandq_u32(mask, and_mask));\n+\t\t\tres &= 0xF;\n+\n+\t\t\tif (res) {\n+\t\t\t\t/* Fill in the ol_flags for any packets that\n+\t\t\t\t * matched.\n+\t\t\t\t */\n+\t\t\t\tol_flags0 |= ((res & 0x1) ? ts_olf : 0);\n+\t\t\t\tol_flags1 |= ((res & 0x2) ? ts_olf : 0);\n+\t\t\t\tol_flags2 |= ((res & 0x4) ? ts_olf : 0);\n+\t\t\t\tol_flags3 |= ((res & 0x8) ? ts_olf : 0);\n+\n+\t\t\t\t/* Update Rxq timestamp with the latest\n+\t\t\t\t * timestamp.\n+\t\t\t\t */\n+\t\t\t\trxq->tstamp->rx_ready = 1;\n+\t\t\t\trxq->tstamp->rx_tstamp =\n+\t\t\t\t\tts[31 - __builtin_clz(res)];\n+\t\t\t}\n+\t\t}\n+\n \t\t/* Form rearm_data with ol_flags */\n \t\trearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);\n \t\trearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);\n@@ -496,17 +592,17 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t * individual mbufs in scalar mode.\n \t\t\t */\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(0) + 8), mbuf0,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(0) + 8), mbuf0,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(1) + 8), mbuf1,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(1) + 8), mbuf1,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(2) + 8), mbuf2,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(2) + 8), mbuf2,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(3) + 8), mbuf3,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(3) + 8), mbuf3,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t} else {\n \t\t\t/* Update that no more segments */\n \t\t\tmbuf0->next = NULL;\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec.c b/drivers/net/cnxk/cn10k_rx_vec.c\nindex 65ffa97841..93528a44f9 100644\n--- a/drivers/net/cnxk/cn10k_rx_vec.c\n+++ b/drivers/net/cnxk/cn10k_rx_vec.c\n@@ -11,9 +11,6 @@\n \t\t\t\t\t struct rte_mbuf **rx_pkts, \\\n \t\t\t\t\t uint16_t pkts) \\\n \t{ \\\n-\t\t/* TSTMP is not supported by vector */ \\\n-\t\tif ((flags) & NIX_RX_OFFLOAD_TSTAMP_F) \\\n-\t\t\treturn 0; \\\n \t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n \t\t\t\t\t\t (flags));\t\t \\\n \t}\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex 107a540915..cb302b75d8 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -309,7 +309,6 @@ nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)\n \tif (nix_recalc_mtu(eth_dev))\n \t\tplt_err(\"Failed to set MTU size for ptp\");\n \n-\tdev->scalar_ena = true;\n \tdev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;\n \n \t/* Setting up the function pointers as per new offload flags */\ndiff --git a/drivers/net/cnxk/cn9k_rx.c b/drivers/net/cnxk/cn9k_rx.c\nindex d293d4eac3..7d9f1bd61f 100644\n--- a/drivers/net/cnxk/cn9k_rx.c\n+++ b/drivers/net/cnxk/cn9k_rx.c\n@@ -75,10 +75,7 @@ cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n \t\tdev->rx_pkt_burst_no_offload =\n \t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0];\n \n-\t/* For PTP enabled, scalar rx function should be chosen as most of the\n-\t * PTP apps are implemented to rx burst 1 pkt.\n-\t */\n-\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {\n+\tif (dev->scalar_ena) {\n \t\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n \t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst);\ndiff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h\nindex 5ae9e8195c..dd3e5d3c7e 100644\n--- a/drivers/net/cnxk/cn9k_rx.h\n+++ b/drivers/net/cnxk/cn9k_rx.h\n@@ -110,7 +110,7 @@ nix_update_match_id(const uint16_t match_id, uint64_t ol_flags,\n \n static __rte_always_inline void\n nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n-\t\t uint64_t rearm)\n+\t\t uint64_t rearm, const uint16_t flags)\n {\n \tconst rte_iova_t *iova_list;\n \tstruct rte_mbuf *head;\n@@ -126,8 +126,10 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n \t\treturn;\n \t}\n \n-\tmbuf->pkt_len = rx->pkt_lenm1 + 1;\n-\tmbuf->data_len = sg & 0xFFFF;\n+\tmbuf->pkt_len = (rx->pkt_lenm1 + 1) - (flags & NIX_RX_OFFLOAD_TSTAMP_F ?\n+\t\t\t\t\t CNXK_NIX_TIMESYNC_RX_OFFSET : 0);\n+\tmbuf->data_len = (sg & 0xFFFF) - (flags & NIX_RX_OFFLOAD_TSTAMP_F ?\n+\t\t\t\t\t CNXK_NIX_TIMESYNC_RX_OFFSET : 0);\n \tmbuf->nb_segs = nb_segs;\n \tsg = sg >> 16;\n \n@@ -210,7 +212,7 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t*(uint64_t *)(&mbuf->rearm_data) = val;\n \n \tif (flag & NIX_RX_MULTI_SEG_F)\n-\t\tnix_cqe_xtract_mseg(rx, mbuf, val);\n+\t\tnix_cqe_xtract_mseg(rx, mbuf, val, flag);\n \telse\n \t\tmbuf->next = NULL;\n }\n@@ -275,8 +277,9 @@ cn9k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \t\t\t\t flags);\n \t\tcnxk_nix_mbuf_to_tstamp(mbuf, rxq->tstamp,\n \t\t\t\t\t(flags & NIX_RX_OFFLOAD_TSTAMP_F),\n-\t\t\t\t\t(uint64_t *)((uint8_t *)mbuf + data_off)\n-\t\t\t\t\t);\n+\t\t\t\t\t(flags & NIX_RX_MULTI_SEG_F),\n+\t\t\t\t\t(uint64_t *)((uint8_t *)mbuf\n+\t\t\t\t\t\t\t\t+ data_off));\n \t\trx_pkts[packets++] = mbuf;\n \t\troc_prefetch_store_keep(mbuf);\n \t\thead++;\n@@ -472,6 +475,99 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\tmbuf3);\n \t\t}\n \n+\t\tif (flags & NIX_RX_OFFLOAD_TSTAMP_F) {\n+\t\t\tconst uint16x8_t len_off = {\n+\t\t\t\t0,\t\t\t /* ptype 0:15 */\n+\t\t\t\t0,\t\t\t /* ptype 16:32 */\n+\t\t\t\tCNXK_NIX_TIMESYNC_RX_OFFSET, /* pktlen 0:15*/\n+\t\t\t\t0,\t\t\t /* pktlen 16:32 */\n+\t\t\t\tCNXK_NIX_TIMESYNC_RX_OFFSET, /* datalen 0:15 */\n+\t\t\t\t0,\n+\t\t\t\t0,\n+\t\t\t\t0};\n+\t\t\tconst uint32x4_t ptype = {RTE_PTYPE_L2_ETHER_TIMESYNC,\n+\t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC,\n+\t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC,\n+\t\t\t\t\t\t RTE_PTYPE_L2_ETHER_TIMESYNC};\n+\t\t\tconst uint64_t ts_olf = PKT_RX_IEEE1588_PTP |\n+\t\t\t\t\t\tPKT_RX_IEEE1588_TMST |\n+\t\t\t\t\t\trxq->tstamp->rx_tstamp_dynflag;\n+\t\t\tconst uint32x4_t and_mask = {0x1, 0x2, 0x4, 0x8};\n+\t\t\tuint64x2_t ts01, ts23, mask;\n+\t\t\tuint64_t ts[4];\n+\t\t\tuint8_t res;\n+\n+\t\t\t/* Substract timesync length from total pkt length. */\n+\t\t\tf0 = vsubq_u16(f0, len_off);\n+\t\t\tf1 = vsubq_u16(f1, len_off);\n+\t\t\tf2 = vsubq_u16(f2, len_off);\n+\t\t\tf3 = vsubq_u16(f3, len_off);\n+\n+\t\t\t/* Get the address of actual timestamp. */\n+\t\t\tts01 = vaddq_u64(mbuf01, data_off);\n+\t\t\tts23 = vaddq_u64(mbuf23, data_off);\n+\t\t\t/* Load timestamp from address. */\n+\t\t\tts01 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts01,\n+\t\t\t\t\t\t\t\t\t 0),\n+\t\t\t\t\t ts01, 0);\n+\t\t\tts01 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts01,\n+\t\t\t\t\t\t\t\t\t 1),\n+\t\t\t\t\t ts01, 1);\n+\t\t\tts23 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts23,\n+\t\t\t\t\t\t\t\t\t 0),\n+\t\t\t\t\t ts23, 0);\n+\t\t\tts23 = vsetq_lane_u64(*(uint64_t *)vgetq_lane_u64(ts23,\n+\t\t\t\t\t\t\t\t\t 1),\n+\t\t\t\t\t ts23, 1);\n+\t\t\t/* Convert from be to cpu byteorder. */\n+\t\t\tts01 = vrev64q_u8(ts01);\n+\t\t\tts23 = vrev64q_u8(ts23);\n+\t\t\t/* Store timestamp into scalar for later use. */\n+\t\t\tts[0] = vgetq_lane_u64(ts01, 0);\n+\t\t\tts[1] = vgetq_lane_u64(ts01, 1);\n+\t\t\tts[2] = vgetq_lane_u64(ts23, 0);\n+\t\t\tts[3] = vgetq_lane_u64(ts23, 1);\n+\n+\t\t\t/* Store timestamp into dynfield. */\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf0, rxq->tstamp) =\n+\t\t\t\tts[0];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf1, rxq->tstamp) =\n+\t\t\t\tts[1];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf2, rxq->tstamp) =\n+\t\t\t\tts[2];\n+\t\t\t*cnxk_nix_timestamp_dynfield(mbuf3, rxq->tstamp) =\n+\t\t\t\tts[3];\n+\n+\t\t\t/* Generate ptype mask to filter L2 ether timesync */\n+\t\t\tmask = vdupq_n_u32(vgetq_lane_u32(f0, 0));\n+\t\t\tmask = vsetq_lane_u32(vgetq_lane_u32(f1, 0), mask, 1);\n+\t\t\tmask = vsetq_lane_u32(vgetq_lane_u32(f2, 0), mask, 2);\n+\t\t\tmask = vsetq_lane_u32(vgetq_lane_u32(f3, 0), mask, 3);\n+\n+\t\t\t/* Match against L2 ether timesync. */\n+\t\t\tmask = vceqq_u32(mask, ptype);\n+\t\t\t/* Convert from vector from scalar mask */\n+\t\t\tres = vaddvq_u32(vandq_u32(mask, and_mask));\n+\t\t\tres &= 0xF;\n+\n+\t\t\tif (res) {\n+\t\t\t\t/* Fill in the ol_flags for any packets that\n+\t\t\t\t * matched.\n+\t\t\t\t */\n+\t\t\t\tol_flags0 |= ((res & 0x1) ? ts_olf : 0);\n+\t\t\t\tol_flags1 |= ((res & 0x2) ? ts_olf : 0);\n+\t\t\t\tol_flags2 |= ((res & 0x4) ? ts_olf : 0);\n+\t\t\t\tol_flags3 |= ((res & 0x8) ? ts_olf : 0);\n+\n+\t\t\t\t/* Update Rxq timestamp with the latest\n+\t\t\t\t * timestamp.\n+\t\t\t\t */\n+\t\t\t\trxq->tstamp->rx_ready = 1;\n+\t\t\t\trxq->tstamp->rx_tstamp =\n+\t\t\t\t\tts[31 - __builtin_clz(res)];\n+\t\t\t}\n+\t\t}\n+\n \t\t/* Form rearm_data with ol_flags */\n \t\trearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);\n \t\trearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);\n@@ -499,17 +595,17 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t * individual mbufs in scalar mode.\n \t\t\t */\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(0) + 8), mbuf0,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(0) + 8), mbuf0,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(1) + 8), mbuf1,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(1) + 8), mbuf1,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(2) + 8), mbuf2,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(2) + 8), mbuf2,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n-\t\t\t\t\t (cq0 + CQE_SZ(3) + 8), mbuf3,\n-\t\t\t\t\t mbuf_initializer);\n+\t\t\t\t\t\t(cq0 + CQE_SZ(3) + 8), mbuf3,\n+\t\t\t\t\t mbuf_initializer, flags);\n \t\t} else {\n \t\t\t/* Update that no more segments */\n \t\t\tmbuf0->next = NULL;\ndiff --git a/drivers/net/cnxk/cn9k_rx_vec.c b/drivers/net/cnxk/cn9k_rx_vec.c\nindex e61c2225c6..ef5f771ef7 100644\n--- a/drivers/net/cnxk/cn9k_rx_vec.c\n+++ b/drivers/net/cnxk/cn9k_rx_vec.c\n@@ -9,9 +9,6 @@\n \tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_vec_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n \t{ \\\n-\t\t/* TSTMP is not supported by vector */ \\\n-\t\tif ((flags) & NIX_RX_OFFLOAD_TSTAMP_F) \\\n-\t\t\treturn 0; \\\n \t\treturn cn9k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n \t\t\t\t\t\t (flags)); \\\n \t}\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 67b1f42531..4eead03905 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -136,13 +136,12 @@ struct cnxk_eth_qconf {\n };\n \n struct cnxk_timesync_info {\n+\tuint8_t rx_ready;\n+\tuint64_t rx_tstamp;\n \tuint64_t rx_tstamp_dynflag;\n+\tint tstamp_dynfield_offset;\n \trte_iova_t tx_tstamp_iova;\n \tuint64_t *tx_tstamp;\n-\tuint64_t rx_tstamp;\n-\tint tstamp_dynfield_offset;\n-\tuint8_t tx_ready;\n-\tuint8_t rx_ready;\n } __plt_cache_aligned;\n \n struct cnxk_eth_dev {\n@@ -465,13 +464,15 @@ cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,\n \n static __rte_always_inline void\n cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,\n-\t\t\tstruct cnxk_timesync_info *tstamp, bool ts_enable,\n+\t\t\tstruct cnxk_timesync_info *tstamp,\n+\t\t\tconst uint8_t ts_enable, const uint8_t mseg_enable,\n \t\t\tuint64_t *tstamp_ptr)\n {\n-\tif (ts_enable &&\n-\t (mbuf->data_off ==\n-\t RTE_PKTMBUF_HEADROOM + CNXK_NIX_TIMESYNC_RX_OFFSET)) {\n-\t\tmbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;\n+\tif (ts_enable) {\n+\t\tif (!mseg_enable) {\n+\t\t\tmbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;\n+\t\t\tmbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;\n+\t\t}\n \n \t\t/* Reading the rx timestamp inserted by CGX, viz at\n \t\t * starting of the packet data.\n", "prefixes": [ "v2", "02/13" ] }