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GET /api/patches/94338/?format=api
{ "id": 94338, "url": "https://patches.dpdk.org/api/patches/94338/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210617110005.4132926-14-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210617110005.4132926-14-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210617110005.4132926-14-jiawenwu@trustnetic.com", "date": "2021-06-17T10:59:59", "name": "[v6,13/19] net/ngbe: add Tx queue setup and release", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "25ad709feb6b189f7c5368134c00c203e1bc0a78", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210617110005.4132926-14-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 17372, "url": "https://patches.dpdk.org/api/series/17372/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17372", "date": "2021-06-17T10:59:46", "name": "net: ngbe PMD", "version": 6, "mbox": "https://patches.dpdk.org/series/17372/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94338/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94338/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CD021A0C4D;\n\tThu, 17 Jun 2021 12:59:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 788AD41163;\n\tThu, 17 Jun 2021 12:58:36 +0200 (CEST)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by mails.dpdk.org (Postfix) with ESMTP id B4C1F41120\n for <dev@dpdk.org>; Thu, 17 Jun 2021 12:58:34 +0200 (CEST)", "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Thu, 17 Jun 2021 18:58:28 +0800 (CST)" ], "X-QQ-mid": "bizesmtp46t1623927508ta0qakwu", "X-QQ-SSF": "01400000000000D0E000B00A0000000", "X-QQ-FEAT": "pLTyZv4M7ZIJVBS7X/nIn+MpxBMKJv5z1lIrp3vKo9+Es3uN1v8/NOZDfX4+C\n elpsaXkm7bbiI1zHdxJqsrc4qFjHKHKxTCm3EtWQ/MDNdRqBTJJ90ao+bvzkTGaXiUuHI3n\n FwV7UkMkAmEvGl+0n9nv7u73XuUCVLMPeLYWVvCBiFUWD+IKmT+/NWFB/GSmCpXIieW/5oG\n II4uL4keqjSM1RfgEfbX/oe3h/A0PFhbdjfzY+aFiUHyAYWt0U2AZ4r/uZhxpennGJRf/pl\n RZJGQWpy0nNEo13j1UMeGElrjT50b/YnRw3Tp6QeL9vMHm/IHcwBqTPGbepdZQ4Bpu5ygUK\n pzej9zOci98NLoEDxmL6mITChKF4G7y0TWDxMN1", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Thu, 17 Jun 2021 18:59:59 +0800", "Message-Id": "<20210617110005.4132926-14-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210617110005.4132926-1-jiawenwu@trustnetic.com>", "References": "<20210617110005.4132926-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign5", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v6 13/19] net/ngbe: add Tx queue setup and release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Setup device Tx queue and release Tx queue.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/ngbe/ngbe_ethdev.c | 24 ++++\n drivers/net/ngbe/ngbe_ethdev.h | 11 ++\n drivers/net/ngbe/ngbe_rxtx.c | 206 +++++++++++++++++++++++++++++++++\n drivers/net/ngbe/ngbe_rxtx.h | 95 +++++++++++++++\n 4 files changed, 336 insertions(+)", "diff": "diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c\nindex e73606c5f3..d6f93cfe46 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.c\n+++ b/drivers/net/ngbe/ngbe_ethdev.c\n@@ -44,6 +44,14 @@ static const struct rte_eth_desc_lim rx_desc_lim = {\n \t.nb_align = NGBE_RXD_ALIGN,\n };\n \n+static const struct rte_eth_desc_lim tx_desc_lim = {\n+\t.nb_max = NGBE_RING_DESC_MAX,\n+\t.nb_min = NGBE_RING_DESC_MIN,\n+\t.nb_align = NGBE_TXD_ALIGN,\n+\t.nb_seg_max = NGBE_TX_MAX_SEG,\n+\t.nb_mtu_seg_max = NGBE_TX_MAX_SEG,\n+};\n+\n static const struct eth_dev_ops ngbe_eth_dev_ops;\n \n static inline void\n@@ -283,6 +291,7 @@ ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \tstruct ngbe_hw *hw = ngbe_dev_hw(dev);\n \n \tdev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;\n+\tdev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;\n \n \tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n \t\t.rx_thresh = {\n@@ -295,14 +304,27 @@ ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t.offloads = 0,\n \t};\n \n+\tdev_info->default_txconf = (struct rte_eth_txconf) {\n+\t\t.tx_thresh = {\n+\t\t\t.pthresh = NGBE_DEFAULT_TX_PTHRESH,\n+\t\t\t.hthresh = NGBE_DEFAULT_TX_HTHRESH,\n+\t\t\t.wthresh = NGBE_DEFAULT_TX_WTHRESH,\n+\t\t},\n+\t\t.tx_free_thresh = NGBE_DEFAULT_TX_FREE_THRESH,\n+\t\t.offloads = 0,\n+\t};\n+\n \tdev_info->rx_desc_lim = rx_desc_lim;\n+\tdev_info->tx_desc_lim = tx_desc_lim;\n \n \tdev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_100M |\n \t\t\t\tETH_LINK_SPEED_10M;\n \n \t/* Driver-preferred Rx/Tx parameters */\n \tdev_info->default_rxportconf.nb_queues = 1;\n+\tdev_info->default_txportconf.nb_queues = 1;\n \tdev_info->default_rxportconf.ring_size = 256;\n+\tdev_info->default_txportconf.ring_size = 256;\n \n \treturn 0;\n }\n@@ -605,6 +627,8 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = {\n \t.link_update = ngbe_dev_link_update,\n \t.rx_queue_setup = ngbe_dev_rx_queue_setup,\n \t.rx_queue_release = ngbe_dev_rx_queue_release,\n+\t.tx_queue_setup = ngbe_dev_tx_queue_setup,\n+\t.tx_queue_release = ngbe_dev_tx_queue_release,\n };\n \n RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd);\ndiff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h\nindex 6580d288c8..131671c313 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.h\n+++ b/drivers/net/ngbe/ngbe_ethdev.h\n@@ -61,11 +61,17 @@ ngbe_dev_intr(struct rte_eth_dev *dev)\n \n void ngbe_dev_rx_queue_release(void *rxq);\n \n+void ngbe_dev_tx_queue_release(void *txq);\n+\n int ngbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \t\tuint16_t nb_rx_desc, unsigned int socket_id,\n \t\tconst struct rte_eth_rxconf *rx_conf,\n \t\tstruct rte_mempool *mb_pool);\n \n+int ngbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n+\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n+\t\tconst struct rte_eth_txconf *tx_conf);\n+\n int\n ngbe_dev_link_update_share(struct rte_eth_dev *dev,\n \t\tint wait_to_complete);\n@@ -82,4 +88,9 @@ ngbe_dev_link_update_share(struct rte_eth_dev *dev,\n #define NGBE_DEFAULT_RX_HTHRESH 8\n #define NGBE_DEFAULT_RX_WTHRESH 0\n \n+#define NGBE_DEFAULT_TX_FREE_THRESH 32\n+#define NGBE_DEFAULT_TX_PTHRESH 32\n+#define NGBE_DEFAULT_TX_HTHRESH 0\n+#define NGBE_DEFAULT_TX_WTHRESH 0\n+\n #endif /* _NGBE_ETHDEV_H_ */\ndiff --git a/drivers/net/ngbe/ngbe_rxtx.c b/drivers/net/ngbe/ngbe_rxtx.c\nindex df0b64dc01..da9150b2f1 100644\n--- a/drivers/net/ngbe/ngbe_rxtx.c\n+++ b/drivers/net/ngbe/ngbe_rxtx.c\n@@ -15,6 +15,212 @@\n #include \"ngbe_ethdev.h\"\n #include \"ngbe_rxtx.h\"\n \n+/*********************************************************************\n+ *\n+ * Queue management functions\n+ *\n+ **********************************************************************/\n+\n+static void __rte_cold\n+ngbe_tx_queue_release_mbufs(struct ngbe_tx_queue *txq)\n+{\n+\tunsigned int i;\n+\n+\tif (txq->sw_ring != NULL) {\n+\t\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\t\tif (txq->sw_ring[i].mbuf != NULL) {\n+\t\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n+\t\t\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+static void __rte_cold\n+ngbe_tx_free_swring(struct ngbe_tx_queue *txq)\n+{\n+\tif (txq != NULL)\n+\t\trte_free(txq->sw_ring);\n+}\n+\n+static void __rte_cold\n+ngbe_tx_queue_release(struct ngbe_tx_queue *txq)\n+{\n+\tif (txq != NULL) {\n+\t\tif (txq->ops != NULL) {\n+\t\t\ttxq->ops->release_mbufs(txq);\n+\t\t\ttxq->ops->free_swring(txq);\n+\t\t}\n+\t\trte_free(txq);\n+\t}\n+}\n+\n+void __rte_cold\n+ngbe_dev_tx_queue_release(void *txq)\n+{\n+\tngbe_tx_queue_release(txq);\n+}\n+\n+/* (Re)set dynamic ngbe_tx_queue fields to defaults */\n+static void __rte_cold\n+ngbe_reset_tx_queue(struct ngbe_tx_queue *txq)\n+{\n+\tstatic const struct ngbe_tx_desc zeroed_desc = {0};\n+\tstruct ngbe_tx_entry *txe = txq->sw_ring;\n+\tuint16_t prev, i;\n+\n+\t/* Zero out HW ring memory */\n+\tfor (i = 0; i < txq->nb_tx_desc; i++)\n+\t\ttxq->tx_ring[i] = zeroed_desc;\n+\n+\t/* Initialize SW ring entries */\n+\tprev = (uint16_t)(txq->nb_tx_desc - 1);\n+\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\t/* the ring can also be modified by hardware */\n+\t\tvolatile struct ngbe_tx_desc *txd = &txq->tx_ring[i];\n+\n+\t\ttxd->dw3 = rte_cpu_to_le_32(NGBE_TXD_DD);\n+\t\ttxe[i].mbuf = NULL;\n+\t\ttxe[i].last_id = i;\n+\t\ttxe[prev].next_id = i;\n+\t\tprev = i;\n+\t}\n+\n+\ttxq->tx_next_dd = (uint16_t)(txq->tx_free_thresh - 1);\n+\ttxq->tx_tail = 0;\n+\n+\t/*\n+\t * Always allow 1 descriptor to be un-allocated to avoid\n+\t * a H/W race condition\n+\t */\n+\ttxq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);\n+\ttxq->ctx_curr = 0;\n+\tmemset((void *)&txq->ctx_cache, 0,\n+\t\tNGBE_CTX_NUM * sizeof(struct ngbe_ctx_info));\n+}\n+\n+static const struct ngbe_txq_ops def_txq_ops = {\n+\t.release_mbufs = ngbe_tx_queue_release_mbufs,\n+\t.free_swring = ngbe_tx_free_swring,\n+\t.reset = ngbe_reset_tx_queue,\n+};\n+\n+int __rte_cold\n+ngbe_dev_tx_queue_setup(struct rte_eth_dev *dev,\n+\t\t\t uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc,\n+\t\t\t unsigned int socket_id,\n+\t\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tconst struct rte_memzone *tz;\n+\tstruct ngbe_tx_queue *txq;\n+\tstruct ngbe_hw *hw;\n+\tuint16_t tx_free_thresh;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\thw = ngbe_dev_hw(dev);\n+\n+\t/*\n+\t * Validate number of transmit descriptors.\n+\t * It must not exceed hardware maximum, and must be multiple\n+\t * of NGBE_ALIGN.\n+\t */\n+\tif (nb_desc % NGBE_TXD_ALIGN != 0 ||\n+\t nb_desc > NGBE_RING_DESC_MAX ||\n+\t nb_desc < NGBE_RING_DESC_MIN) {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * The Tx descriptor ring will be cleaned after txq->tx_free_thresh\n+\t * descriptors are used or if the number of descriptors required\n+\t * to transmit a packet is greater than the number of free Tx\n+\t * descriptors.\n+\t * One descriptor in the Tx ring is used as a sentinel to avoid a\n+\t * H/W race condition, hence the maximum threshold constraints.\n+\t * When set to zero use default values.\n+\t */\n+\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?\n+\t\t\ttx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);\n+\tif (tx_free_thresh >= (nb_desc - 3)) {\n+\t\tPMD_INIT_LOG(ERR, \"tx_free_thresh must be less than the number of \"\n+\t\t\t \"TX descriptors minus 3. (tx_free_thresh=%u \"\n+\t\t\t \"port=%d queue=%d)\",\n+\t\t\t (unsigned int)tx_free_thresh,\n+\t\t\t (int)dev->data->port_id, (int)queue_idx);\n+\t\treturn -(EINVAL);\n+\t}\n+\n+\tif (nb_desc % tx_free_thresh != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"tx_free_thresh must be a divisor of the \"\n+\t\t\t \"number of Tx descriptors. (tx_free_thresh=%u \"\n+\t\t\t \"port=%d queue=%d)\", (unsigned int)tx_free_thresh,\n+\t\t\t (int)dev->data->port_id, (int)queue_idx);\n+\t\treturn -(EINVAL);\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed... */\n+\tif (dev->data->tx_queues[queue_idx] != NULL) {\n+\t\tngbe_tx_queue_release(dev->data->tx_queues[queue_idx]);\n+\t\tdev->data->tx_queues[queue_idx] = NULL;\n+\t}\n+\n+\t/* First allocate the Tx queue data structure */\n+\ttxq = rte_zmalloc_socket(\"ethdev Tx queue\",\n+\t\t\t\t sizeof(struct ngbe_tx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq == NULL)\n+\t\treturn -ENOMEM;\n+\n+\t/*\n+\t * Allocate Tx ring hardware descriptors. A memzone large enough to\n+\t * handle the maximum ring size is allocated in order to allow for\n+\t * resizing in later calls to the queue setup function.\n+\t */\n+\ttz = rte_eth_dma_zone_reserve(dev, \"tx_ring\", queue_idx,\n+\t\t\tsizeof(struct ngbe_tx_desc) * NGBE_RING_DESC_MAX,\n+\t\t\tNGBE_ALIGN, socket_id);\n+\tif (tz == NULL) {\n+\t\tngbe_tx_queue_release(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxq->nb_tx_desc = nb_desc;\n+\ttxq->tx_free_thresh = tx_free_thresh;\n+\ttxq->pthresh = tx_conf->tx_thresh.pthresh;\n+\ttxq->hthresh = tx_conf->tx_thresh.hthresh;\n+\ttxq->wthresh = tx_conf->tx_thresh.wthresh;\n+\ttxq->queue_id = queue_idx;\n+\ttxq->reg_idx = queue_idx;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->ops = &def_txq_ops;\n+\ttxq->tx_deferred_start = tx_conf->tx_deferred_start;\n+\n+\ttxq->tdt_reg_addr = NGBE_REG_ADDR(hw, NGBE_TXWP(txq->reg_idx));\n+\ttxq->tdc_reg_addr = NGBE_REG_ADDR(hw, NGBE_TXCFG(txq->reg_idx));\n+\n+\ttxq->tx_ring_phys_addr = TMZ_PADDR(tz);\n+\ttxq->tx_ring = (struct ngbe_tx_desc *)TMZ_VADDR(tz);\n+\n+\t/* Allocate software ring */\n+\ttxq->sw_ring = rte_zmalloc_socket(\"txq->sw_ring\",\n+\t\t\t\tsizeof(struct ngbe_tx_entry) * nb_desc,\n+\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq->sw_ring == NULL) {\n+\t\tngbe_tx_queue_release(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\" PRIx64,\n+\t\t txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);\n+\n+\ttxq->ops->reset(txq);\n+\n+\tdev->data->tx_queues[queue_idx] = txq;\n+\n+\treturn 0;\n+}\n+\n /**\n * ngbe_free_sc_cluster - free the not-yet-completed scattered cluster\n *\ndiff --git a/drivers/net/ngbe/ngbe_rxtx.h b/drivers/net/ngbe/ngbe_rxtx.h\nindex 92b9a9fd1b..0f2c185dbf 100644\n--- a/drivers/net/ngbe/ngbe_rxtx.h\n+++ b/drivers/net/ngbe/ngbe_rxtx.h\n@@ -43,11 +43,41 @@ struct ngbe_rx_desc {\n \t} qw1; /* also as r.hdr_addr */\n };\n \n+/*****************************************************************************\n+ * Transmit Descriptor\n+ *****************************************************************************/\n+/**\n+ * Transmit Context Descriptor (NGBE_TXD_TYP=CTXT)\n+ **/\n+struct ngbe_tx_ctx_desc {\n+\trte_le32_t dw0; /* w.vlan_macip_lens */\n+\trte_le32_t dw1; /* w.seqnum_seed */\n+\trte_le32_t dw2; /* w.type_tucmd_mlhl */\n+\trte_le32_t dw3; /* w.mss_l4len_idx */\n+};\n+\n+/* @ngbe_tx_ctx_desc.dw3 */\n+#define NGBE_TXD_DD MS(0, 0x1) /* descriptor done */\n+\n+/**\n+ * Transmit Data Descriptor (NGBE_TXD_TYP=DATA)\n+ **/\n+struct ngbe_tx_desc {\n+\trte_le64_t qw0; /* r.buffer_addr , w.reserved */\n+\trte_le32_t dw2; /* r.cmd_type_len, w.nxtseq_seed */\n+\trte_le32_t dw3; /* r.olinfo_status, w.status */\n+};\n+\n #define RTE_PMD_NGBE_RX_MAX_BURST 32\n \n #define RX_RING_SZ ((NGBE_RING_DESC_MAX + RTE_PMD_NGBE_RX_MAX_BURST) * \\\n \t\t sizeof(struct ngbe_rx_desc))\n \n+#define NGBE_TX_MAX_SEG 40\n+\n+#ifndef DEFAULT_TX_FREE_THRESH\n+#define DEFAULT_TX_FREE_THRESH 32\n+#endif\n \n /**\n * Structure associated with each descriptor of the Rx ring of a Rx queue.\n@@ -60,6 +90,15 @@ struct ngbe_scattered_rx_entry {\n \tstruct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */\n };\n \n+/**\n+ * Structure associated with each descriptor of the Tx ring of a Tx queue.\n+ */\n+struct ngbe_tx_entry {\n+\tstruct rte_mbuf *mbuf; /**< mbuf associated with Tx desc, if any. */\n+\tuint16_t next_id; /**< Index of next descriptor in ring. */\n+\tuint16_t last_id; /**< Index of last scattered descriptor. */\n+};\n+\n /**\n * Structure associated with each Rx queue.\n */\n@@ -93,4 +132,60 @@ struct ngbe_rx_queue {\n \tstruct rte_mbuf *rx_stage[RTE_PMD_NGBE_RX_MAX_BURST * 2];\n };\n \n+/**\n+ * NGBE CTX Constants\n+ */\n+enum ngbe_ctx_num {\n+\tNGBE_CTX_0 = 0, /**< CTX0 */\n+\tNGBE_CTX_1 = 1, /**< CTX1 */\n+\tNGBE_CTX_NUM = 2, /**< CTX NUMBER */\n+};\n+\n+/**\n+ * Structure to check if new context need be built\n+ */\n+struct ngbe_ctx_info {\n+\tuint64_t flags; /**< ol_flags for context build. */\n+};\n+\n+/**\n+ * Structure associated with each Tx queue.\n+ */\n+struct ngbe_tx_queue {\n+\t/** Tx ring virtual address. */\n+\tvolatile struct ngbe_tx_desc *tx_ring;\n+\tuint64_t tx_ring_phys_addr; /**< Tx ring DMA address. */\n+\tstruct ngbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD.*/\n+\tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n+\tvolatile uint32_t *tdc_reg_addr; /**< Address of TDC register. */\n+\tuint16_t nb_tx_desc; /**< number of Tx descriptors. */\n+\tuint16_t tx_tail; /**< current value of TDT reg. */\n+\t/**< Start freeing Tx buffers if there are less free descriptors than\n+\t * this value.\n+\t */\n+\tuint16_t tx_free_thresh;\n+\t/** Index to last Tx descriptor to have been cleaned. */\n+\tuint16_t last_desc_cleaned;\n+\t/** Total number of Tx descriptors ready to be allocated. */\n+\tuint16_t nb_tx_free;\n+\tuint16_t tx_next_dd; /**< next desc to scan for DD bit */\n+\tuint16_t queue_id; /**< Tx queue index. */\n+\tuint16_t reg_idx; /**< Tx queue register index. */\n+\tuint16_t port_id; /**< Device port identifier. */\n+\tuint8_t pthresh; /**< Prefetch threshold register. */\n+\tuint8_t hthresh; /**< Host threshold register. */\n+\tuint8_t wthresh; /**< Write-back threshold reg. */\n+\tuint32_t ctx_curr; /**< Hardware context states. */\n+\t/** Hardware context0 history. */\n+\tstruct ngbe_ctx_info ctx_cache[NGBE_CTX_NUM];\n+\tconst struct ngbe_txq_ops *ops; /**< txq ops */\n+\tuint8_t tx_deferred_start; /**< not in global dev start. */\n+};\n+\n+struct ngbe_txq_ops {\n+\tvoid (*release_mbufs)(struct ngbe_tx_queue *txq);\n+\tvoid (*free_swring)(struct ngbe_tx_queue *txq);\n+\tvoid (*reset)(struct ngbe_tx_queue *txq);\n+};\n+\n #endif /* _NGBE_RXTX_H_ */\n", "prefixes": [ "v6", "13/19" ] }