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GET /api/patches/92796/?format=api
{ "id": 92796, "url": "https://patches.dpdk.org/api/patches/92796/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210505042004.25280-16-bingz@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210505042004.25280-16-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210505042004.25280-16-bingz@nvidia.com", "date": "2021-05-05T04:20:02", "name": "[v2,15/17] net/mlx5: validation of CT item", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "eac40d9073f36062f0dd6b7c3bce51a57079ad61", "submitter": { "id": 1976, "url": "https://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210505042004.25280-16-bingz@nvidia.com/mbox/", "series": [ { "id": 16816, "url": "https://patches.dpdk.org/api/series/16816/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16816", "date": "2021-05-05T04:19:47", "name": "conntrack support in mlx5 PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16816/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92796/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92796/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2A416A034F;\n\tWed, 5 May 2021 06:22:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2E69441117;\n\tWed, 5 May 2021 06:21:25 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2073.outbound.protection.outlook.com [40.107.244.73])\n by mails.dpdk.org (Postfix) with ESMTP id 2DB36410F5\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Wed, 5 May 2021 07:20:02 +0300", "Message-ID": "<20210505042004.25280-16-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210505042004.25280-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>\n <20210505042004.25280-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "f972ffdb-0b55-4c36-5f96-08d90f7d3ca0", "X-MS-TrafficTypeDiagnostic": "BN9PR12MB5049:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN9PR12MB5049C3742FE98EAC6F84B3CDD0599@BN9PR12MB5049.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n J+tK/ucyzUttT3cP2yv+kQwCRzXpBpBK0ym+cjkKWt1CCDdzN4EfYdustOLyriOW67y1tczBCY675+iPw+021K2IyWJ1J9nUDf8BMFEWGYfqUAWN6V7WwCEynqJkKAp/gH/0tLPybY+hFcjkNnkj1koGXQ+UsZYi2wmzAXn0NFt7l0kCQWYb6bfCEeCJxMsCVJtvwqrRV53phgQdYvkFgp50JxA18o5ZUBatl5hn0PKHNUzoEfJPN84oimA5npWx4JHk2Uly0c94h5pEftj7AlbFQddN6lkO67M+gh3kVR0Inp5UXZhlqJPFGfwpdxPgF4XRPZ2xTqYKtlkEZdtUOHkNQ8/oF5EglbYfT6EgVakdQompi4hhiMhfVBihCuKverJBXZoVHhER3qaI9PiW0xZTxNRUTVEwAdebc3aPAxiL9nxEBHy4rTnEjLkDdcXFDj0TbFuwyrX4ayNS1ti+2Qo4XSfHzBciO3x/z+e36674PXInxzEt5X0WAlQM2DaLv6qAYDcBENwWPnamaSqx6sOaSjtQbtFtldvjeVs6ulY1wl+m/sESDoj1FmunfJY2trK9eZpLRDDuQL4OGKjaej+UwNpLXB91c9pgSn+jUadi2Pwg1mLQ8YUQlG17ysv/Su4mZ3CBhRjNX2RjZO9GLeYX4gF7p1PFN591eBIYMIY=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(136003)(376002)(346002)(396003)(46966006)(36840700001)(6286002)(8936002)(478600001)(16526019)(316002)(26005)(426003)(70206006)(8676002)(186003)(7696005)(55016002)(4326008)(70586007)(36860700001)(2616005)(6666004)(83380400001)(336012)(54906003)(36906005)(86362001)(5660300002)(107886003)(2906002)(47076005)(36756003)(82740400003)(356005)(1076003)(7636003)(110136005)(82310400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2021 04:21:21.0988 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f972ffdb-0b55-4c36-5f96-08d90f7d3ca0", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT066.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR12MB5049", "Subject": "[dpdk-dev] [PATCH v2 15/17] net/mlx5: validation of CT item", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The item of ASO connection tracking will be translated into the\nregister value when matching. The validation of this item has no\ndependency on other layers, since the flow including this item\nshould be jumped from another group. All the layers checking was\nalready done in the previous groups. Only the state bits conflict\nshould be checked.\n\nIt is assumed that the flow with CT item will always work on the\nTCP traffic.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 3 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 51 +++++++++++++++++++++++++++++++++\n 2 files changed, 54 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex eb0bb42161..238befa2d4 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -147,6 +147,9 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)\n #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)\n \n+/* Conntrack item. */\n+#define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 34)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex f2a2c609e2..aa0a5acdca 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2598,6 +2598,51 @@ flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,\n \t\t\t\t \"specified range not supported\");\n }\n \n+/*\n+ * Validate ASO CT item.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] item\n+ * Item specification.\n+ * @param[in] item_flags\n+ * Pointer to bit-fields that holds the items detected until now.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t uint64_t *item_flags,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_conntrack *spec = item->spec;\n+\tconst struct rte_flow_item_conntrack *mask = item->mask;\n+\tRTE_SET_USED(dev);\n+\tuint32_t flags;\n+\n+\tif (*item_flags & MLX5_FLOW_LAYER_ASO_CT)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t\t \"Only one CT is supported\");\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_conntrack_mask;\n+\tflags = spec->flags & mask->flags;\n+\tif ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&\n+\t ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||\n+\t (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||\n+\t (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t\t \"Conflict status bits\");\n+\t/* State change also needs to be considered. */\n+\t*item_flags |= MLX5_FLOW_LAYER_ASO_CT;\n+\treturn 0;\n+}\n+\n /**\n * Validate the pop VLAN action.\n *\n@@ -6696,6 +6741,12 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_LAYER_ECPRI;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n+\t\t\tret = flow_dv_validate_item_aso_ct(dev, items,\n+\t\t\t\t\t\t\t &item_flags, error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n", "prefixes": [ "v2", "15/17" ] }