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GET /api/patches/92525/?format=api
{ "id": 92525, "url": "https://patches.dpdk.org/api/patches/92525/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210430135336.2749-14-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210430135336.2749-14-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210430135336.2749-14-pbhagavatula@marvell.com", "date": "2021-04-30T13:53:16", "name": "[v3,13/33] event/cnxk: add SSO HW device operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "71d2a759e4068024ec19692d0f70766efe9c5e0d", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210430135336.2749-14-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16775, "url": "https://patches.dpdk.org/api/series/16775/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16775", "date": "2021-04-30T13:53:03", "name": "Marvell CNXK Event device Driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16775/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92525/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/92525/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B22CDA0546;\n\tFri, 30 Apr 2021 15:55:32 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A2FC64113F;\n\tFri, 30 Apr 2021 15:54:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 979DF41243\n for <dev@dpdk.org>; Fri, 30 Apr 2021 15:54:20 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13UDpJIb016402 for <dev@dpdk.org>; Fri, 30 Apr 2021 06:54:20 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 387rpneavf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 30 Apr 2021 06:54:19 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 30 Apr 2021 06:54:17 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 30 Apr 2021 06:54:17 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 1B3DB3F704E;\n Fri, 30 Apr 2021 06:54:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=sYVuGJXL2H+2XJpmaD8uvZbfy0DSg+uCLJ6tDyLgRWo=;\n b=bzOyzmGzRun92qu4a+CR+r8WkhXwDEHE5fAxsaCTmlcWxnbviL255Yer4/T2+AQ4kVGX\n 0Iu4hOMp9NhuKBCwibwJpeDgGMzf7ILL1fNW3UpV2SSes8q4Jea7pBG6c92ymxKjyGds\n hctu8RaZ70K9R7exVu2RUfAh9xHRdoHgvHpTHjVn4l+/I9tij18hbLXwM2cj49TcQlPU\n lYgHSQQ4SaZa4q1HjoRmmX7rkFbdslUXWf7gSYzn4kr3yIk44TG64K8prSMnnCW1kEUt\n yIxYp2PL4WSVBUfvpKzNqlDy9gyWbg+2VYLtxCGqM5khTV4xokU6sK2TGIlG64Riw6ZU 9g==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 30 Apr 2021 19:23:16 +0530", "Message-ID": "<20210430135336.2749-14-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210430135336.2749-1-pbhagavatula@marvell.com>", "References": "<20210426174441.2302-1-pbhagavatula@marvell.com>\n <20210430135336.2749-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "G2Aa3qN91yrhoMbSesYNVieLW4AawL8m", "X-Proofpoint-ORIG-GUID": "G2Aa3qN91yrhoMbSesYNVieLW4AawL8m", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-30_08:2021-04-30,\n 2021-04-30 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 13/33] event/cnxk: add SSO HW device operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd SSO HW device operations used for enqueue/dequeue.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_worker.c | 7 +\n drivers/event/cnxk/cn10k_worker.h | 151 +++++++++++++++++\n drivers/event/cnxk/cn9k_worker.c | 7 +\n drivers/event/cnxk/cn9k_worker.h | 249 +++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 10 ++\n drivers/event/cnxk/cnxk_worker.h | 101 ++++++++++++\n drivers/event/cnxk/meson.build | 4 +-\n 7 files changed, 528 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/cnxk/cn10k_worker.c\n create mode 100644 drivers/event/cnxk/cn10k_worker.h\n create mode 100644 drivers/event/cnxk/cn9k_worker.c\n create mode 100644 drivers/event/cnxk/cn9k_worker.h\n create mode 100644 drivers/event/cnxk/cnxk_worker.h", "diff": "diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nnew file mode 100644\nindex 000000000..63b587301\n--- /dev/null\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -0,0 +1,7 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nnew file mode 100644\nindex 000000000..04517055d\n--- /dev/null\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -0,0 +1,151 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __CN10K_WORKER_H__\n+#define __CN10K_WORKER_H__\n+\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+/* SSO Operations */\n+\n+static __rte_always_inline uint8_t\n+cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\tconst uint64_t event_ptr = ev->u64;\n+\tconst uint16_t grp = ev->queue_id;\n+\n+\trte_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+\tif (ws->xaq_lmt <= *ws->fc_mem)\n+\t\treturn 0;\n+\n+\tcnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]);\n+\treturn 1;\n+}\n+\n+static __rte_always_inline void\n+cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\tconst uint8_t cur_tt = CNXK_TT_FROM_TAG(plt_read64(ws->tag_wqe_op));\n+\n+\t/* CNXK model\n+\t * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED\n+\t *\n+\t * SSO_TT_ORDERED norm norm untag\n+\t * SSO_TT_ATOMIC norm norm\t\t untag\n+\t * SSO_TT_UNTAGGED norm norm NOOP\n+\t */\n+\n+\tif (new_tt == SSO_TT_UNTAGGED) {\n+\t\tif (cur_tt != SSO_TT_UNTAGGED)\n+\t\t\tcnxk_sso_hws_swtag_untag(ws->swtag_untag_op);\n+\t} else {\n+\t\tcnxk_sso_hws_swtag_norm(tag, new_tt, ws->swtag_norm_op);\n+\t}\n+\tws->swtag_req = 1;\n+}\n+\n+static __rte_always_inline void\n+cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev,\n+\t\t\tconst uint16_t grp)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\n+\tplt_write64(ev->u64, ws->updt_wqe_op);\n+\tcnxk_sso_hws_swtag_desched(tag, new_tt, grp, ws->swtag_desched_op);\n+}\n+\n+static __rte_always_inline void\n+cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,\n+\t\t\t const struct rte_event *ev)\n+{\n+\tconst uint8_t grp = ev->queue_id;\n+\n+\t/* Group hasn't changed, Use SWTAG to forward the event */\n+\tif (CNXK_GRP_FROM_TAG(plt_read64(ws->tag_wqe_op)) == grp)\n+\t\tcn10k_sso_hws_fwd_swtag(ws, ev);\n+\telse\n+\t\t/*\n+\t\t * Group has been changed for group based work pipelining,\n+\t\t * Use deschedule/add_work operation to transfer the event to\n+\t\t * new group/core\n+\t\t */\n+\t\tcn10k_sso_hws_fwd_group(ws, ev, grp);\n+}\n+\n+static __rte_always_inline uint16_t\n+cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev)\n+{\n+\tunion {\n+\t\t__uint128_t get_work;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\n+\tgw.get_work = ws->gw_wdata;\n+#if defined(RTE_ARCH_ARM64) && !defined(__clang__)\n+\tasm volatile(\n+\t\tPLT_CPU_FEATURE_PREAMBLE\n+\t\t\"caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\\n\"\n+\t\t: [wdata] \"+r\"(gw.get_work)\n+\t\t: [gw_loc] \"r\"(ws->getwrk_op)\n+\t\t: \"memory\");\n+#else\n+\tplt_write64(gw.u64[0], ws->getwrk_op);\n+\tdo {\n+\t\troc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op);\n+\t} while (gw.u64[0] & BIT_ULL(63));\n+#endif\n+\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n+\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n+\t\t (gw.u64[0] & 0xffffffff);\n+\n+\tev->event = gw.u64[0];\n+\tev->u64 = gw.u64[1];\n+\n+\treturn !!gw.u64[1];\n+}\n+\n+/* Used in cleaning up workslot. */\n+static __rte_always_inline uint16_t\n+cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n+{\n+\tunion {\n+\t\t__uint128_t get_work;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\n+#ifdef RTE_ARCH_ARM64\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"\t\tldp %[tag], %[wqp], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\ttbz %[tag], 63, done%=\t\t\t\\n\"\n+\t\t \"\t\tsevl\t\t\t\t\t\\n\"\n+\t\t \"rty%=:\twfe\t\t\t\t\t\\n\"\n+\t\t \"\t\tldp %[tag], %[wqp], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\t\\n\"\n+\t\t \"done%=:\tdmb ld\t\t\t\t\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t : [tag_loc] \"r\"(ws->tag_wqe_op)\n+\t\t : \"memory\");\n+#else\n+\tdo {\n+\t\troc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op);\n+\t} while (gw.u64[0] & BIT_ULL(63));\n+#endif\n+\n+\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n+\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n+\t\t (gw.u64[0] & 0xffffffff);\n+\n+\tev->event = gw.u64[0];\n+\tev->u64 = gw.u64[1];\n+\n+\treturn !!gw.u64[1];\n+}\n+\n+#endif\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nnew file mode 100644\nindex 000000000..836914163\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -0,0 +1,7 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+\n+#include \"cn9k_worker.h\"\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nnew file mode 100644\nindex 000000000..85be742c1\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -0,0 +1,249 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __CN9K_WORKER_H__\n+#define __CN9K_WORKER_H__\n+\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+/* SSO Operations */\n+\n+static __rte_always_inline uint8_t\n+cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\tconst uint64_t event_ptr = ev->u64;\n+\tconst uint16_t grp = ev->queue_id;\n+\n+\trte_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+\tif (ws->xaq_lmt <= *ws->fc_mem)\n+\t\treturn 0;\n+\n+\tcnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]);\n+\treturn 1;\n+}\n+\n+static __rte_always_inline void\n+cn9k_sso_hws_fwd_swtag(struct cn9k_sso_hws_state *vws,\n+\t\t const struct rte_event *ev)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\tconst uint8_t cur_tt = CNXK_TT_FROM_TAG(plt_read64(vws->tag_op));\n+\n+\t/* CNXK model\n+\t * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED\n+\t *\n+\t * SSO_TT_ORDERED norm norm untag\n+\t * SSO_TT_ATOMIC norm norm\t\t untag\n+\t * SSO_TT_UNTAGGED norm norm NOOP\n+\t */\n+\n+\tif (new_tt == SSO_TT_UNTAGGED) {\n+\t\tif (cur_tt != SSO_TT_UNTAGGED)\n+\t\t\tcnxk_sso_hws_swtag_untag(\n+\t\t\t\tCN9K_SSOW_GET_BASE_ADDR(vws->getwrk_op) +\n+\t\t\t\tSSOW_LF_GWS_OP_SWTAG_UNTAG);\n+\t} else {\n+\t\tcnxk_sso_hws_swtag_norm(tag, new_tt, vws->swtag_norm_op);\n+\t}\n+}\n+\n+static __rte_always_inline void\n+cn9k_sso_hws_fwd_group(struct cn9k_sso_hws_state *ws,\n+\t\t const struct rte_event *ev, const uint16_t grp)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\n+\tplt_write64(ev->u64, CN9K_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n+\t\t\t\t SSOW_LF_GWS_OP_UPD_WQP_GRP1);\n+\tcnxk_sso_hws_swtag_desched(tag, new_tt, grp, ws->swtag_desched_op);\n+}\n+\n+static __rte_always_inline void\n+cn9k_sso_hws_forward_event(struct cn9k_sso_hws *ws, const struct rte_event *ev)\n+{\n+\tconst uint8_t grp = ev->queue_id;\n+\n+\t/* Group hasn't changed, Use SWTAG to forward the event */\n+\tif (CNXK_GRP_FROM_TAG(plt_read64(ws->tag_op)) == grp) {\n+\t\tcn9k_sso_hws_fwd_swtag((struct cn9k_sso_hws_state *)ws, ev);\n+\t\tws->swtag_req = 1;\n+\t} else {\n+\t\t/*\n+\t\t * Group has been changed for group based work pipelining,\n+\t\t * Use deschedule/add_work operation to transfer the event to\n+\t\t * new group/core\n+\t\t */\n+\t\tcn9k_sso_hws_fwd_group((struct cn9k_sso_hws_state *)ws, ev,\n+\t\t\t\t grp);\n+\t}\n+}\n+\n+/* Dual ws ops. */\n+\n+static __rte_always_inline uint8_t\n+cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws,\n+\t\t\t const struct rte_event *ev)\n+{\n+\tconst uint32_t tag = (uint32_t)ev->event;\n+\tconst uint8_t new_tt = ev->sched_type;\n+\tconst uint64_t event_ptr = ev->u64;\n+\tconst uint16_t grp = ev->queue_id;\n+\n+\trte_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+\tif (dws->xaq_lmt <= *dws->fc_mem)\n+\t\treturn 0;\n+\n+\tcnxk_sso_hws_add_work(event_ptr, tag, new_tt, dws->grps_base[grp]);\n+\treturn 1;\n+}\n+\n+static __rte_always_inline void\n+cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws,\n+\t\t\t\tstruct cn9k_sso_hws_state *vws,\n+\t\t\t\tconst struct rte_event *ev)\n+{\n+\tconst uint8_t grp = ev->queue_id;\n+\n+\t/* Group hasn't changed, Use SWTAG to forward the event */\n+\tif (CNXK_GRP_FROM_TAG(plt_read64(vws->tag_op)) == grp) {\n+\t\tcn9k_sso_hws_fwd_swtag(vws, ev);\n+\t\tdws->swtag_req = 1;\n+\t} else {\n+\t\t/*\n+\t\t * Group has been changed for group based work pipelining,\n+\t\t * Use deschedule/add_work operation to transfer the event to\n+\t\t * new group/core\n+\t\t */\n+\t\tcn9k_sso_hws_fwd_group(vws, ev, grp);\n+\t}\n+}\n+\n+static __rte_always_inline uint16_t\n+cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n+\t\t\t struct cn9k_sso_hws_state *ws_pair,\n+\t\t\t struct rte_event *ev)\n+{\n+\tconst uint64_t set_gw = BIT_ULL(16) | 1;\n+\tunion {\n+\t\t__uint128_t get_work;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\n+#ifdef RTE_ARCH_ARM64\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"rty%=:\t\t\t\t\t\\n\"\n+\t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n+\t\t \"done%=:\tstr %[gw], [%[pong]]\t\t\\n\"\n+\t\t \"\t\tdmb ld\t\t\t\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op),\n+\t\t [gw] \"r\"(set_gw), [pong] \"r\"(ws_pair->getwrk_op));\n+#else\n+\tgw.u64[0] = plt_read64(ws->tag_op);\n+\twhile ((BIT_ULL(63)) & gw.u64[0])\n+\t\tgw.u64[0] = plt_read64(ws->tag_op);\n+\tgw.u64[1] = plt_read64(ws->wqp_op);\n+\tplt_write64(set_gw, ws_pair->getwrk_op);\n+#endif\n+\n+\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n+\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n+\t\t (gw.u64[0] & 0xffffffff);\n+\n+\tev->event = gw.u64[0];\n+\tev->u64 = gw.u64[1];\n+\n+\treturn !!gw.u64[1];\n+}\n+\n+static __rte_always_inline uint16_t\n+cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n+{\n+\tunion {\n+\t\t__uint128_t get_work;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\n+\tplt_write64(BIT_ULL(16) | /* wait for work. */\n+\t\t\t 1,\t /* Use Mask set 0. */\n+\t\t ws->getwrk_op);\n+#ifdef RTE_ARCH_ARM64\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t \"\t\ttbz %[tag], 63, done%=\t\t\\n\"\n+\t\t \"\t\tsevl\t\t\t\t\\n\"\n+\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n+\t\t \"done%=:\tdmb ld\t\t\t\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op));\n+#else\n+\tgw.u64[0] = plt_read64(ws->tag_op);\n+\twhile ((BIT_ULL(63)) & gw.u64[0])\n+\t\tgw.u64[0] = plt_read64(ws->tag_op);\n+\n+\tgw.u64[1] = plt_read64(ws->wqp_op);\n+#endif\n+\n+\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n+\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n+\t\t (gw.u64[0] & 0xffffffff);\n+\n+\tev->event = gw.u64[0];\n+\tev->u64 = gw.u64[1];\n+\n+\treturn !!gw.u64[1];\n+}\n+\n+/* Used in cleaning up workslot. */\n+static __rte_always_inline uint16_t\n+cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n+{\n+\tunion {\n+\t\t__uint128_t get_work;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\n+#ifdef RTE_ARCH_ARM64\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t \"\t\ttbz %[tag], 63, done%=\t\t\\n\"\n+\t\t \"\t\tsevl\t\t\t\t\\n\"\n+\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n+\t\t \"done%=:\tdmb ld\t\t\t\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op));\n+#else\n+\tgw.u64[0] = plt_read64(ws->tag_op);\n+\twhile ((BIT_ULL(63)) & gw.u64[0])\n+\t\tgw.u64[0] = plt_read64(ws->tag_op);\n+\n+\tgw.u64[1] = plt_read64(ws->wqp_op);\n+#endif\n+\n+\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n+\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n+\t\t (gw.u64[0] & 0xffffffff);\n+\n+\tev->event = gw.u64[0];\n+\tev->u64 = gw.u64[1];\n+\n+\treturn !!gw.u64[1];\n+}\n+\n+#endif\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 437cdf3db..0a3ab71e4 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -29,6 +29,16 @@\n #define CNXK_SSO_XAQ_CACHE_CNT (0x7)\n #define CNXK_SSO_XAQ_SLACK (8)\n \n+#define CNXK_TT_FROM_TAG(x)\t (((x) >> 32) & SSO_TT_EMPTY)\n+#define CNXK_TT_FROM_EVENT(x)\t (((x) >> 38) & SSO_TT_EMPTY)\n+#define CNXK_EVENT_TYPE_FROM_TAG(x) (((x) >> 28) & 0xf)\n+#define CNXK_SUB_EVENT_FROM_TAG(x) (((x) >> 20) & 0xff)\n+#define CNXK_CLR_SUB_EVENT(x)\t (~(0xffu << 20) & x)\n+#define CNXK_GRP_FROM_TAG(x)\t (((x) >> 36) & 0x3ff)\n+#define CNXK_SWTAG_PEND(x)\t (BIT_ULL(62) & x)\n+\n+#define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0)\n+\n #define CN10K_GW_MODE_NONE 0\n #define CN10K_GW_MODE_PREF 1\n #define CN10K_GW_MODE_PREF_WFE 2\ndiff --git a/drivers/event/cnxk/cnxk_worker.h b/drivers/event/cnxk/cnxk_worker.h\nnew file mode 100644\nindex 000000000..4eb46ae16\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_worker.h\n@@ -0,0 +1,101 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __CNXK_WORKER_H__\n+#define __CNXK_WORKER_H__\n+\n+#include \"cnxk_eventdev.h\"\n+\n+/* SSO Operations */\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_add_work(const uint64_t event_ptr, const uint32_t tag,\n+\t\t const uint8_t new_tt, const uintptr_t grp_base)\n+{\n+\tuint64_t add_work0;\n+\n+\tadd_work0 = tag | ((uint64_t)(new_tt) << 32);\n+\troc_store_pair(add_work0, event_ptr, grp_base);\n+}\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_swtag_desched(uint32_t tag, uint8_t new_tt, uint16_t grp,\n+\t\t\t uintptr_t swtag_desched_op)\n+{\n+\tuint64_t val;\n+\n+\tval = tag | ((uint64_t)(new_tt & 0x3) << 32) | ((uint64_t)grp << 34);\n+\t__atomic_store_n((uint64_t *)swtag_desched_op, val, __ATOMIC_RELEASE);\n+}\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_swtag_norm(uint32_t tag, uint8_t new_tt, uintptr_t swtag_norm_op)\n+{\n+\tuint64_t val;\n+\n+\tval = tag | ((uint64_t)(new_tt & 0x3) << 32);\n+\tplt_write64(val, swtag_norm_op);\n+}\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_swtag_untag(uintptr_t swtag_untag_op)\n+{\n+\tplt_write64(0, swtag_untag_op);\n+}\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_swtag_flush(uint64_t tag_op, uint64_t flush_op)\n+{\n+\tif (CNXK_TT_FROM_TAG(plt_read64(tag_op)) == SSO_TT_EMPTY)\n+\t\treturn;\n+\tplt_write64(0, flush_op);\n+}\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_swtag_wait(uintptr_t tag_op)\n+{\n+#ifdef RTE_ARCH_ARM64\n+\tuint64_t swtp;\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n+\t\t \"\t\ttbz %[swtb], 62, done%=\t\t\\n\"\n+\t\t \"\t\tsevl\t\t\t\t\\n\"\n+\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n+\t\t \"\t\ttbnz %[swtb], 62, rty%=\t\t\\n\"\n+\t\t \"done%=:\t\t\t\t\t\\n\"\n+\t\t : [swtb] \"=&r\"(swtp)\n+\t\t : [swtp_loc] \"r\"(tag_op));\n+#else\n+\t/* Wait for the SWTAG/SWTAG_FULL operation */\n+\twhile (plt_read64(tag_op) & BIT_ULL(62))\n+\t\t;\n+#endif\n+}\n+\n+static __rte_always_inline void\n+cnxk_sso_hws_head_wait(uintptr_t tag_op)\n+{\n+#ifdef RTE_ARCH_ARM64\n+\tuint64_t swtp;\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n+\t\t \"\t\ttbz %[swtb], 35, done%=\t\t\\n\"\n+\t\t \"\t\tsevl\t\t\t\t\\n\"\n+\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n+\t\t \"\t\ttbnz %[swtb], 35, rty%=\t\t\\n\"\n+\t\t \"done%=:\t\t\t\t\t\\n\"\n+\t\t : [swtb] \"=&r\"(swtp)\n+\t\t : [swtp_loc] \"r\"(tag_op));\n+#else\n+\t/* Wait for the SWTAG/SWTAG_FULL operation */\n+\twhile (plt_read64(tag_op) & BIT_ULL(35))\n+\t\t;\n+#endif\n+}\n+\n+#endif\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex 888aeb064..3617d707b 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -8,7 +8,9 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n subdir_done()\n endif\n \n-sources = files('cn10k_eventdev.c',\n+sources = files('cn10k_worker.c',\n+ 'cn10k_eventdev.c',\n+ 'cn9k_worker.c',\n 'cn9k_eventdev.c',\n 'cnxk_eventdev.c',\n )\n", "prefixes": [ "v3", "13/33" ] }