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GET /api/patches/92445/?format=api
{ "id": 92445, "url": "https://patches.dpdk.org/api/patches/92445/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-14-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210429154712.2820159-14-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210429154712.2820159-14-matan@nvidia.com", "date": "2021-04-29T15:47:10", "name": "[v2,13/15] crypto/mlx5: add enqueue and dequeue operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6d155ea18ca102f38b8457a2a1af2052ab830f83", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-14-matan@nvidia.com/mbox/", "series": [ { "id": 16765, "url": "https://patches.dpdk.org/api/series/16765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16765", "date": "2021-04-29T15:46:57", "name": "drivers: introduce mlx5 crypto PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16765/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92445/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92445/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C234FA0547;\n\tThu, 29 Apr 2021 17:49:06 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 26AA44135E;\n\tThu, 29 Apr 2021 17:48:55 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2067.outbound.protection.outlook.com [40.107.243.67])\n by mails.dpdk.org (Postfix) with ESMTP id 4C3664123F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>", "Date": "Thu, 29 Apr 2021 18:47:10 +0300", "Message-ID": "<20210429154712.2820159-14-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210429154712.2820159-1-matan@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210429154712.2820159-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5ebc0d9d-43a6-4c89-48ed-08d90b264940", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1150:", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB1150C0CFD539D85B3588BA87DF5F9@MWHPR12MB1150.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:252;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n MCg/0bV4Ube0m48Vp9GBEdLVC5ctnjkKw0m5gSRu8RBNv4c+fXqC4/9YuyFSnUUGJuzZgV3wfVmE4QsS69Lozt0fYC8LrEihtK9Mvr9eVe9hNX/hMWw5X13oeaNWYXSmWkC3fyvqEyCjzF4b2aoN7gkrf80Cy6TXx3Np/441WF8Y5I36PsXzYJNsFN/2vR+RVNMX4motRCIGA/yGTYdeWnOtnnqoZDliMVGTP7Oxaf+Qan4Y7e8Gx3CFarZ/lEljO3X5DH+ZL4xWOnx0SAzMe4nqhsUljF5dNGJWWBxCrsxCH/7jtZAq6vIH+K4OTkIzNDNJ58I4FGfHkMK2gsi/HkcKRoCbXSsx5TVGLs9aV1ADdun3yCOxeR2y+/Mbt0/lDfSp5bc+hxTmsfA9d0+95XEmEldd4M58FIan5vVQTNjjhi9bKoTdqYXeE1gbj3czPZj49CBJcM8iigh+yorPRn5HwJ53vMq6xieEEzsBHFc6M+gM362XEyH9bFxKaZyv1hsNNPMRDDjCKGHq977OBA+FASpvymGLrV2jCOQsZKus0vVEudM2EKn45Y01n2k6BLjJHzbX7OofY68WfjTbInb5BfgnONrRL6VWYypCW0XsF+5Ke837zg16di/9UkfHND0WXrxdm4CdtnyUi29ZsRiOO8Inwu8/dhsD3XRf6kc=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(39860400002)(346002)(396003)(136003)(36840700001)(46966006)(86362001)(2616005)(82310400003)(478600001)(426003)(26005)(316002)(55016002)(6666004)(16526019)(70206006)(2906002)(70586007)(36906005)(5660300002)(186003)(7696005)(107886003)(6916009)(6286002)(1076003)(8676002)(36860700001)(356005)(36756003)(7636003)(82740400003)(336012)(4326008)(83380400001)(54906003)(47076005)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2021 15:48:51.3999 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5ebc0d9d-43a6-4c89-48ed-08d90b264940", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT041.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1150", "Subject": "[dpdk-dev] [PATCH v2 13/15] crypto/mlx5: add enqueue and dequeue\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nThe crypto operations are done with the WQE set which contains\none UMR WQE and one rdma write WQE. Most segments of the WQE\nset are initialized properly during queue setup, only limited\nsegments are initialized according to the crypto detail in the\ndatapath process.\n\nThis commit adds the enquue and dequeue operations and updates\nthe WQE set segments accordingly.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 243 +++++++++++++++++++++++++++++-\n drivers/crypto/mlx5/mlx5_crypto.h | 3 +\n 2 files changed, 241 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex e8f68eb115..08a8c1e925 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -268,6 +268,239 @@ mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)\n \treturn 0;\n }\n \n+static __rte_noinline uint32_t\n+mlx5_crypto_get_block_size(struct rte_crypto_op *op)\n+{\n+\tuint32_t bl = op->sym->cipher.data.length;\n+\n+\tswitch (bl) {\n+\tcase (1 << 20):\n+\t\treturn RTE_BE32(MLX5_BLOCK_SIZE_1MB << MLX5_BLOCK_SIZE_OFFSET);\n+\tcase (1 << 12):\n+\t\treturn RTE_BE32(MLX5_BLOCK_SIZE_4096B <<\n+\t\t\t\tMLX5_BLOCK_SIZE_OFFSET);\n+\tcase (1 << 9):\n+\t\treturn RTE_BE32(MLX5_BLOCK_SIZE_512B << MLX5_BLOCK_SIZE_OFFSET);\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Unknown block size: %u.\", bl);\n+\t\treturn UINT32_MAX;\n+\t}\n+}\n+\n+static __rte_always_inline uint32_t\n+mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,\n+\t\t struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm,\n+\t\t uint32_t offset, uint32_t *remain)\n+{\n+\tuint32_t data_len = (rte_pktmbuf_data_len(mbuf) - offset);\n+\tuintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);\n+\n+\tif (data_len > *remain)\n+\t\tdata_len = *remain;\n+\t*remain -= data_len;\n+\tklm->bcount = rte_cpu_to_be_32(data_len);\n+\tklm->pbuf = rte_cpu_to_be_64(addr);\n+\tklm->lkey = mlx5_mr_addr2mr_bh(priv->pd, 0,\n+\t\t&priv->mr_scache, &qp->mr_ctrl, addr,\n+\t\t!!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\treturn klm->lkey;\n+\n+}\n+\n+static __rte_always_inline uint32_t\n+mlx5_crypto_klms_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,\n+\t\t struct rte_crypto_op *op, struct rte_mbuf *mbuf,\n+\t\t struct mlx5_wqe_dseg *klm)\n+{\n+\tuint32_t remain_len = op->sym->cipher.data.length;\n+\tuint32_t nb_segs = mbuf->nb_segs;\n+\tuint32_t klm_n = 1;\n+\n+\t/* First mbuf needs to take the cipher offset. */\n+\tif (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, klm,\n+\t\t op->sym->cipher.data.offset, &remain_len) == UINT32_MAX)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn 0;\n+\t}\n+\twhile (remain_len) {\n+\t\tnb_segs--;\n+\t\tmbuf = mbuf->next;\n+\t\tif (unlikely(mbuf == NULL || nb_segs == 0)) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tif (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, klm, 0,\n+\t\t\t\t\t\t &remain_len) == UINT32_MAX)) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tklm_n++;\n+\t}\n+\treturn klm_n;\n+}\n+\n+static __rte_always_inline int\n+mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv,\n+\t\t\t struct mlx5_crypto_qp *qp,\n+\t\t\t struct rte_crypto_op *op,\n+\t\t\t struct mlx5_umr_wqe *umr)\n+{\n+\tstruct mlx5_crypto_session *sess = get_sym_session_private_data\n+\t\t\t\t(op->sym->session, mlx5_crypto_driver_id);\n+\tstruct mlx5_wqe_cseg *cseg = &umr->ctr;\n+\tstruct mlx5_wqe_mkey_cseg *mkc = &umr->mkc;\n+\tstruct mlx5_wqe_dseg *klms = &umr->kseg[0];\n+\tstruct mlx5_wqe_umr_bsf_seg *bsf = ((struct mlx5_wqe_umr_bsf_seg *)\n+\t\t\t\t RTE_PTR_ADD(umr, priv->umr_wqe_size)) - 1;\n+\tuint16_t nop_ds;\n+\t/* Set UMR WQE. */\n+\tuint32_t klm_n = mlx5_crypto_klms_set(priv, qp, op,\n+\t\t\top->sym->m_dst ? op->sym->m_dst : op->sym->m_src, klms);\n+\n+\tif (unlikely(klm_n == 0))\n+\t\treturn 0;\n+\tbsf->bs_bpt_eo_es = sess->bs_bpt_eo_es;\n+\tif (unlikely(!sess->bsp_res)) {\n+\t\tbsf->bsp_res = mlx5_crypto_get_block_size(op);\n+\t\tif (unlikely(bsf->bsp_res == UINT32_MAX)) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\t\treturn 0;\n+\t\t}\n+\t} else {\n+\t\tbsf->bsp_res = sess->bsp_res;\n+\t}\n+\tbsf->raw_data_size = rte_cpu_to_be_32(op->sym->cipher.data.length);\n+\tmemcpy(bsf->xts_initial_tweak,\n+\t rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv_offset), 16);\n+\tbsf->res_dp = sess->dek_id;\n+\tcseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | MLX5_OPCODE_UMR);\n+\tmkc->len = rte_cpu_to_be_64(op->sym->cipher.data.length);\n+\t/* Set RDMA_WRITE WQE. */\n+\tcseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size);\n+\tklms = RTE_PTR_ADD(cseg, sizeof(struct mlx5_rdma_write_wqe));\n+\tcseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |\n+\t\t\t\t\tMLX5_OPCODE_RDMA_WRITE);\n+\tif (op->sym->m_dst != op->sym->m_src) {\n+\t\tklm_n = mlx5_crypto_klms_set(priv, qp, op, op->sym->m_src,\n+\t\t\t\t\t klms);\n+\t\tif (unlikely(klm_n == 0))\n+\t\t\treturn 0;\n+\t} else {\n+\t\tmemcpy(klms, &umr->kseg[0], sizeof(*klms) * klm_n);\n+\t}\n+\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | (2 + klm_n));\n+\tqp->db_pi += priv->wqe_stride;\n+\t/* Set NOP WQE if needed. */\n+\tklm_n = RTE_ALIGN(klm_n + 2, 4) - 2;\n+\tnop_ds = priv->max_rdmaw_klm_n - klm_n;\n+\tif (nop_ds) {\n+\t\tcseg = (struct mlx5_wqe_cseg *)(klms + klm_n);\n+\t\tcseg->opcode = rte_cpu_to_be_32(((qp->db_pi - (nop_ds >> 2)) <<\n+\t\t\t\t\t\t 8) | MLX5_OPCODE_NOP);\n+\t\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | nop_ds);\n+\t}\n+\tqp->wqe = (uint8_t *)cseg;\n+\treturn 1;\n+}\n+\n+static __rte_always_inline void\n+mlx5_crypto_uar_write(uint64_t val, struct mlx5_crypto_priv *priv)\n+{\n+#ifdef RTE_ARCH_64\n+\t*priv->uar_addr = val;\n+#else /* !RTE_ARCH_64 */\n+\trte_spinlock_lock(&priv->uar32_sl);\n+\t*(volatile uint32_t *)priv->uar_addr = val;\n+\trte_io_wmb();\n+\t*((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;\n+\trte_spinlock_unlock(&priv->uar32_sl);\n+#endif\n+}\n+\n+static uint16_t\n+mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,\n+\t\t\t uint16_t nb_ops)\n+{\n+\tstruct mlx5_crypto_qp *qp = queue_pair;\n+\tstruct mlx5_crypto_priv *priv = qp->priv;\n+\tstruct mlx5_umr_wqe *umr;\n+\tstruct rte_crypto_op *op;\n+\tuint16_t mask = qp->entries_n - 1;\n+\tuint16_t remain = qp->entries_n - (qp->pi - qp->ci);\n+\n+\tif (remain < nb_ops)\n+\t\tnb_ops = remain;\n+\telse\n+\t\tremain = nb_ops;\n+\tif (unlikely(remain == 0))\n+\t\treturn 0;\n+\tdo {\n+\t\top = *ops++;\n+\t\tumr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);\n+\t\tif (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0))\n+\t\t\tbreak;\n+\t\tqp->ops[qp->pi] = op;\n+\t\tqp->pi = (qp->pi + 1) & mask;\n+\t} while (--remain);\n+\trte_io_wmb();\n+\tqp->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);\n+\trte_wmb();\n+\tmlx5_crypto_uar_write(*(volatile uint64_t *)qp->wqe, qp->priv);\n+\trte_wmb();\n+\treturn nb_ops;\n+}\n+\n+static __rte_noinline void\n+mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op)\n+{\n+\tconst uint32_t idx = qp->ci & (qp->entries_n - 1);\n+\tvolatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)\n+\t\t\t\t\t\t\t&qp->cq_obj.cqes[idx];\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\tDRV_LOG(ERR, \"CQE ERR:%x.\\n\", rte_be_to_cpu_32(cqe->syndrome));\n+}\n+\n+static uint16_t\n+mlx5_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,\n+\t\t\t uint16_t nb_ops)\n+{\n+\tstruct mlx5_crypto_qp *qp = queue_pair;\n+\tvolatile struct mlx5_cqe *restrict cqe;\n+\tstruct rte_crypto_op *restrict op;\n+\tconst unsigned int cq_size = qp->entries_n;\n+\tconst unsigned int mask = cq_size - 1;\n+\tuint32_t idx;\n+\tuint32_t next_idx = qp->ci & mask;\n+\tconst uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);\n+\tuint16_t i = 0;\n+\tint ret;\n+\n+\tif (unlikely(max == 0))\n+\t\treturn 0;\n+\tdo {\n+\t\tidx = next_idx;\n+\t\tnext_idx = (qp->ci + 1) & mask;\n+\t\top = qp->ops[idx];\n+\t\tcqe = &qp->cq_obj.cqes[idx];\n+\t\tret = check_cqe(cqe, cq_size, qp->ci);\n+\t\trte_io_rmb();\n+\t\tif (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {\n+\t\t\tif (unlikely(ret != MLX5_CQE_STATUS_HW_OWN))\n+\t\t\t\tmlx5_crypto_cqe_err_handle(qp, op);\n+\t\t\tbreak;\n+\t\t}\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\tops[i++] = op;\n+\t\tqp->ci++;\n+\t} while (i < max);\n+\tif (likely(i != 0)) {\n+\t\trte_io_wmb();\n+\t\tqp->cq_obj.db_rec[0] = rte_cpu_to_be_32(qp->ci);\n+\t}\n+\treturn i;\n+}\n+\n static void\n mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)\n {\n@@ -489,8 +722,9 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n \tif (mlx5_crypto_pd_create(priv) != 0)\n \t\treturn -1;\n \tpriv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);\n-\tif (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==\n-\t NULL) {\n+\tif (priv->uar)\n+\t\tpriv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);\n+\tif (priv->uar == NULL || priv->uar_addr == NULL) {\n \t\trte_errno = errno;\n \t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n \t\tDRV_LOG(ERR, \"Failed to allocate UAR.\");\n@@ -685,9 +919,8 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \tDRV_LOG(INFO,\n \t\t\"Crypto device %s was created successfully.\", ibv->name);\n \tcrypto_dev->dev_ops = &mlx5_crypto_ops;\n-\tcrypto_dev->dequeue_burst = NULL;\n-\tcrypto_dev->enqueue_burst = NULL;\n-\tcrypto_dev->feature_flags = RTE_CRYPTODEV_FF_HW_ACCELERATED;\n+\tcrypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst;\n+\tcrypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst;\n \tcrypto_dev->driver_id = mlx5_crypto_driver_id;\n \tpriv = crypto_dev->data->dev_private;\n \tpriv->ctx = ctx;\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 52fcf5217f..ac4ad1834f 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -37,6 +37,9 @@ struct mlx5_crypto_priv {\n \tuint16_t rdmw_wqe_size;\n \tuint16_t wqe_stride;\n \tuint16_t max_rdmaw_klm_n;\n+#ifndef RTE_ARCH_64\n+\trte_spinlock_t uar32_sl;\n+#endif /* RTE_ARCH_64 */\n };\n \n struct mlx5_crypto_qp {\n", "prefixes": [ "v2", "13/15" ] }