Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/91561/?format=api
{ "id": 91561, "url": "https://patches.dpdk.org/api/patches/91561/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210415092908.805959-1-yuying.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210415092908.805959-1-yuying.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210415092908.805959-1-yuying.zhang@intel.com", "date": "2021-04-15T09:29:07", "name": "[v5,1/2] net/ice: support GTPU TEID pattern for switch filter", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f64f53e866bba24c1d29511621fb7a2362eb83f0", "submitter": { "id": 1844, "url": "https://patches.dpdk.org/api/people/1844/?format=api", "name": "Zhang, Yuying", "email": "yuying.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210415092908.805959-1-yuying.zhang@intel.com/mbox/", "series": [ { "id": 16406, "url": "https://patches.dpdk.org/api/series/16406/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16406", "date": "2021-04-15T09:29:07", "name": "[v5,1/2] net/ice: support GTPU TEID pattern for switch filter", "version": 5, "mbox": "https://patches.dpdk.org/series/16406/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91561/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/91561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 75EFCA0C3F;\n\tThu, 15 Apr 2021 11:39:51 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 47D8D16218C;\n\tThu, 15 Apr 2021 11:39:51 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id ADD23161C40\n for <dev@dpdk.org>; Thu, 15 Apr 2021 11:39:49 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Apr 2021 02:39:46 -0700", "from dpdk-yyzhang2.sh.intel.com ([10.67.117.129])\n by fmsmga002.fm.intel.com with ESMTP; 15 Apr 2021 02:39:45 -0700" ], "IronPort-SDR": [ "\n xzn4EASxRkKz1JB0ZFb6i1brN5sCzhSJivW0s+vP36rEUy7h4j0heqUX8UClbzyo8wZoYGC9ax\n R35MpX73H28w==", "\n USRQHr419jZ2jFuBCuvUtuQj90wkmv0/FUEdwK0x6PDmHSzcQjJb2rjLh/0dbJPKTQbX3//qXi\n Xa8CGRhC6eUg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9954\"; a=\"256140399\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"256140399\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"452845513\"" ], "X-ExtLoop1": "1", "From": "Yuying Zhang <yuying.zhang@intel.com>", "To": "dev@dpdk.org,\n\tqi.z.zhang@intel.com", "Cc": "Yuying Zhang <yuying.zhang@intel.com>", "Date": "Thu, 15 Apr 2021 09:29:07 +0000", "Message-Id": "<20210415092908.805959-1-yuying.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210318084824.165907-1-yuying.zhang@intel.com>", "References": "<20210318084824.165907-1-yuying.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 1/2] net/ice: support GTPU TEID pattern for\n switch filter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable GTPU pattern for CVL switch filter. Support teid and\nqfi field of GTPU pattern. Patterns without inner l3/l4 field\nsupport outer dst/src ip. Patterns with inner l3/l4 field only\nsupport inner dst/src ip and inner dst/src port.\n\n+-----------------------------------+-------------------------------------+\n| Pattern | Input Set |\n+-----------------------------------+-------------------------------------+\n| pattern_eth_ipv4_gtpu | teid, dst/src ip |\n| pattern_eth_ipv6_gtpu | teid, dst/src ip |\n| pattern_eth_ipv4_gtpu_ipv4 | teid, dst/src ip |\n| pattern_eth_ipv4_gtpu_ipv4_tcp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_ipv4_udp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_ipv6 | teid, dst/src ip |\n| pattern_eth_ipv4_gtpu_ipv6_tcp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_ipv6_udp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_ipv4 | teid, dst/src ip |\n| pattern_eth_ipv6_gtpu_ipv4_tcp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_ipv4_udp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_ipv6 | teid, dst/src ip |\n| pattern_eth_ipv6_gtpu_ipv6_tcp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_ipv6_udp | teid, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_eh_ipv4 | teid, qfi, dst/src ip |\n| pattern_eth_ipv4_gtpu_eh_ipv4_tcp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_eh_ipv4_udp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_eh_ipv6 | teid, qfi, dst/src ip |\n| pattern_eth_ipv4_gtpu_eh_ipv6_tcp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv4_gtpu_eh_ipv6_udp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_eh_ipv4 | teid, qfi, dst/src ip |\n| pattern_eth_ipv6_gtpu_eh_ipv4_tcp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_eh_ipv4_udp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_eh_ipv6 | teid, qfi, dst/src ip |\n| pattern_eth_ipv6_gtpu_eh_ipv6_tcp | teid, qfi, dst/src ip, dst/src port |\n| pattern_eth_ipv6_gtpu_eh_ipv6_udp | teid, qfi, dst/src ip, dst/src port |\n+-----------------------------------+-------------------------------------+\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\n---\n doc/guides/rel_notes/release_21_05.rst | 1 +\n drivers/net/ice/ice_switch_filter.c | 288 ++++++++++++++++++++++++-\n 2 files changed, 284 insertions(+), 5 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst\nindex 3bd775772f..d28e44c997 100644\n--- a/doc/guides/rel_notes/release_21_05.rst\n+++ b/doc/guides/rel_notes/release_21_05.rst\n@@ -125,6 +125,7 @@ New Features\n * **Updated Intel ice driver.**\n \n * Added Intel ice support on Windows.\n+ * Added GTPU TEID support for DCF switch filter.\n \n * **Updated Marvell OCTEON TX2 ethdev driver.**\n \ndiff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex 0bf3660677..7560fc4353 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -137,6 +137,78 @@\n #define ICE_SW_INSET_MAC_IPV6_PFCP ( \\\n \tICE_SW_INSET_MAC_IPV6 | \\\n \tICE_INSET_PFCP_S_FIELD | ICE_INSET_PFCP_SEID)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU ( \\\n+\tICE_SW_INSET_MAC_IPV4 | ICE_INSET_GTPU_TEID)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU ( \\\n+\tICE_SW_INSET_MAC_IPV6 | ICE_INSET_GTPU_TEID)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV4 ( \\\n+\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n+\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4 ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4 | ICE_INSET_GTPU_QFI)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV6 ( \\\n+\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n+\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6 ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6 | ICE_INSET_GTPU_QFI)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV4 ( \\\n+\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n+\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4 ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4 | ICE_INSET_GTPU_QFI)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV6 ( \\\n+\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n+\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6 ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6 | ICE_INSET_GTPU_QFI)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV4_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV4_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV6_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV6_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV4_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV4_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_UDP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6 | \\\n+\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV6_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_TCP ( \\\n+\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6 | \\\n+\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n \n struct sw_meta {\n \tstruct ice_adv_lkup_elem *list;\n@@ -198,6 +270,32 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {\n \t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n \t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n \t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n };\n \n static struct\n@@ -251,6 +349,32 @@ ice_pattern_match_item ice_switch_pattern_perm_list[] = {\n \t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n \t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n \t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n };\n \n static int\n@@ -378,6 +502,8 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \tconst struct rte_flow_item_ah *ah_spec, *ah_mask;\n \tconst struct rte_flow_item_l2tpv3oip *l2tp_spec, *l2tp_mask;\n \tconst struct rte_flow_item_pfcp *pfcp_spec, *pfcp_mask;\n+\tconst struct rte_flow_item_gtp *gtp_spec, *gtp_mask;\n+\tconst struct rte_flow_item_gtp_psc *gtp_psc_spec, *gtp_psc_mask;\n \tuint64_t input_set = ICE_INSET_NONE;\n \tuint16_t input_set_byte = 0;\n \tbool pppoe_elem_valid = 0;\n@@ -394,7 +520,13 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \tbool ipv4_valid = 0;\n \tbool udp_valid = 0;\n \tbool tcp_valid = 0;\n-\tuint16_t j, t = 0;\n+\tbool gtpu_valid = 0;\n+\tbool gtpu_psc_valid = 0;\n+\tbool inner_ipv4_valid = 0;\n+\tbool inner_ipv6_valid = 0;\n+\tbool inner_tcp_valid = 0;\n+\tbool inner_udp_valid = 0;\n+\tuint16_t j, k, t = 0;\n \n \tif (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n \t *tun_type == ICE_NON_TUN_QINQ)\n@@ -484,7 +616,11 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n \t\t\tipv4_spec = item->spec;\n \t\t\tipv4_mask = item->mask;\n-\t\t\tipv4_valid = 1;\n+\t\t\tif (tunnel_valid)\n+\t\t\t\tinner_ipv4_valid = 1;\n+\t\t\telse\n+\t\t\t\tipv4_valid = 1;\n+\n \t\t\tif (ipv4_spec && ipv4_mask) {\n \t\t\t\t/* Check IPv4 mask and update input set */\n \t\t\t\tif (ipv4_mask->hdr.version_ihl ||\n@@ -576,7 +712,10 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n \t\t\tipv6_spec = item->spec;\n \t\t\tipv6_mask = item->mask;\n-\t\t\tipv6_valid = 1;\n+\t\t\tif (tunnel_valid)\n+\t\t\t\tinner_ipv6_valid = 1;\n+\t\t\telse\n+\t\t\t\tipv6_valid = 1;\n \t\t\tif (ipv6_spec && ipv6_mask) {\n \t\t\t\tif (ipv6_mask->hdr.payload_len) {\n \t\t\t\t\trte_flow_error_set(error, EINVAL,\n@@ -694,7 +833,10 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_UDP:\n \t\t\tudp_spec = item->spec;\n \t\t\tudp_mask = item->mask;\n-\t\t\tudp_valid = 1;\n+\t\t\tif (tunnel_valid)\n+\t\t\t\tinner_udp_valid = 1;\n+\t\t\telse\n+\t\t\t\tudp_valid = 1;\n \t\t\tif (udp_spec && udp_mask) {\n \t\t\t\t/* Check UDP mask and update input set*/\n \t\t\t\tif (udp_mask->hdr.dgram_len ||\n@@ -747,7 +889,10 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n \t\t\ttcp_spec = item->spec;\n \t\t\ttcp_mask = item->mask;\n-\t\t\ttcp_valid = 1;\n+\t\t\tif (tunnel_valid)\n+\t\t\t\tinner_tcp_valid = 1;\n+\t\t\telse\n+\t\t\t\ttcp_valid = 1;\n \t\t\tif (tcp_spec && tcp_mask) {\n \t\t\t\t/* Check TCP mask and update input set */\n \t\t\t\tif (tcp_mask->hdr.sent_seq ||\n@@ -1263,6 +1408,71 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t}\n \t\t\tbreak;\n \n+\t\tcase RTE_FLOW_ITEM_TYPE_GTPU:\n+\t\t\tgtp_spec = item->spec;\n+\t\t\tgtp_mask = item->mask;\n+\t\t\tif (gtp_spec && !gtp_mask) {\n+\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\titem,\n+\t\t\t\t\t\"Invalid GTP item\");\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t\tif (gtp_spec && gtp_mask) {\n+\t\t\t\tif (gtp_mask->v_pt_rsv_flags ||\n+\t\t\t\t gtp_mask->msg_type ||\n+\t\t\t\t gtp_mask->msg_len) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid GTP mask\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t\tif (gtp_mask->teid)\n+\t\t\t\t\tinput_set |= ICE_INSET_GTPU_TEID;\n+\t\t\t\tlist[t].type = ICE_GTP;\n+\t\t\t\tlist[t].h_u.gtp_hdr.teid =\n+\t\t\t\t\tgtp_spec->teid;\n+\t\t\t\tlist[t].m_u.gtp_hdr.teid =\n+\t\t\t\t\tgtp_mask->teid;\n+\t\t\t\tinput_set_byte += 4;\n+\t\t\t\tt++;\n+\t\t\t}\n+\t\t\ttunnel_valid = 1;\n+\t\t\tgtpu_valid = 1;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n+\t\t\tgtp_psc_spec = item->spec;\n+\t\t\tgtp_psc_mask = item->mask;\n+\t\t\tif (gtp_psc_spec && !gtp_psc_mask) {\n+\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\titem,\n+\t\t\t\t\t\"Invalid GTPU_EH item\");\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t\tif (gtp_psc_spec && gtp_psc_mask) {\n+\t\t\t\tif (gtp_psc_mask->pdu_type) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid GTPU_EH mask\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t\tif (gtp_psc_mask->qfi)\n+\t\t\t\t\tinput_set |= ICE_INSET_GTPU_QFI;\n+\t\t\t\tlist[t].type = ICE_GTP;\n+\t\t\t\tlist[t].h_u.gtp_hdr.qfi =\n+\t\t\t\t\tgtp_psc_spec->qfi;\n+\t\t\t\tlist[t].m_u.gtp_hdr.qfi =\n+\t\t\t\t\tgtp_psc_mask->qfi;\n+\t\t\t\tinput_set_byte += 1;\n+\t\t\t\tt++;\n+\t\t\t}\n+\t\t\tgtpu_psc_valid = 1;\n+\t\t\tbreak;\n+\n \t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n \t\t\tbreak;\n \n@@ -1310,6 +1520,74 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t*tun_type = ICE_SW_TUN_PPPOE;\n \t}\n \n+\tif (gtpu_valid && gtpu_psc_valid) {\n+\t\tif (ipv4_valid && inner_ipv4_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_EH_IPV4_UDP;\n+\t\telse if (ipv4_valid && inner_ipv4_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_EH_IPV4_TCP;\n+\t\telse if (ipv4_valid && inner_ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_EH_IPV4;\n+\t\telse if (ipv4_valid && inner_ipv6_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_EH_IPV6_UDP;\n+\t\telse if (ipv4_valid && inner_ipv6_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_EH_IPV6_TCP;\n+\t\telse if (ipv4_valid && inner_ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_EH_IPV6;\n+\t\telse if (ipv6_valid && inner_ipv4_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_EH_IPV4_UDP;\n+\t\telse if (ipv6_valid && inner_ipv4_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_EH_IPV4_TCP;\n+\t\telse if (ipv6_valid && inner_ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_EH_IPV4;\n+\t\telse if (ipv6_valid && inner_ipv6_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP;\n+\t\telse if (ipv6_valid && inner_ipv6_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP;\n+\t\telse if (ipv6_valid && inner_ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_EH_IPV6;\n+\t\telse if (ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_NO_PAY;\n+\t\telse if (ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_NO_PAY;\n+\t} else if (gtpu_valid) {\n+\t\tif (ipv4_valid && inner_ipv4_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_IPV4_UDP;\n+\t\telse if (ipv4_valid && inner_ipv4_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_IPV4_TCP;\n+\t\telse if (ipv4_valid && inner_ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_IPV4;\n+\t\telse if (ipv4_valid && inner_ipv6_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_IPV6_UDP;\n+\t\telse if (ipv4_valid && inner_ipv6_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_IPV6_TCP;\n+\t\telse if (ipv4_valid && inner_ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_IPV6;\n+\t\telse if (ipv6_valid && inner_ipv4_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_IPV4_UDP;\n+\t\telse if (ipv6_valid && inner_ipv4_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_IPV4_TCP;\n+\t\telse if (ipv6_valid && inner_ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_IPV4;\n+\t\telse if (ipv6_valid && inner_ipv6_valid && inner_udp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_IPV6_UDP;\n+\t\telse if (ipv6_valid && inner_ipv6_valid && inner_tcp_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_IPV6_TCP;\n+\t\telse if (ipv6_valid && inner_ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_IPV6;\n+\t\telse if (ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV4_GTPU_NO_PAY;\n+\t\telse if (ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_IPV6_GTPU_NO_PAY;\n+\t}\n+\n+\tif (*tun_type == ICE_SW_TUN_IPV4_GTPU_NO_PAY ||\n+\t *tun_type == ICE_SW_TUN_IPV6_GTPU_NO_PAY) {\n+\t\tfor (k = 0; k < t; k++) {\n+\t\t\tif (list[k].type == ICE_GTP)\n+\t\t\t\tlist[k].type = ICE_GTP_NO_PAY;\n+\t\t}\n+\t}\n+\n \tif (*tun_type == ICE_NON_TUN) {\n \t\tif (vxlan_valid)\n \t\t\t*tun_type = ICE_SW_TUN_VXLAN;\n", "prefixes": [ "v5", "1/2" ] }