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GET /api/patches/91509/?format=api
{ "id": 91509, "url": "https://patches.dpdk.org/api/patches/91509/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-26-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618451359-20693-26-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-26-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-15T01:49:17", "name": "[v4,25/27] doc/dlb2: update documentation for v2.5", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0c13c21fedaf752d7ad1d00db2447cc8d1b5479b", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-26-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16383, "url": "https://patches.dpdk.org/api/series/16383/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383", "date": "2021-04-15T01:48:52", "name": "Add DLB v2.5", "version": 4, "mbox": "https://patches.dpdk.org/series/16383/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91509/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91509/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 747ACA0562;\n\tThu, 15 Apr 2021 03:53:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0148B161EC7;\n\tThu, 15 Apr 2021 03:51:10 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 6FD24161E4E\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:49 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:47 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:46 -0700" ], "IronPort-SDR": [ "\n PZbxaANd+NU/1xSpo02GLLq9kMhYm9gFiTWvMDRCvj6x9HkH6RXu+tNQRdE0lYAB/ety4CjqSl\n eHwbDRhsEXxA==", "\n TihPJI77thEYgM9giV4jA8OsGv35XgYMLRzf2mEQel3o8CP4b83dk6bukdsV/QrWPGYP64aqtb\n KE0vkkfPczVQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9954\"; a=\"194881864\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"194881864\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569921\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net", "Date": "Wed, 14 Apr 2021 20:49:17 -0500", "Message-Id": "<1618451359-20693-26-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] =?utf-8?q?=5BPATCH_v4_25/27=5D_doc/dlb2=3A_update_docume?=\n\t=?utf-8?q?ntation_for_v2=2E5?=", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the dlb documentation for v2.5. Notable differences include\nthe new cobined credit scheme. Also cleaned up a couple of sections,\nand removed a duplicate section.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n doc/guides/eventdevs/dlb2.rst | 75 +++++++++++++----------------------\n 1 file changed, 27 insertions(+), 48 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/dlb2.rst b/doc/guides/eventdevs/dlb2.rst\nindex 94d2c77ff..94e46ea7d 100644\n--- a/doc/guides/eventdevs/dlb2.rst\n+++ b/doc/guides/eventdevs/dlb2.rst\n@@ -4,7 +4,8 @@\n Driver for the Intel® Dynamic Load Balancer (DLB2)\n ==================================================\n \n-The DPDK dlb poll mode driver supports the Intel® Dynamic Load Balancer.\n+The DPDK dlb poll mode driver supports the Intel® Dynamic Load Balancer,\n+hardware versions 2.0 and 2.5.\n \n Prerequisites\n -------------\n@@ -35,7 +36,7 @@ eventdev API and DLB2 misalign.\n Scheduling Domain Configuration\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n \n-There are 32 scheduling domainis the DLB2.\n+DLB2 supports 32 scheduling domains.\n When one is configured, it allocates load-balanced and\n directed queues, ports, credits, and other hardware resources. Some\n resource allocations are user-controlled -- the number of queues, for example\n@@ -67,42 +68,7 @@ If the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag is not set, schedule_type\n dictates the queue's scheduling type.\n \n The ``nb_atomic_order_sequences`` queue configuration field sets the ordered\n-queue's reorder buffer size. DLB2 has 4 groups of ordered queues, where each\n-group is configured to contain either 1 queue with 1024 reorder entries, 2\n-queues with 512 reorder entries, and so on down to 32 queues with 32 entries.\n-\n-When a load-balanced queue is created, the PMD will configure a new sequence\n-number group on-demand if num_sequence_numbers does not match a pre-existing\n-group with available reorder buffer entries. If all sequence number groups are\n-in use, no new group will be created and queue configuration will fail. (Note\n-that when the PMD is used with a virtual DLB2 device, it cannot change the\n-sequence number configuration.)\n-\n-The queue's ``nb_atomic_flows`` parameter is ignored by the DLB2 PMD, because\n-the DLB2 does not limit the number of flows a queue can track. In the DLB2, all\n-load-balanced queues can use the full 16-bit flow ID range.\n-\n-Load-Balanced Queues\n-~~~~~~~~~~~~~~~~~~~~\n-\n-A load-balanced queue can support atomic and ordered scheduling, or atomic and\n-unordered scheduling, but not atomic and unordered and ordered scheduling. A\n-queue's scheduling types are controlled by the event queue configuration.\n-\n-If the user sets the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag, the\n-``nb_atomic_order_sequences`` determines the supported scheduling types.\n-With non-zero ``nb_atomic_order_sequences``, the queue is configured for atomic\n-and ordered scheduling. In this case, ``RTE_SCHED_TYPE_PARALLEL`` scheduling is\n-supported by scheduling those events as ordered events. Note that when the\n-event is dequeued, its sched_type will be ``RTE_SCHED_TYPE_ORDERED``. Else if\n-``nb_atomic_order_sequences`` is zero, the queue is configured for atomic and\n-unordered scheduling. In this case, ``RTE_SCHED_TYPE_ORDERED`` is unsupported.\n-\n-If the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag is not set, schedule_type\n-dictates the queue's scheduling type.\n-\n-The ``nb_atomic_order_sequences`` queue configuration field sets the ordered\n-queue's reorder buffer size. DLB2 has 4 groups of ordered queues, where each\n+queue's reorder buffer size. DLB2 has 2 groups of ordered queues, where each\n group is configured to contain either 1 queue with 1024 reorder entries, 2\n queues with 512 reorder entries, and so on down to 32 queues with 32 entries.\n \n@@ -157,6 +123,11 @@ type (atomic, ordered, or parallel) is not preserved, and an event's sched_type\n will be set to ``RTE_SCHED_TYPE_ATOMIC`` when it is dequeued from a directed\n port.\n \n+Finally, even though all 3 event types are supported on the same QID by\n+converting unordered events to ordered, such use should be discouraged as much\n+as possible, since mixing types on the same queue uses valuable reorder\n+resources, and orders events which do not require ordering.\n+\n Flow ID\n ~~~~~~~\n \n@@ -169,13 +140,15 @@ Hardware Credits\n DLB2 uses a hardware credit scheme to prevent software from overflowing hardware\n event storage, with each unit of storage represented by a credit. A port spends\n a credit to enqueue an event, and hardware refills the ports with credits as the\n-events are scheduled to ports. Refills come from credit pools, and each port is\n-a member of a load-balanced credit pool and a directed credit pool. The\n-load-balanced credits are used to enqueue to load-balanced queues, and directed\n-credits are used for directed queues.\n+events are scheduled to ports. Refills come from credit pools.\n \n-A DLB2 eventdev contains one load-balanced and one directed credit pool. These\n-pools' sizes are controlled by the nb_events_limit field in struct\n+For DLB v2.5, there is a single credit pool used for both load balanced and\n+directed traffic.\n+\n+For DLB v2.0, each port is a member of both a load-balanced credit pool and a\n+directed credit pool. The load-balanced credits are used to enqueue to\n+load-balanced queues, and directed credits are used for directed queues.\n+These pools' sizes are controlled by the nb_events_limit field in struct\n rte_event_dev_config. The load-balanced pool is sized to contain\n nb_events_limit credits, and the directed pool is sized to contain\n nb_events_limit/4 credits. The directed pool size can be overridden with the\n@@ -276,10 +249,16 @@ The DLB2 supports event priority and per-port queue service priority, as\n described in the eventdev header file. The DLB2 does not support 'global' event\n queue priority established at queue creation time.\n \n-DLB2 supports 8 event and queue service priority levels. For both priority\n-types, the PMD uses the upper three bits of the priority field to determine the\n-DLB2 priority, discarding the 5 least significant bits. The 5 least significant\n-event priority bits are not preserved when an event is enqueued.\n+DLB2 supports 4 event and queue service priority levels. For both priority types,\n+the PMD uses the upper three bits of the priority field to determine the DLB2\n+priority, discarding the 5 least significant bits. But least significant bit out\n+of 3 priority bits is effectively ignored for binning into 4 priorities. The\n+discarded 5 least significant event priority bits are not preserved when an event\n+is enqueued.\n+\n+Note that event priority only works within the same event type.\n+When atomic and ordered or unordered events are enqueued to same QID, priority\n+across the types is always equal, and both types are served in a round robin manner.\n \n Reconfiguration\n ~~~~~~~~~~~~~~~\n", "prefixes": [ "v4", "25/27" ] }