Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/91499/?format=api
{ "id": 91499, "url": "https://patches.dpdk.org/api/patches/91499/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-16-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618451359-20693-16-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-16-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-15T01:49:07", "name": "[v4,15/27] event/dlb2: add v2.5 credit scheme", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e4ef194d4dc541e60d1741bd2ec53049fbc326e5", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-16-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16383, "url": "https://patches.dpdk.org/api/series/16383/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383", "date": "2021-04-15T01:48:52", "name": "Add DLB v2.5", "version": 4, "mbox": "https://patches.dpdk.org/series/16383/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91499/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/91499/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DDCB0A0562;\n\tThu, 15 Apr 2021 03:52:32 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6F4B5161E7E;\n\tThu, 15 Apr 2021 03:50:55 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 55A43161E22\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:40 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:39 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:39 -0700" ], "IronPort-SDR": [ "\n AbUMTadlQ4JXkBUeYaSUUfIpToTcGnUovJi8yAbVT5klXv3s5iqLAlBfVtl2o8/79Pf6gHhd/P\n nL8vOBUPhXAQ==", "\n S+ZruCwxY1haxYUhxSyvYt5xcHziRnKngwRqc0x+7AlyT1hKSJ1yYpziHDNlhJ6dlk4gu7MBjV\n kAmUjrjuqa3A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9954\"; a=\"215272811\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"215272811\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569869\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net", "Date": "Wed, 14 Apr 2021 20:49:07 -0500", "Message-Id": "<1618451359-20693-16-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 15/27] event/dlb2: add v2.5 credit scheme", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "DLB v2.5 uses a different credit scheme than was used in DLB v2.0 .\nSpecifically, there is a single credit pool for both load balanced\nand directed traffic, instead of a separate pool for each as is\nfound with DLB v2.0.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 311 ++++++++++++++++++++++++++------------\n 1 file changed, 212 insertions(+), 99 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 0048f6a1b..cc6495b76 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -436,8 +436,13 @@ dlb2_eventdev_info_get(struct rte_eventdev *dev,\n \t */\n \tevdev_dlb2_default_info.max_event_ports += dlb2->num_ldb_ports;\n \tevdev_dlb2_default_info.max_event_queues += dlb2->num_ldb_queues;\n-\tevdev_dlb2_default_info.max_num_events += dlb2->max_ldb_credits;\n-\n+\tif (dlb2->version == DLB2_HW_V2_5) {\n+\t\tevdev_dlb2_default_info.max_num_events +=\n+\t\t\tdlb2->max_credits;\n+\t} else {\n+\t\tevdev_dlb2_default_info.max_num_events +=\n+\t\t\tdlb2->max_ldb_credits;\n+\t}\n \tevdev_dlb2_default_info.max_event_queues =\n \t\tRTE_MIN(evdev_dlb2_default_info.max_event_queues,\n \t\t\tRTE_EVENT_MAX_QUEUES_PER_DEV);\n@@ -451,7 +456,8 @@ dlb2_eventdev_info_get(struct rte_eventdev *dev,\n \n static int\n dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n-\t\t\t const struct dlb2_hw_rsrcs *resources_asked)\n+\t\t\t const struct dlb2_hw_rsrcs *resources_asked,\n+\t\t\t uint8_t device_version)\n {\n \tint ret = 0;\n \tstruct dlb2_create_sched_domain_args *cfg;\n@@ -468,8 +474,10 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n \t/* DIR ports and queues */\n \n \tcfg->num_dir_ports = resources_asked->num_dir_ports;\n-\n-\tcfg->num_dir_credits = resources_asked->num_dir_credits;\n+\tif (device_version == DLB2_HW_V2_5)\n+\t\tcfg->num_credits = resources_asked->num_credits;\n+\telse\n+\t\tcfg->num_dir_credits = resources_asked->num_dir_credits;\n \n \t/* LDB queues */\n \n@@ -509,8 +517,8 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n \t\tbreak;\n \t}\n \n-\tcfg->num_ldb_credits =\n-\t\tresources_asked->num_ldb_credits;\n+\tif (device_version == DLB2_HW_V2)\n+\t\tcfg->num_ldb_credits = resources_asked->num_ldb_credits;\n \n \tcfg->num_atomic_inflights =\n \t\tDLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE *\n@@ -519,14 +527,24 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n \tcfg->num_hist_list_entries = resources_asked->num_ldb_ports *\n \t\tDLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n \n-\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d\\n\",\n-\t\t cfg->num_ldb_queues,\n-\t\t resources_asked->num_ldb_ports,\n-\t\t cfg->num_dir_ports,\n-\t\t cfg->num_atomic_inflights,\n-\t\t cfg->num_hist_list_entries,\n-\t\t cfg->num_ldb_credits,\n-\t\t cfg->num_dir_credits);\n+\tif (device_version == DLB2_HW_V2_5) {\n+\t\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\\n\",\n+\t\t\t cfg->num_ldb_queues,\n+\t\t\t resources_asked->num_ldb_ports,\n+\t\t\t cfg->num_dir_ports,\n+\t\t\t cfg->num_atomic_inflights,\n+\t\t\t cfg->num_hist_list_entries,\n+\t\t\t cfg->num_credits);\n+\t} else {\n+\t\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d\\n\",\n+\t\t\t cfg->num_ldb_queues,\n+\t\t\t resources_asked->num_ldb_ports,\n+\t\t\t cfg->num_dir_ports,\n+\t\t\t cfg->num_atomic_inflights,\n+\t\t\t cfg->num_hist_list_entries,\n+\t\t\t cfg->num_ldb_credits,\n+\t\t\t cfg->num_dir_credits);\n+\t}\n \n \t/* Configure the QM */\n \n@@ -606,7 +624,6 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)\n \t */\n \tif (dlb2->configured) {\n \t\tdlb2_hw_reset_sched_domain(dev, true);\n-\n \t\tret = dlb2_hw_query_resources(dlb2);\n \t\tif (ret) {\n \t\t\tDLB2_LOG_ERR(\"get resources err=%d, devid=%d\\n\",\n@@ -665,20 +682,26 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)\n \t/* 1 dir queue per dir port */\n \trsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;\n \n-\t/* Scale down nb_events_limit by 4 for directed credits, since there\n-\t * are 4x as many load-balanced credits.\n-\t */\n-\trsrcs->num_ldb_credits = 0;\n-\trsrcs->num_dir_credits = 0;\n+\tif (dlb2->version == DLB2_HW_V2_5) {\n+\t\trsrcs->num_credits = 0;\n+\t\tif (rsrcs->num_ldb_queues || rsrcs->num_dir_ports)\n+\t\t\trsrcs->num_credits = config->nb_events_limit;\n+\t} else {\n+\t\t/* Scale down nb_events_limit by 4 for directed credits,\n+\t\t * since there are 4x as many load-balanced credits.\n+\t\t */\n+\t\trsrcs->num_ldb_credits = 0;\n+\t\trsrcs->num_dir_credits = 0;\n \n-\tif (rsrcs->num_ldb_queues)\n-\t\trsrcs->num_ldb_credits = config->nb_events_limit;\n-\tif (rsrcs->num_dir_ports)\n-\t\trsrcs->num_dir_credits = config->nb_events_limit / 4;\n-\tif (dlb2->num_dir_credits_override != -1)\n-\t\trsrcs->num_dir_credits = dlb2->num_dir_credits_override;\n+\t\tif (rsrcs->num_ldb_queues)\n+\t\t\trsrcs->num_ldb_credits = config->nb_events_limit;\n+\t\tif (rsrcs->num_dir_ports)\n+\t\t\trsrcs->num_dir_credits = config->nb_events_limit / 4;\n+\t\tif (dlb2->num_dir_credits_override != -1)\n+\t\t\trsrcs->num_dir_credits = dlb2->num_dir_credits_override;\n+\t}\n \n-\tif (dlb2_hw_create_sched_domain(handle, rsrcs) < 0) {\n+\tif (dlb2_hw_create_sched_domain(handle, rsrcs, dlb2->version) < 0) {\n \t\tDLB2_LOG_ERR(\"dlb2_hw_create_sched_domain failed\\n\");\n \t\treturn -ENODEV;\n \t}\n@@ -693,10 +716,15 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)\n \tdlb2->num_ldb_ports = dlb2->num_ports - dlb2->num_dir_ports;\n \tdlb2->num_ldb_queues = dlb2->num_queues - dlb2->num_dir_ports;\n \tdlb2->num_dir_queues = dlb2->num_dir_ports;\n-\tdlb2->ldb_credit_pool = rsrcs->num_ldb_credits;\n-\tdlb2->max_ldb_credits = rsrcs->num_ldb_credits;\n-\tdlb2->dir_credit_pool = rsrcs->num_dir_credits;\n-\tdlb2->max_dir_credits = rsrcs->num_dir_credits;\n+\tif (dlb2->version == DLB2_HW_V2_5) {\n+\t\tdlb2->credit_pool = rsrcs->num_credits;\n+\t\tdlb2->max_credits = rsrcs->num_credits;\n+\t} else {\n+\t\tdlb2->ldb_credit_pool = rsrcs->num_ldb_credits;\n+\t\tdlb2->max_ldb_credits = rsrcs->num_ldb_credits;\n+\t\tdlb2->dir_credit_pool = rsrcs->num_dir_credits;\n+\t\tdlb2->max_dir_credits = rsrcs->num_dir_credits;\n+\t}\n \n \tdlb2->configured = true;\n \n@@ -1170,8 +1198,9 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tstruct dlb2_port *qm_port = NULL;\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n \tuint32_t qm_port_id;\n-\tuint16_t ldb_credit_high_watermark;\n-\tuint16_t dir_credit_high_watermark;\n+\tuint16_t ldb_credit_high_watermark = 0;\n+\tuint16_t dir_credit_high_watermark = 0;\n+\tuint16_t credit_high_watermark = 0;\n \n \tif (handle == NULL)\n \t\treturn -EINVAL;\n@@ -1206,15 +1235,18 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \t/* User controls the LDB high watermark via enqueue depth. The DIR high\n \t * watermark is equal, unless the directed credit pool is too small.\n \t */\n-\tldb_credit_high_watermark = enqueue_depth;\n-\n-\t/* If there are no directed ports, the kernel driver will ignore this\n-\t * port's directed credit settings. Don't use enqueue_depth if it would\n-\t * require more directed credits than are available.\n-\t */\n-\tdir_credit_high_watermark =\n-\t\tRTE_MIN(enqueue_depth,\n-\t\t\thandle->cfg.num_dir_credits / dlb2->num_ports);\n+\tif (dlb2->version == DLB2_HW_V2) {\n+\t\tldb_credit_high_watermark = enqueue_depth;\n+\t\t/* If there are no directed ports, the kernel driver will\n+\t\t * ignore this port's directed credit settings. Don't use\n+\t\t * enqueue_depth if it would require more directed credits\n+\t\t * than are available.\n+\t\t */\n+\t\tdir_credit_high_watermark =\n+\t\t\tRTE_MIN(enqueue_depth,\n+\t\t\t\thandle->cfg.num_dir_credits / dlb2->num_ports);\n+\t} else\n+\t\tcredit_high_watermark = enqueue_depth;\n \n \t/* Per QM values */\n \n@@ -1249,8 +1281,12 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \n \tqm_port->id = qm_port_id;\n \n-\tqm_port->cached_ldb_credits = 0;\n-\tqm_port->cached_dir_credits = 0;\n+\tif (dlb2->version == DLB2_HW_V2) {\n+\t\tqm_port->cached_ldb_credits = 0;\n+\t\tqm_port->cached_dir_credits = 0;\n+\t} else\n+\t\tqm_port->cached_credits = 0;\n+\n \t/* CQs with depth < 8 use an 8-entry queue, but withhold credits so\n \t * the effective depth is smaller.\n \t */\n@@ -1298,17 +1334,26 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tqm_port->state = PORT_STARTED; /* enabled at create time */\n \tqm_port->config_state = DLB2_CONFIGURED;\n \n-\tqm_port->dir_credits = dir_credit_high_watermark;\n-\tqm_port->ldb_credits = ldb_credit_high_watermark;\n-\tqm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;\n-\tqm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;\n-\n-\tDLB2_LOG_DBG(\"dlb2: created ldb port %d, depth = %d, ldb credits=%d, dir credits=%d\\n\",\n-\t\t qm_port_id,\n-\t\t dequeue_depth,\n-\t\t qm_port->ldb_credits,\n-\t\t qm_port->dir_credits);\n+\tif (dlb2->version == DLB2_HW_V2) {\n+\t\tqm_port->dir_credits = dir_credit_high_watermark;\n+\t\tqm_port->ldb_credits = ldb_credit_high_watermark;\n+\t\tqm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;\n+\t\tqm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;\n+\n+\t\tDLB2_LOG_DBG(\"dlb2: created ldb port %d, depth = %d, ldb credits=%d, dir credits=%d\\n\",\n+\t\t\t qm_port_id,\n+\t\t\t dequeue_depth,\n+\t\t\t qm_port->ldb_credits,\n+\t\t\t qm_port->dir_credits);\n+\t} else {\n+\t\tqm_port->credits = credit_high_watermark;\n+\t\tqm_port->credit_pool[DLB2_COMBINED_POOL] = &dlb2->credit_pool;\n \n+\t\tDLB2_LOG_DBG(\"dlb2: created ldb port %d, depth = %d, credits=%d\\n\",\n+\t\t\t qm_port_id,\n+\t\t\t dequeue_depth,\n+\t\t\t qm_port->credits);\n+\t}\n \trte_spinlock_unlock(&handle->resource_lock);\n \n \treturn 0;\n@@ -1356,8 +1401,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,\n \tstruct dlb2_port *qm_port = NULL;\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n \tuint32_t qm_port_id;\n-\tuint16_t ldb_credit_high_watermark;\n-\tuint16_t dir_credit_high_watermark;\n+\tuint16_t ldb_credit_high_watermark = 0;\n+\tuint16_t dir_credit_high_watermark = 0;\n+\tuint16_t credit_high_watermark = 0;\n \n \tif (dlb2 == NULL || handle == NULL)\n \t\treturn -EINVAL;\n@@ -1386,14 +1432,16 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,\n \t/* User controls the LDB high watermark via enqueue depth. The DIR high\n \t * watermark is equal, unless the directed credit pool is too small.\n \t */\n-\tldb_credit_high_watermark = enqueue_depth;\n-\n-\t/* Don't use enqueue_depth if it would require more directed credits\n-\t * than are available.\n-\t */\n-\tdir_credit_high_watermark =\n-\t\tRTE_MIN(enqueue_depth,\n-\t\t\thandle->cfg.num_dir_credits / dlb2->num_ports);\n+\tif (dlb2->version == DLB2_HW_V2) {\n+\t\tldb_credit_high_watermark = enqueue_depth;\n+\t\t/* Don't use enqueue_depth if it would require more directed\n+\t\t * credits than are available.\n+\t\t */\n+\t\tdir_credit_high_watermark =\n+\t\t\tRTE_MIN(enqueue_depth,\n+\t\t\t\thandle->cfg.num_dir_credits / dlb2->num_ports);\n+\t} else\n+\t\tcredit_high_watermark = enqueue_depth;\n \n \t/* Per QM values */\n \n@@ -1430,8 +1478,12 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,\n \n \tqm_port->id = qm_port_id;\n \n-\tqm_port->cached_ldb_credits = 0;\n-\tqm_port->cached_dir_credits = 0;\n+\tif (dlb2->version == DLB2_HW_V2) {\n+\t\tqm_port->cached_ldb_credits = 0;\n+\t\tqm_port->cached_dir_credits = 0;\n+\t} else\n+\t\tqm_port->cached_credits = 0;\n+\n \t/* CQs with depth < 8 use an 8-entry queue, but withhold credits so\n \t * the effective depth is smaller.\n \t */\n@@ -1467,17 +1519,26 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,\n \tqm_port->state = PORT_STARTED; /* enabled at create time */\n \tqm_port->config_state = DLB2_CONFIGURED;\n \n-\tqm_port->dir_credits = dir_credit_high_watermark;\n-\tqm_port->ldb_credits = ldb_credit_high_watermark;\n-\tqm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;\n-\tqm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;\n-\n-\tDLB2_LOG_DBG(\"dlb2: created dir port %d, depth = %d cr=%d,%d\\n\",\n-\t\t qm_port_id,\n-\t\t dequeue_depth,\n-\t\t dir_credit_high_watermark,\n-\t\t ldb_credit_high_watermark);\n+\tif (dlb2->version == DLB2_HW_V2) {\n+\t\tqm_port->dir_credits = dir_credit_high_watermark;\n+\t\tqm_port->ldb_credits = ldb_credit_high_watermark;\n+\t\tqm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;\n+\t\tqm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;\n+\n+\t\tDLB2_LOG_DBG(\"dlb2: created dir port %d, depth = %d cr=%d,%d\\n\",\n+\t\t\t qm_port_id,\n+\t\t\t dequeue_depth,\n+\t\t\t dir_credit_high_watermark,\n+\t\t\t ldb_credit_high_watermark);\n+\t} else {\n+\t\tqm_port->credits = credit_high_watermark;\n+\t\tqm_port->credit_pool[DLB2_COMBINED_POOL] = &dlb2->credit_pool;\n \n+\t\tDLB2_LOG_DBG(\"dlb2: created dir port %d, depth = %d cr=%d\\n\",\n+\t\t\t qm_port_id,\n+\t\t\t dequeue_depth,\n+\t\t\t credit_high_watermark);\n+\t}\n \trte_spinlock_unlock(&handle->resource_lock);\n \n \treturn 0;\n@@ -2297,6 +2358,24 @@ dlb2_check_enqueue_hw_dir_credits(struct dlb2_port *qm_port)\n \treturn 0;\n }\n \n+static inline int\n+dlb2_check_enqueue_hw_credits(struct dlb2_port *qm_port)\n+{\n+\tif (unlikely(qm_port->cached_credits == 0)) {\n+\t\tqm_port->cached_credits =\n+\t\t\tdlb2_port_credits_get(qm_port,\n+\t\t\t\t\t DLB2_COMBINED_POOL);\n+\t\tif (unlikely(qm_port->cached_credits == 0)) {\n+\t\t\tDLB2_INC_STAT(\n+\t\t\tqm_port->ev_port->stats.traffic.tx_nospc_hw_credits, 1);\n+\t\t\tDLB2_LOG_DBG(\"credits exhausted\\n\");\n+\t\t\treturn 1; /* credits exhausted */\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static __rte_always_inline void\n dlb2_pp_write(struct dlb2_enqueue_qe *qe4,\n \t struct process_local_port_data *port_data)\n@@ -2565,12 +2644,19 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \tif (!qm_queue->is_directed) {\n \t\t/* Load balanced destination queue */\n \n-\t\tif (dlb2_check_enqueue_hw_ldb_credits(qm_port)) {\n-\t\t\trte_errno = -ENOSPC;\n-\t\t\treturn 1;\n+\t\tif (dlb2->version == DLB2_HW_V2) {\n+\t\t\tif (dlb2_check_enqueue_hw_ldb_credits(qm_port)) {\n+\t\t\t\trte_errno = -ENOSPC;\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t\tcached_credits = &qm_port->cached_ldb_credits;\n+\t\t} else {\n+\t\t\tif (dlb2_check_enqueue_hw_credits(qm_port)) {\n+\t\t\t\trte_errno = -ENOSPC;\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t\tcached_credits = &qm_port->cached_credits;\n \t\t}\n-\t\tcached_credits = &qm_port->cached_ldb_credits;\n-\n \t\tswitch (ev->sched_type) {\n \t\tcase RTE_SCHED_TYPE_ORDERED:\n \t\t\tDLB2_LOG_DBG(\"dlb2: put_qe: RTE_SCHED_TYPE_ORDERED\\n\");\n@@ -2602,12 +2688,19 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t} else {\n \t\t/* Directed destination queue */\n \n-\t\tif (dlb2_check_enqueue_hw_dir_credits(qm_port)) {\n-\t\t\trte_errno = -ENOSPC;\n-\t\t\treturn 1;\n+\t\tif (dlb2->version == DLB2_HW_V2) {\n+\t\t\tif (dlb2_check_enqueue_hw_dir_credits(qm_port)) {\n+\t\t\t\trte_errno = -ENOSPC;\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t\tcached_credits = &qm_port->cached_dir_credits;\n+\t\t} else {\n+\t\t\tif (dlb2_check_enqueue_hw_credits(qm_port)) {\n+\t\t\t\trte_errno = -ENOSPC;\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t\tcached_credits = &qm_port->cached_credits;\n \t\t}\n-\t\tcached_credits = &qm_port->cached_dir_credits;\n-\n \t\tDLB2_LOG_DBG(\"dlb2: put_qe: RTE_SCHED_TYPE_DIRECTED\\n\");\n \n \t\t*sched_type = DLB2_SCHED_DIRECTED;\n@@ -2891,20 +2984,40 @@ dlb2_port_credits_inc(struct dlb2_port *qm_port, int num)\n \n \t/* increment port credits, and return to pool if exceeds threshold */\n \tif (!qm_port->is_directed) {\n-\t\tqm_port->cached_ldb_credits += num;\n-\t\tif (qm_port->cached_ldb_credits >= 2 * batch_size) {\n-\t\t\t__atomic_fetch_add(\n-\t\t\t\tqm_port->credit_pool[DLB2_LDB_QUEUE],\n-\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n-\t\t\tqm_port->cached_ldb_credits -= batch_size;\n+\t\tif (qm_port->dlb2->version == DLB2_HW_V2) {\n+\t\t\tqm_port->cached_ldb_credits += num;\n+\t\t\tif (qm_port->cached_ldb_credits >= 2 * batch_size) {\n+\t\t\t\t__atomic_fetch_add(\n+\t\t\t\t\tqm_port->credit_pool[DLB2_LDB_QUEUE],\n+\t\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\tqm_port->cached_ldb_credits -= batch_size;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tqm_port->cached_credits += num;\n+\t\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n+\t\t\t\t__atomic_fetch_add(\n+\t\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL],\n+\t\t\t\t batch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\tqm_port->cached_credits -= batch_size;\n+\t\t\t}\n \t\t}\n \t} else {\n-\t\tqm_port->cached_dir_credits += num;\n-\t\tif (qm_port->cached_dir_credits >= 2 * batch_size) {\n-\t\t\t__atomic_fetch_add(\n-\t\t\t\tqm_port->credit_pool[DLB2_DIR_QUEUE],\n-\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n-\t\t\tqm_port->cached_dir_credits -= batch_size;\n+\t\tif (qm_port->dlb2->version == DLB2_HW_V2) {\n+\t\t\tqm_port->cached_dir_credits += num;\n+\t\t\tif (qm_port->cached_dir_credits >= 2 * batch_size) {\n+\t\t\t\t__atomic_fetch_add(\n+\t\t\t\t\tqm_port->credit_pool[DLB2_DIR_QUEUE],\n+\t\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\tqm_port->cached_dir_credits -= batch_size;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tqm_port->cached_credits += num;\n+\t\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n+\t\t\t\t__atomic_fetch_add(\n+\t\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL],\n+\t\t\t\t batch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\tqm_port->cached_credits -= batch_size;\n+\t\t\t}\n \t\t}\n \t}\n }\n", "prefixes": [ "v4", "15/27" ] }