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GET /api/patches/91446/?format=api
{ "id": 91446, "url": "https://patches.dpdk.org/api/patches/91446/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210414113321.3483-2-adamx.dybkowski@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210414113321.3483-2-adamx.dybkowski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210414113321.3483-2-adamx.dybkowski@intel.com", "date": "2021-04-14T11:33:21", "name": "[v3,1/1] crypto/qat: support Single-Pass GMAC on QAT GEN3", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fe70c0f556ad00e53e567ed552bb75f41feb38ef", "submitter": { "id": 1322, "url": "https://patches.dpdk.org/api/people/1322/?format=api", "name": "Dybkowski, AdamX", "email": "adamx.dybkowski@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210414113321.3483-2-adamx.dybkowski@intel.com/mbox/", "series": [ { "id": 16369, "url": "https://patches.dpdk.org/api/series/16369/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16369", "date": "2021-04-14T11:33:20", "name": "crypto/qat: support Single-Pass GMAC on QAT GEN3", "version": 3, "mbox": "https://patches.dpdk.org/series/16369/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91446/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/91446/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 04AA1A0562;\n\tWed, 14 Apr 2021 13:33:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BAE91619E9;\n\tWed, 14 Apr 2021 13:33:45 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id E598A1619DB\n for <dev@dpdk.org>; Wed, 14 Apr 2021 13:33:42 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 04:33:41 -0700", "from silpixa00400308.ir.intel.com ([10.237.214.57])\n by fmsmga004.fm.intel.com with ESMTP; 14 Apr 2021 04:33:39 -0700" ], "IronPort-SDR": [ "\n YkAvAsRefcULFIhEs5ufJxGvskRKkni9XRL7BNsjS+xY1uGtkGj/6f321UM+T+DgJ8k7AOWyJF\n XhWgA2Xheg4Q==", "\n /MpAve8DK+9+UFW446dmOn72h13iEo3rBaUCrSAEzzH1js3g9R3T0zvMd3nFHOr8FqxUIu/RGw\n cyCyKny7Km1g==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"174725910\"", "E=Sophos;i=\"5.82,222,1613462400\"; d=\"scan'208\";a=\"174725910\"", "E=Sophos;i=\"5.82,222,1613462400\"; d=\"scan'208\";a=\"443791144\"" ], "X-ExtLoop1": "1", "From": "Adam Dybkowski <adamx.dybkowski@intel.com>", "To": "dev@dpdk.org, declan.doherty@intel.com, arkadiuszx.kusztal@intel.com,\n gakhil@marvell.com", "Cc": "Adam Dybkowski <adamx.dybkowski@intel.com>", "Date": "Wed, 14 Apr 2021 12:33:21 +0100", "Message-Id": "<20210414113321.3483-2-adamx.dybkowski@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210414113321.3483-1-adamx.dybkowski@intel.com>", "References": "<20210305141641.16707-2-adamx.dybkowski@intel.com>\n <20210414113321.3483-1-adamx.dybkowski@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/1] crypto/qat: support Single-Pass GMAC on\n QAT GEN3", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch implements Single-Pass AES-GMAC possible on QAT GEN3\nwhich improves the performance. On GEN1 and GEN2 the previous\nchained method is used.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\n---\n drivers/common/qat/qat_qp.c | 3 +-\n drivers/crypto/qat/qat_sym.c | 72 +++++++++++++++++++++++++++-\n drivers/crypto/qat/qat_sym.h | 66 ++++++++++++++++---------\n drivers/crypto/qat/qat_sym_pmd.c | 6 +++\n drivers/crypto/qat/qat_sym_session.c | 10 +++-\n drivers/crypto/qat/qat_sym_session.h | 3 +-\n 6 files changed, 132 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 32d740105..4a8078541 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -862,7 +862,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \t\tnb_fw_responses = 1;\n \n \t\tif (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)\n-\t\t\tqat_sym_process_response(ops, resp_msg);\n+\t\t\tqat_sym_process_response(ops, resp_msg,\n+\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz]);\n \t\telse if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)\n \t\t\tnb_fw_responses = qat_comp_process_response(\n \t\t\t\tops, resp_msg,\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 4b7676deb..2c0f5cd92 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -144,6 +144,72 @@ set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,\n \t\t\tiv_length);\n }\n \n+/** Handle Single-Pass AES-GMAC on QAT GEN3 */\n+static inline void\n+handle_spc_gmac(struct qat_sym_session *ctx, struct rte_crypto_op *op,\n+\t\tstruct qat_sym_op_cookie *cookie,\n+\t\tstruct icp_qat_fw_la_bulk_req *qat_req)\n+{\n+\tstatic const uint32_t ver_key_offset =\n+\t\t\tsizeof(struct icp_qat_hw_auth_setup) +\n+\t\t\tICP_QAT_HW_GALOIS_128_STATE1_SZ +\n+\t\t\tICP_QAT_HW_GALOIS_H_SZ + ICP_QAT_HW_GALOIS_LEN_A_SZ +\n+\t\t\tICP_QAT_HW_GALOIS_E_CTR0_SZ +\n+\t\t\tsizeof(struct icp_qat_hw_cipher_config);\n+\tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl =\n+\t\t\t(void *) &qat_req->cd_ctrl;\n+\tstruct icp_qat_fw_la_cipher_req_params *cipher_param =\n+\t\t\t(void *) &qat_req->serv_specif_rqpars;\n+\tuint32_t data_length = op->sym->auth.data.length;\n+\n+\t/* Fill separate Content Descriptor for this op */\n+\trte_memcpy(cookie->opt.spc_gmac.cd_cipher.key,\n+\t\t\tctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?\n+\t\t\t\tctx->cd.cipher.key :\n+\t\t\t\tRTE_PTR_ADD(&ctx->cd, ver_key_offset),\n+\t\t\tctx->auth_key_length);\n+\tcookie->opt.spc_gmac.cd_cipher.cipher_config.val =\n+\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD(\n+\t\t\t\tICP_QAT_HW_CIPHER_AEAD_MODE,\n+\t\t\t\tctx->qat_cipher_alg,\n+\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT,\n+\t\t\t\t(ctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?\n+\t\t\t\t\tICP_QAT_HW_CIPHER_ENCRYPT :\n+\t\t\t\t\tICP_QAT_HW_CIPHER_DECRYPT));\n+\tQAT_FIELD_SET(cookie->opt.spc_gmac.cd_cipher.cipher_config.val,\n+\t\t\tctx->digest_length,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n+\tcookie->opt.spc_gmac.cd_cipher.cipher_config.reserved =\n+\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(data_length);\n+\n+\t/* Update the request */\n+\tqat_req->cd_pars.u.s.content_desc_addr =\n+\t\t\tcookie->opt.spc_gmac.cd_phys_addr;\n+\tqat_req->cd_pars.u.s.content_desc_params_sz = RTE_ALIGN_CEIL(\n+\t\t\tsizeof(struct icp_qat_hw_cipher_config) +\n+\t\t\tctx->auth_key_length, 8) >> 3;\n+\tqat_req->comn_mid.src_length = data_length;\n+\tqat_req->comn_mid.dst_length = 0;\n+\n+\tcipher_param->spc_aad_addr = 0;\n+\tcipher_param->spc_auth_res_addr = op->sym->auth.digest.phys_addr;\n+\tcipher_param->spc_aad_sz = data_length;\n+\tcipher_param->reserved = 0;\n+\tcipher_param->spc_auth_res_sz = ctx->digest_length;\n+\n+\tqat_req->comn_hdr.service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER;\n+\tcipher_cd_ctrl->cipher_cfg_offset = 0;\n+\tICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);\n+\tICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);\n+\tICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(\n+\t\t\tqat_req->comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO);\n+\tICP_QAT_FW_LA_PROTO_SET(\n+\t\t\tqat_req->comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+}\n+\n int\n qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen)\n@@ -619,11 +685,15 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tqat_req->comn_mid.dest_data_addr = dst_buf_start;\n \t}\n \n-\t/* Handle Single-Pass GCM */\n \tif (ctx->is_single_pass) {\n+\t\t/* Handle Single-Pass GCM */\n \t\tcipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;\n \t\tcipher_param->spc_auth_res_addr =\n \t\t\t\top->sym->aead.digest.phys_addr;\n+\t} else if (ctx->is_single_pass_gmac &&\n+\t\t op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {\n+\t\t/* Handle Single-Pass AES-GMAC */\n+\t\thandle_spc_gmac(ctx, op, cookie, qat_req);\n \t}\n \n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex b58be1282..20b1b53d3 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -29,6 +29,9 @@\n */\n #define QAT_SYM_SGL_MAX_NUMBER\t16\n \n+/* Maximum data length for single pass GMAC: 2^14-1 */\n+#define QAT_AES_GMAC_SPC_MAX_SIZE 16383\n+\n struct qat_sym_session;\n \n struct qat_sym_sgl {\n@@ -41,6 +44,14 @@ struct qat_sym_op_cookie {\n \tstruct qat_sym_sgl qat_sgl_dst;\n \tphys_addr_t qat_sgl_src_phys_addr;\n \tphys_addr_t qat_sgl_dst_phys_addr;\n+\tunion {\n+\t\t/* Used for Single-Pass AES-GMAC only */\n+\t\tstruct {\n+\t\t\tstruct icp_qat_hw_cipher_algo_blk cd_cipher\n+\t\t\t\t\t__rte_packed __rte_cache_aligned;\n+\t\t\tphys_addr_t cd_phys_addr;\n+\t\t} spc_gmac;\n+\t} opt;\n };\n \n int\n@@ -212,46 +223,46 @@ qat_sym_preprocess_requests(void **ops __rte_unused,\n #endif\n \n static inline void\n-qat_sym_process_response(void **op, uint8_t *resp)\n+qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie)\n {\n \tstruct icp_qat_fw_comn_resp *resp_msg =\n \t\t\t(struct icp_qat_fw_comn_resp *)resp;\n \tstruct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)\n \t\t\t(resp_msg->opaque_data);\n \tstruct qat_sym_session *sess;\n+\tuint8_t is_docsis_sec;\n \n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n \tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat_response:\", (uint8_t *)resp_msg,\n \t\t\tsizeof(struct icp_qat_fw_comn_resp));\n #endif\n \n+#ifdef RTE_LIB_SECURITY\n+\tif (rx_op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n+\t\t/*\n+\t\t * Assuming at this point that if it's a security\n+\t\t * op, that this is for DOCSIS\n+\t\t */\n+\t\tsess = (struct qat_sym_session *)\n+\t\t\t\tget_sec_session_private_data(\n+\t\t\t\trx_op->sym->sec_session);\n+\t\tis_docsis_sec = 1;\n+\t} else\n+#endif\n+\t{\n+\t\tsess = (struct qat_sym_session *)\n+\t\t\t\tget_sym_session_private_data(\n+\t\t\t\trx_op->sym->session,\n+\t\t\t\tqat_sym_driver_id);\n+\t\tis_docsis_sec = 0;\n+\t}\n+\n \tif (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=\n \t\t\tICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(\n \t\t\tresp_msg->comn_hdr.comn_status)) {\n \n \t\trx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n \t} else {\n-#ifdef RTE_LIB_SECURITY\n-\t\tuint8_t is_docsis_sec = 0;\n-\n-\t\tif (rx_op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n-\t\t\t/*\n-\t\t\t * Assuming at this point that if it's a security\n-\t\t\t * op, that this is for DOCSIS\n-\t\t\t */\n-\t\t\tsess = (struct qat_sym_session *)\n-\t\t\t\t\tget_sec_session_private_data(\n-\t\t\t\t\trx_op->sym->sec_session);\n-\t\t\tis_docsis_sec = 1;\n-\t\t} else\n-#endif\n-\t\t{\n-\t\t\tsess = (struct qat_sym_session *)\n-\t\t\t\t\tget_sym_session_private_data(\n-\t\t\t\t\trx_op->sym->session,\n-\t\t\t\t\tqat_sym_driver_id);\n-\t\t}\n-\n \t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n \n \t\tif (sess->bpi_ctx) {\n@@ -262,6 +273,14 @@ qat_sym_process_response(void **op, uint8_t *resp)\n #endif\n \t\t}\n \t}\n+\n+\tif (sess->is_single_pass_gmac) {\n+\t\tstruct qat_sym_op_cookie *cookie =\n+\t\t\t\t(struct qat_sym_op_cookie *) op_cookie;\n+\t\tmemset(cookie->opt.spc_gmac.cd_cipher.key, 0,\n+\t\t\t\tsess->auth_key_length);\n+\t}\n+\n \t*op = (void *)rx_op;\n }\n \n@@ -283,7 +302,8 @@ qat_sym_preprocess_requests(void **ops __rte_unused,\n }\n \n static inline void\n-qat_sym_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)\n+qat_sym_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,\n+\tvoid *op_cookie __rte_unused)\n {\n }\n \ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex 93666fdad..b9601c6c3 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -211,6 +211,12 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\t\t\trte_mempool_virt2iova(cookie) +\n \t\t\t\toffsetof(struct qat_sym_op_cookie,\n \t\t\t\tqat_sgl_dst);\n+\n+\t\tcookie->opt.spc_gmac.cd_phys_addr =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\t\topt.spc_gmac.cd_cipher);\n+\n \t}\n \n \t/* Get fw version from QAT (GEN2), skip if we've got it already */\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 23d059bf8..231b1640d 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -537,6 +537,8 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tstruct rte_crypto_sym_xform *xform, void *session_private)\n {\n \tstruct qat_sym_session *session = session_private;\n+\tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n+\tenum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;\n \tint ret;\n \tint qat_cmd_id;\n \n@@ -571,6 +573,10 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tret = qat_sym_session_configure_auth(dev, xform, session);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n+\t\tsession->is_single_pass_gmac =\n+\t\t\t qat_dev_gen == QAT_GEN3 &&\n+\t\t\t xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC &&\n+\t\t\t xform->auth.iv.length == QAT_AES_GCM_SPC_IV_SIZE;\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_CIPHER_HASH:\n \t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n@@ -706,8 +712,9 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n \tconst uint8_t *key_data = auth_xform->key.data;\n \tuint8_t key_length = auth_xform->key.length;\n-\tsession->aes_cmac = 0;\n \n+\tsession->aes_cmac = 0;\n+\tsession->auth_key_length = auth_xform->key.length;\n \tsession->auth_iv.offset = auth_xform->iv.offset;\n \tsession->auth_iv.length = auth_xform->iv.length;\n \tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n@@ -765,7 +772,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n \t\tif (session->auth_iv.length == 0)\n \t\t\tsession->auth_iv.length = AES_GCM_J0_LEN;\n-\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 011e5bb7a..72eee0659 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -36,7 +36,6 @@\n /* 96-bit case of IV for CCP/GCM single pass algorithm */\n #define QAT_AES_GCM_SPC_IV_SIZE 12\n \n-\n #define QAT_AES_HW_CONFIG_CBC_ENC(alg) \\\n \tICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \\\n \t\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT, \\\n@@ -86,11 +85,13 @@ struct qat_sym_session {\n \t\tuint16_t offset;\n \t\tuint16_t length;\n \t} auth_iv;\n+\tuint16_t auth_key_length;\n \tuint16_t digest_length;\n \trte_spinlock_t lock;\t/* protects this struct */\n \tenum qat_device_gen min_qat_dev_gen;\n \tuint8_t aes_cmac;\n \tuint8_t is_single_pass;\n+\tuint8_t is_single_pass_gmac;\n };\n \n int\n", "prefixes": [ "v3", "1/1" ] }